CN104465402B - A kind of semiconductor device fabrication processes - Google Patents
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- 238000005389 semiconductor device fabrication Methods 0.000 title claims abstract 3
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- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 17
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a kind of semiconductor device fabrication processes with super-junction structure, comprise the following steps：The Semiconductor substrate of one first conduction type is provided, the sacrifice layer with some first grooves is prepared on the Semiconductor substrate；Prepare the side wall that a side wall is covered in first groove；First groove is filled by the first epitaxial layer for preparing the second conduction type；Sacrifice layer and side wall are removed, to form second groove in the first epitaxial layer；Second groove is filled by the second epitaxial layer for preparing the first conduction type.The present invention is by using advanced amorphous carbon technique so that the N-type semiconductor material of super-junction structure and p-type semiconductor material interface are vertically smooth, and N-type semiconductor material keeps accurate consistent with p-type semiconductor material width, improves superjunction devices performance.And due to using advanced amorphous carbon technique, P posts and N posts width can be reduced to below 40nm, so as to substantially reduce cell density.
Description
Technical Field
The invention relates to the field of semiconductor preparation, in particular to a preparation process of a semiconductor device with a super junction structure.
Background
In the field of high voltage MOSFETs (400V to 1000V), a Super Junction (Super Junction) structure is increasingly receiving attention from the industry as an advanced drift region structure. The drift region of the super junction structure adopts an alternate PN junction structure to replace a single-conductivity-type drift region in a traditional high-voltage MOSFET, and a transverse electric field is introduced into the drift region, so that the drift region of the device can be completely depleted under a small turn-off voltage, and the breakdown voltage is only related to the thickness of a depletion layer and a critical electric field. Therefore, under the same withstand voltage, the doping concentration of the super junction structure drift region can be increased by one order of magnitude, and the on-resistance can be reduced by 5-10 times.
Power MOSFETs are typically used in devices that require power conversion and power amplification. For power conversion devices, a representative device is commercially available such as an electrical double Diffused MOSFET (DMOSFET). In conventional power transistors, most of the breakdown voltage BV is carried by the drift region, which typically needs to be lightly doped in order to provide a higher breakdown voltage BV for the device. However, it is not limited toLightly doped drift regions produce high on-resistance Rdson. For a typical transistor, the on-resistance and BV are simply considered2.5Is in direct proportion. Therefore, with the conventional transistor, as the breakdown voltage BV increases, the on-resistance also sharply increases.
The super junction device shown in fig. 1 is a well-known power semiconductor device. The super junction transistor proposes a method that can achieve a very low on-resistance while maintaining a very high off-state breakdown voltage BV. The super junction device contains alternating P-type and N-type doped columns formed in the drift region. When the MOSFET is switched off, the pillars can be fully depleted at a relatively low voltage, so that a high breakdown voltage can be maintained, since the pillars are laterally depleted and thus the entire P and N type pillars are substantially depleted. For super junctions, the on-resistance increases in proportion to the breakdown voltage BV, more slowly than in conventional semiconductor structures. Therefore, for the same high breakdown voltage BV, the super junction device has a lower on-resistance than the conventional MOSFET device. Or put another way, conversely, for a given on-resistance, a super junction device has a higher BV than a conventional MOSFET. More relevant information about superjunctions, such as "24 m Ω cm", published by Iwamoto, Sato et al in 2002 at pages 241-244 of the fourteenth power semiconductor device and integrated circuit seminar2The super junction device is presented in detail in 680V silicon super junction MOSFET ", which is hereby incorporated by reference in its entirety.
The structure of the super junction is mainly realized by two processes at present: the difficulty of multiple epitaxy and deep trench epitaxy is to form P-type and N-type semiconductor pillars with high aspect ratio. The multiple epitaxial method is to grow a drift region with required thickness on an N + type semiconductor substrate by adopting a multiple epitaxial mode, perform P-type ion implantation after each epitaxial process, and finally anneal to form a continuous P-type semiconductor column. The method has the advantages of complex process, long time consumption and high cost, and the area of the unit cell is difficult to reduce. The deep groove epitaxial method is to etch a deep groove on an N-type semiconductor epitaxial layer with a certain thickness and then carry out P-type semiconductor epitaxial growth in the deep groove. The method is simple compared with a multi-time epitaxy process method, the cost is reduced, but the filling is difficult during deep groove epitaxy, the difficulty of a groove process for etching a groove with a large depth-to-width ratio is high, and expensive equipment is needed.
Therefore, various novel process methods are provided based on deep trench epitaxy in some prior art, which can reduce the process difficulty of preparing the super junction, but the vertical side surface of the P-type semiconductor material is difficult to be flat in the P-type semiconductor material epitaxy process, so that the PN interface is also uneven after the N-type semiconductor material is epitaxial, and reverse voltage resistance is affected. In addition, it is difficult to precisely control the widths of the P-type semiconductor material and the N-type semiconductor material to be consistent through epitaxy, and it is difficult to reduce the cell area.
Disclosure of Invention
The invention provides a novel super-junction device preparation method, which not only effectively reduces the difficulty of a super-junction process, but also ensures that a PN interface is more vertical and smooth, and improves the reverse voltage endurance capacity of the device, and in order to realize the technical effect, the super-junction semiconductor device can be prepared by adopting the following steps: preparing a sacrificial layer with a plurality of first grooves above a semiconductor substrate of a first conductive type; preparing a side wall to cover the side wall of the first groove; preparing a first epitaxial layer of a second conduction type to fill the first groove; sequentially removing the sacrificial layer and the side walls to form a plurality of second grooves in the first epitaxial layer; and preparing a second epitaxial layer of the first conductivity type to fill the second trench.
In the above semiconductor device manufacturing process, the semiconductor substrate includes a bottom substrate and a buffer layer covering the bottom substrate; the ion doping concentration of the buffer layer is less than that of the bottom substrate.
In the above semiconductor device manufacturing process, the step of manufacturing the sacrificial layer having the plurality of first trenches includes: sequentially forming a sacrificial layer, a first dielectric layer, a second dielectric layer and photoresist on a semiconductor substrate from bottom to top; carrying out a photoetching process, and forming a plurality of openings in the photoresist, the first dielectric layer and the second dielectric layer;
and etching the sacrificial layer by using the opening to form a plurality of first grooves in the sacrificial layer.
In the above semiconductor device manufacturing process, the first dielectric layer is a DARC layer, and the second dielectric layer is a BARC layer.
In the above semiconductor device manufacturing process, after the plurality of first trenches are formed in the sacrificial layer, the photoresist and the second dielectric layer are removed, and the first dielectric layer on the top of the sacrificial layer is remained.
In the semiconductor device preparation process, the photoresist and the second dielectric layer are removed by adopting a wet etching process, but the removal mode of ashing treatment is not used, so that the sacrificial layer is prevented from being damaged.
In the above semiconductor device manufacturing process, after the plurality of first trenches are formed in the sacrificial layer, the photoresist, the second dielectric layer, and the first dielectric layer are removed.
In the semiconductor device manufacturing process, the photoresist, the second dielectric layer and the first dielectric layer are removed by a wet etching process, but the removal mode of ashing treatment is not used, so that the sacrificial layer is prevented from being damaged.
In the above semiconductor device manufacturing process, the sacrificial layer is amorphous carbon; the sacrificial layer is removed using an ashing process.
In the above semiconductor device manufacturing process, the sidewall is an oxide of silicon; after removing the sacrificial layer, the sidewall is removed by using a hydrogen fluoride solution.
In the above semiconductor device manufacturing process, the sidewall is a silicon nitride; after removing the sacrificial layer, the side wall is removed by using hot phosphoric acid solution.
In the semiconductor device manufacturing process, the thickness of the side wall is 5-20 μm.
In the semiconductor device manufacturing process, the ratio of the sum of the thicknesses of the sacrificial layer and the first dielectric layer to the width of the first trench is 5:1 to 1: 1.
In the semiconductor device manufacturing process, the ratio of the thickness of the sacrificial layer to the first trench is 5:1 to 1: 1.
In the semiconductor device manufacturing process, the epitaxial rate is not greater than 1.5 μm/min when the first epitaxial layer is manufactured.
In the semiconductor device manufacturing process, the epitaxial rate is not greater than 2 μm/min when the second epitaxial layer is manufactured.
In the above semiconductor device manufacturing process, the first conductivity type is N-type, and the second conductivity type is P-type.
In the semiconductor device manufacturing process, after the sacrificial layer and the side walls are removed, the formed second trench has a vertical side wall shape with a flat surface.
Drawings
The invention and its features, aspects and advantages will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
Fig. 1 is a cross-sectional view of a superjunction semiconductor device incorporating schottky contacts;
fig. 2A-2L are principal process diagrams of manufacturing a superjunction device in an embodiment of the invention;
fig. 3A-3C are partial process diagrams of the present invention for fabricating a superjunction device in one embodiment;
fig. 4-6 show three applications of the super junction device prepared by the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A semiconductor substrate having a first conductivity type is provided. Optionally, the semiconductor substrate includes a bottom substrate 110 and a buffer layer 120 covering the bottom substrate 110, and an ion doping concentration of the buffer layer 120 is smaller than that of the bottom substrate 110. A sacrificial layer 130, a first dielectric layer 140, a second dielectric layer 150, and a Photoresist (PR)160 are sequentially formed on the semiconductor substrate from bottom to top, and the structure formed can be as shown in fig. 2A. Optionally, but not limited to, the first dielectric layer 140 is a DARC (dielectric Anti-Reflective coating) layer, and the second dielectric layer 150 is a BARC (Bottom Anti-Reflective coating) layer. In some embodiments, a CVD process may be used to deposit a layer of SiON as the DARC layer described above. Optionally, but not limited to, the sacrificial layer 130 is Amorphous Carbon (AC). The thickness of the sacrificial layer 130 is required to be greater than or equal to the height of the P/N type semiconductor column required by the superjunction device, and the thicknesses of the first dielectric layer 140, the second dielectric layer 150 and the photoresist 160 are optimized according to the thickness requirement and the exposure requirement of the sacrificial layer 130.
In the present invention, the first dielectric layer 140 and the second dielectric layer 150 under the photoresist 160 are used to improve the photolithography effect and the precision. In the present invention, the reason why amorphous carbon is used as the sacrificial layer 130 is that: 1. the reflectivity is small, the PR thickness is favorably reduced, the PR collapse is avoided, and meanwhile the photoetching cost is reduced; 2. the reflectivity is small and can be less than 0.5 percent, so that the exposure precision can be greatly improved; 3. reducing the roughness of the boundary of the photoresist after exposure (LER), thereby improving the flatness of the boundary of the graph; 4. a larger etching process window can be realized; 5. has less CD (critical dimension) micro-loading effect (micro-loading effect) between different linear density areas; 6. the method is beneficial to improving the good CD consistency of AEI (After Etch Inspection) CDU (chemical dependent unit); 7. amorphous carbon is very easily removed by Ashing process (Ashing process), and the removal effect is very good without generating residue.
By using a photolithography process (including an exposure and development process) and an etching process, a plurality of trenches 210 are formed in the sacrificial layer 130, the first dielectric layer 140, the second dielectric layer 150 and the photoresist 160 on the buffer layer 120, and a first trench 220 is formed at the bottom of each trench 210 and between adjacent remaining sacrificial layers 130, as shown in fig. 2B. Due to the adoption of the advanced amorphous carbon process, the widths of the P column and the N column can be reduced to be less than 40nm, so that the area of a unit cell is greatly reduced.
And removing the photoresist 160 and the second dielectric layer 150 by using a wet etching process, as shown in fig. 2C. In order to preserve and protect the amorphous carbon layer (i.e., the sacrificial layer 130), an Ashing process (Ashing process) cannot be used to remove the photoresist. In this embodiment, a wet etching process may be optionally used to remove the photoresist 160 and the second dielectric layer 150, and leave the first dielectric layer 140 on top of the sacrificial layer 130, so as to prevent the sacrificial layer 130 from being damaged by etching.
In order to ensure the quality of the subsequent selective epitaxy, it is required that the aspect ratio of the trench 210 is between 5:1 and 1:1, i.e., the ratio of the thickness of the sacrificial layer 130 + the thickness of the first dielectric layer 140 (if the first dielectric layer 140 is not removed) to the width of the first trench 220 is between 5:1 and 1: 1.
Spacers 171 are formed in the first trench 220 covering the sidewalls of the remaining sacrificial layer 130. Specifically, the steps of preparing the sidewall 171 can be as shown in fig. 2D to fig. 2E: after the structure shown in fig. 2C is formed, a spacer material layer 170 is deposited or grown to cover the exposed surfaces of the sacrificial layer 130, the first dielectric layer 140 and the buffer layer 120; then, an anisotropic dry etching process may be used to etch the sidewall material layer 170, so as to remove the sidewall material layer 170 on top of the first dielectric layer 140 and the buffer layer 120, and form a sidewall 171 covering the sidewalls of the sacrificial layer 130 and the first dielectric layer 140.
Since the grain structure of amorphous carbon is close to that of conventional semiconductor materials (e.g., silicon, germanium), in order to ensure the quality of semiconductor epitaxy in the subsequent amorphous carbon trench (i.e., the first trench 220), a layer of material with a grain structure different from that of the semiconductor is deposited or grown, for example, silicon oxide (e.g., SiO)2) Or silicon nitride (e.g. Si)3N4) As a side wall material layer 170. Optionally, but without limitation, in FIG. 2E, sidewall 171 is preferably formed to a thickness of between 5-20 μm. It should be noted that the side wall 171 preferably covers the sidewalls of the sacrificial layer 130 and the first dielectric layer 140 at the same time, but in other embodiments, the etching reaction conditions may also be adjusted so that the side wall 171 only covers the sidewall of the sacrificial layer 130, which does not affect the present invention.
The first epitaxial layer 180 of the second conductive type opposite to the conductive type of the semiconductor substrate is prepared to fill the first trenches 220 in the sacrificial layer 130 and to make the first epitaxial layer 180 flush with the top surface of the sacrificial layer 130 by means of a planarization process, as shown with reference to fig. 2F-2G. Optionally, but not by way of limitation, selective epitaxy of P-type semiconductor material, i.e., one-sided, soft etching (soft etch) of the first epitaxial layer 180 at the trench sidewalls and top, and finally causing its epitaxial upper surface to exceed the upper surface of the first dielectric layer 140 (if the DARC layer is removed by the above step, the upper surface of the first epitaxial layer 180 exceeds the upper surface of the sacrificial layer 130). Wherein the soft-etch can be an instu extension + soft-etch machine with a Siconi module. To ensure the quality of the first epitaxial layer 180 in the trench, the epitaxial rate is required to be not more than 1.5 μm/min. After the structure shown in fig. 2F is formed, a CMP process may be used to polish and remove the first epitaxial layer 180, the sidewall 171 and the first dielectric layer 140 on the top surface of the sacrificial layer 130, so that the first epitaxial layer 180 is flush with the top surface of the sacrificial layer 130.
The sacrificial layer 130 and the sidewall spacers 171 are sequentially removed, and a second trench 230 is formed in the first epitaxial layer 180. First, an ashing process is used to remove the amorphous carbon sacrificial layer 130 to form a second trench 230 in the first epitaxial layer 180, as shown in fig. 2H. Then, a wet process is used to remove the sidewall 171, as shown in fig. 2I. If the material of the sidewall 171 is an oxide layer of silicon, a hydrogen fluoride diluent may be used to remove the sidewall 171, and if the material of the sidewall 171 is a nitride of silicon, a hot phosphoric acid solution may be used to remove the sidewall 171. Since the material of the sidewall 171 is greatly different from that of the first epitaxial layer 180, during the wet etching process, the etching solution can strip the sidewall 171 at a high etching rate, and the damage to the first epitaxial layer 180 is small, so that the P-type pillar is very vertical and flat. Please refer to fig. 2J, which is a perspective view of fig. 2I.
A second epitaxial layer 190 of the first conductivity type is prepared overlying the first epitaxial layer 180 to fill the second trenches 230 in the first epitaxial layer 180 and to cause the upper surface of the second epitaxial layer 190 to exceed the upper surface of the first epitaxial layer 180, as shown in fig. 2K. Optionally, but without limitation, the second epitaxial layer 190 of N-type may be prepared using a selective epitaxy process, while the epitaxy rate is required to be no greater than 2 μm/min in order to ensure the epitaxial quality of the N-type semiconductor in the P-type semiconductor column spacing. Then, a planarization process is performed to make the top surfaces of the second epitaxial layer 190 and the first epitaxial layer 180 flush, and then an annealing process is performed to form the overlapped N pillars 191 and P pillars 181 in the lateral direction, wherein the P/N interfaces are very vertical and flat, and the widths are kept precisely consistent. Compared with the traditional preparation method, the area of the cell is greatly reduced.
Meanwhile, in other embodiments of the present invention, after the structure shown in fig. 2B is formed, the first dielectric layer 140 and the second dielectric layer 150 on the top of the sacrificial layer 130 may also be removed, and then the sidewall spacer material layer 170 is deposited to cover the exposed surfaces of the sacrificial layer 130 and the buffer layer 120, so that optionally, the ratio of the thickness of the sacrificial layer 130 to the first trench 220 is preferably between 5:1 and 1:1, as shown in fig. 3A; then, removing the side wall material layer 170 on the top of the sacrificial layer 130 and the buffer layer 120 by using a plasma etching process to form the structure shown in fig. 3B; a first epitaxial layer 180 of the first conductivity type is then prepared to fill the trenches in the sacrificial layer, as shown in fig. 3C. After that, a polishing process is performed to make the top surface of the first epitaxial layer 180 flush with the top surface of the sacrificial layer 130, and the processes after fig. 3C are substantially the same as the processes described above, and reference may be made to fig. 2G to 2L and related descriptions, which are not repeated herein.
Example two
The embodiment provides a semiconductor device manufacturing process, which comprises the following steps:
step S1: a sacrificial layer is etched first, and a plurality of first trenches spaced apart from each other are formed in the sacrificial layer. Optionally, but not by way of limitation, the sacrificial layer is amorphous carbon and is etched using a photolithography and etching process to form a plurality of first trenches spaced apart from each other therein.
Step S2: and preparing a side wall to cover the side wall of the first groove. Optionally, but not limited to, the material of the sidewall spacer may be silicon oxide or silicon nitride. The preparation method of the side wall mainly comprises the following steps: firstly, a side wall material layer is deposited to cover the exposed surface of the device, and then the side wall material layer is etched by adopting an anisotropic etching process so as to reserve the side wall covered on the side wall of the first groove.
Step S3: a first epitaxial layer of a first conductivity type (e.g., P-type) is epitaxially grown in the first trench and then a polishing process is performed so that the first epitaxial layer is flush with the top surface of the sacrificial layer.
Step S4: and sequentially removing the sacrificial layer and the side walls, and forming a plurality of second grooves which are mutually separated in the first epitaxial layer. Optionally, but not by way of limitation, an ashing process is used to remove the sacrificial layer (i.e., amorphous carbon) followed by a wet etch process to remove the sidewalls. When the side wall is removed, different wet etching solutions are selected according to different materials, for example, when the side wall is made of silicon oxide, hydrogen fluoride diluent is used for removing the side wall; and when the side wall is silicon nitride, removing the side wall by using hot phosphoric acid liquid.
Step S5: a second epitaxial layer of a second conductivity type (e.g., N-type) opposite the first conductivity type is epitaxially grown in the second trenches and a grinding process is performed so that the second epitaxial layer is flush with the top surface of the first epitaxial layer. After the spacers are removed in the previous step S4, the vertical sidewall morphology of the formed second trench having a flat surface ensures that the PN junction at the interface between the second epitaxial layer of the second conductivity type and the first epitaxial layer of the first conductivity type in the second trench is a plane parallel junction. And the stand columns formed by second epitaxial layers with second conductivity types in the second trenches and the stand columns formed by first epitaxial layers with first conductivity types between the second trenches are alternately arranged at intervals to form a super junction structure.
In summary, due to the adoption of the technical scheme, compared with the prior art, the interface of the N-type semiconductor material and the P-type semiconductor material of the super junction structure is vertically flat by adopting the advanced amorphous carbon process, the widths of the N-type semiconductor material and the P-type semiconductor material are kept accurate and consistent, and the performance of the super junction device is improved. And because of adopting the advanced amorphous carbon technology, the width of the P column and the N column can be reduced to be less than 40nm, thereby greatly reducing the area of the unit cell. The invention has small process change and lower realization cost, and is suitable for popularization and production.
Fig. 4-6 outline the concept of improving both Vbd and Rdson of a power MOSFET using super junction devices, the application of which improves. According to the initial invention, which began in the early eighties of the twentieth century, the drift region of the superjunction transistor device was comprised of a plurality of alternating n and p semiconductor stripes. As long as the stripes are very narrow and the number of charge carriers in adjacent stripes is approximately equal, or a so-called charge balance is reached, it is possible to deplete the stripes at a relatively low voltage. Once depleted, the stripe appears as an intrinsic silicon, achieving an approximately uniform electric field distribution, and thus a high breakdown voltage. Both lateral super junction devices (fig. 4) and vertical super junction devices (fig. 5 and 6) can be fabricated using the super junction concept. Whereas lateral devices are more suitable for integrated circuits, vertical super junction devices are more suitable for discrete devices. Fig. 4 shows the arrangement of the stripes in the third dimension in the lateral configuration, called 3D Resurf. Fig. 5 and 6 show layouts suitable for vertical metal-oxide-semiconductor field effect transistors (Cool MOS, MDMesh). All super junction devices have the most prominent feature that they break the limit imposed on conventional non-super junction silicon devices.
The above description is of the preferred embodiment of the invention. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments to equivalent variations, without departing from the spirit of the invention, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (15)
1. A semiconductor device manufacturing process is characterized by comprising the following steps:
preparing a sacrificial layer with a plurality of first grooves above a semiconductor substrate of a first conductive type;
preparing a side wall to cover the side wall of the first groove;
preparing a first epitaxial layer of a second conduction type to fill the first groove;
sequentially removing the sacrificial layer and the side walls to form a plurality of second grooves in the first epitaxial layer;
preparing a second epitaxial layer of the first conductivity type to fill the second trench;
wherein,
the sacrificial layer is amorphous carbon and is removed by ashing treatment;
the side wall is made of silicon oxide, and after the sacrificial layer is removed, hydrogen fluoride solution and/or hot phosphoric acid solution are used for removing the side wall.
2. The process for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate comprises a base substrate and a buffer layer overlying the base substrate;
the ion doping concentration of the buffer layer is less than that of the bottom substrate.
3. The process for manufacturing a semiconductor device according to claim 1, wherein the step of preparing a sacrificial layer having a plurality of first trenches comprises:
sequentially forming a sacrificial layer, a first dielectric layer, a second dielectric layer and photoresist on a semiconductor substrate from bottom to top;
carrying out a photoetching process, and forming a plurality of openings in the photoresist, the first dielectric layer and the second dielectric layer;
and etching the sacrificial layer by using the opening to form a plurality of first grooves in the sacrificial layer.
4. The process for preparing a semiconductor device according to claim 3, wherein the first dielectric layer is a DARC layer and the second dielectric layer is a BARC layer.
5. The process for manufacturing a semiconductor device according to claim 3, wherein, after forming the first trenches in the sacrificial layer,
and removing the photoresist and the second dielectric layer, and keeping the first dielectric layer on the top of the sacrificial layer.
6. The process for manufacturing a semiconductor device according to claim 5, wherein the photoresist and the second dielectric layer are removed by a wet etching process without ashing, thereby preventing the sacrificial layer from being damaged.
7. The process for manufacturing a semiconductor device according to claim 3, wherein, after forming the first trenches in the sacrificial layer,
and removing the photoresist, the second dielectric layer and the first dielectric layer.
8. The process for manufacturing a semiconductor device according to claim 7, wherein the photoresist, the second dielectric layer and the first dielectric layer are removed by a wet etching process without ashing, thereby preventing the sacrificial layer from being damaged.
9. The process for manufacturing a semiconductor device according to claim 1, wherein the thickness of the sidewall is 5 to 20 μm.
10. The process for manufacturing a semiconductor device according to claim 5, wherein a ratio of a sum of thicknesses of the sacrificial layer and the first dielectric layer to a width of the first trench is between 5:1 and 1: 1.
11. The semiconductor device fabrication process of claim 7, wherein a ratio of a thickness of the sacrificial layer to a width of the first trench is between 5:1 and 1: 1.
12. The process for producing a semiconductor device according to claim 1, wherein the first epitaxial layer is produced at an epitaxial rate of not more than 1.5 μm/min.
13. The process for manufacturing a semiconductor device according to claim 1, wherein the second epitaxial layer is formed at an epitaxial rate of not more than 2 μm/min.
14. The process for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
15. The process for manufacturing a semiconductor device according to claim 1, wherein the second trench is formed to have a vertical sidewall profile with a flat surface after removing the sacrificial layer and the sidewall spacers.
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