CN104465402B - A kind of semiconductor device fabrication processes - Google Patents

Abstract

The invention discloses a process for preparing a semiconductor device with a super junction structure, comprising the following steps: providing a semiconductor substrate of a first conductivity type, and preparing a sacrificial layer having a plurality of first trenches on the semiconductor substrate; preparing The sidewall covers the sidewall of the first trench; preparing a first epitaxial layer of the second conductivity type to fill the first trench; removing the sacrificial layer and the sidewall to form a second trench in the first epitaxial layer groove; preparing a second epitaxial layer of the first conductivity type to fill the second groove. The present invention adopts advanced amorphous carbon technology to make the interface of N-type semiconductor material and P-type semiconductor material of super junction structure vertically flat, and the width of N-type semiconductor material and P-type semiconductor material remains accurate and consistent, which improves the performance of super-junction devices . And due to the use of advanced amorphous carbon technology, the width of P column and N column can be reduced to less than 40nm, thereby greatly reducing the cell area.

Description

A kind of semiconductor device manufacturing process

technical field

The invention relates to the field of semiconductor preparation, specifically, to a preparation process of a semiconductor device with a super junction structure.

Background technique

In the field of high-voltage MOSFETs (400V ~ 1000V), the super junction (Super Junction) structure, as an advanced drift region structure, has attracted more and more attention from the industry. The drift region of the super-junction structure uses an alternate PN junction structure to replace the single conductivity type drift region in the traditional high-voltage MOSFET, and a lateral electric field is introduced in the drift region, so that the device drift region can be completely exhausted at a small turn-off voltage, and the strike The breakdown voltage is only related to the thickness of the depletion layer and the critical electric field. Therefore, under the same withstand voltage, the doping concentration of the drift region of the super-junction structure can be increased by an order of magnitude, and the on-resistance can be reduced by 5 to 10 times.

Power MOSFETs are typically used in devices requiring power conversion and power amplification. For power conversion devices, representative devices available on the market such as electrical double-diffused MOSFETs (DMOSFETs). In conventional power transistors, most of the breakdown voltage BV is carried by the drift region. In order to provide a higher breakdown voltage BV for the device, the drift region generally requires light doping. However, a lightly doped drift region will produce a high on-resistance Rdson. For a typical transistor, the simplification is that the on-resistance is directly proportional to BV ^2.5 . Therefore, for conventional transistors, as the breakdown voltage BV increases, the on-resistance also increases sharply.

The super junction device shown in Fig. 1 is a well-known power semiconductor device. Superjunction transistors present a way to achieve very low on-resistance while maintaining a high off-state breakdown voltage BV. Superjunction devices contain alternating P-type and N-type doped pillars formed in the drift region. When the MOSFET is switched to the off state, the column can be completely depleted at a relatively low voltage, so that a high breakdown voltage can be maintained. Because the column is depleted laterally, the entire P and N-type columns are basically depleted. do. For superjunctions, the on-resistance increases proportional to the breakdown voltage BV, which increases more slowly than conventional semiconductor structures. Therefore, for the same high breakdown voltage BV, superjunction devices have lower on-resistance than conventional MOSFET devices. Or to put it another way, conversely, for a given on-resistance, superjunction devices have a higher BV than conventional MOSFETs. More relevant content about super junctions, such as "24mΩcm ² 680V silicon superjunction" disclosed by Iwamoto, Sato et al. Superjunction devices are presented in detail in "Junction MOSFET", the full text of which is hereby incorporated by reference.

At present, the structure of the super junction is mainly realized by two processes: multiple epitaxy and deep trench epitaxy. The difficulty in manufacturing lies in the formation of P-type semiconductor pillars and N-type semiconductor pillars with high aspect ratio characteristics. The multiple epitaxy method is to grow a drift region with a required thickness on the N+ type semiconductor substrate by multiple epitaxy, perform P-type ion implantation after each epitaxy, and finally anneal to form a continuous P-type semiconductor column. This method is complex in process, time-consuming and high in cost, and it is difficult to reduce the cell area. The deep groove epitaxy method is to etch a deep groove on an N-type semiconductor epitaxial layer of a certain thickness, and then carry out P-type semiconductor epitaxial growth in the deep groove. This method is simpler than the multiple epitaxy process, and also reduces the cost, but it is difficult to fill the deep trench epitaxy, and the process of etching a trench with a large aspect ratio is difficult and requires expensive equipment.

For this reason, in some existing technologies, various new process methods have been proposed on the basis of deep trench epitaxy, which can reduce the process difficulty of preparing super junctions, but it is difficult to make P-type semiconductor materials in the epitaxy process of P-type semiconductor materials. The vertical side of the material is flat, resulting in the unevenness of the PN interface after the epitaxy of the N-type semiconductor material, which will affect the reverse withstand voltage. In addition, it is difficult to accurately control the width of the P-type semiconductor material and the N-type semiconductor material to be consistent through epitaxy, and it is difficult to reduce the cell area.

Contents of the invention

The present invention provides a new type of super junction device preparation method, which not only effectively reduces the difficulty of the super junction process, but also ensures that the PN interface is more vertical and smooth, and improves the reverse withstand voltage capability of the device. In order to achieve the above technical effects, the following steps can be adopted To prepare a super junction semiconductor device: prepare a sacrificial layer with several first trenches on a semiconductor substrate of the first conductivity type; prepare a sidewall covering the sidewalls of the first trenches; prepare a first trench of the second conductivity type filling the first trenches with an epitaxial layer; removing the sacrificial layer and sidewalls in sequence to form several second trenches in the first epitaxial layer; preparing a second epitaxial layer of the first conductivity type to fill the second trenches filling.

In the manufacturing process of the above semiconductor device, the semiconductor substrate includes a base substrate and a buffer layer covering the base substrate; the ion doping concentration of the buffer layer is lower than the ion doping concentration of the base substrate.

The above-mentioned semiconductor device manufacturing process, wherein, the step of preparing the sacrificial layer having several first grooves includes: sequentially forming a sacrificial layer, a first dielectric layer, a second dielectric layer and a photolithography layer on the semiconductor substrate from bottom to top glue; performing a photolithography process to form a number of openings in the photoresist and the first dielectric layer and the second dielectric layer;

The sacrificial layer is etched using the openings to form a plurality of first trenches in the sacrificial layer.

In the above semiconductor device manufacturing process, the first dielectric layer is a DARC layer, and the second dielectric layer is a BARC layer.

In the manufacturing process of the above-mentioned semiconductor device, after forming several first trenches in the sacrificial layer, the photoresist and the second dielectric layer are removed, and the first dielectric layer on the top of the sacrificial layer remains.

In the manufacturing process of the above semiconductor device, the photoresist and the second dielectric layer are removed by a wet etching process, but ashing treatment is not used to avoid damage to the sacrificial layer.

In the manufacturing process of the above semiconductor device, after forming a plurality of first trenches in the sacrificial layer, the photoresist, the second dielectric layer and the first dielectric layer are removed.

In the manufacturing process of the above semiconductor device, the photoresist, the second dielectric layer and the first dielectric layer are removed by wet etching process, but the ashing treatment is not used to avoid damage to the sacrificial layer.

In the above semiconductor device manufacturing process, wherein the sacrificial layer is amorphous carbon; the sacrificial layer is removed by ashing treatment.

In the above manufacturing process of the semiconductor device, the sidewall is silicon oxide; after removing the sacrificial layer, the sidewall is removed by a hydrogen fluoride solution.

In the manufacturing process of the above semiconductor device, the sidewall is made of silicon nitride; after removing the sacrificial layer, the sidewall is removed by hot phosphoric acid solution.

In the above semiconductor device manufacturing process, the thickness of the sidewall is 5-20 μm.

In the above semiconductor device manufacturing process, the ratio of the sum of the thicknesses of the sacrificial layer and the first dielectric layer to the width of the first trench is between 5:1 and 1:1.

In the above semiconductor device manufacturing process, the ratio of the thickness of the sacrificial layer to the first trench is between 5:1 and 1:1.

In the above semiconductor device manufacturing process, when preparing the first epitaxial layer, the epitaxial rate is not greater than 1.5 μm/min.

In the above semiconductor device manufacturing process, when preparing the second epitaxial layer, the epitaxial rate is not greater than 2 μm/min.

In the above semiconductor device manufacturing process, the first conductivity type is N-type, and the second conductivity type is P-type.

In the manufacturing process of the above semiconductor device, after removing the sacrificial layer and the sidewall, the formed second trench has a vertical sidewall shape with a flat surface.

Description of drawings

The invention and its characteristics, shapes and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings are not intended to be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

Fig. 1 is a cross-sectional view of a super junction semiconductor device with a Schottky contact;

2A to 2L are the main process diagrams of preparing a super junction device in an embodiment of the present invention;

3A to 3C are partial process diagrams of preparing super junction devices in an embodiment of the present invention;

4 to 6 show three applications of the super junction device prepared by the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps and detailed structures will be provided in the following description, so as to illustrate the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

Embodiment one

A semiconductor substrate having a first conductivity type is provided. Optionally, the semiconductor substrate includes a base substrate 110 and a buffer layer 120 covering the base substrate 110 , and the ion doping concentration of the buffer layer 120 is lower than the ion doping concentration of the base substrate 110 . A sacrificial layer 130 , a first dielectric layer 140 , a second dielectric layer 150 and a photoresist (PR) 160 are sequentially formed on the semiconductor substrate from bottom to top, and the formed structure can be referred to as shown in FIG. 2A . Optionally but not limited, the first dielectric layer 140 is a DARC (dielectric Anti-reflective coating, dielectric anti-reflective coating) layer, and the second dielectric layer 150 is a BARC (Bottom Anti Reflective coating, bottom anti-reflective coating) layer. In some embodiments, a layer of SiON may be deposited by CVD process as the above-mentioned DARC layer. Optionally but not limited, the aforementioned sacrificial layer 130 is amorphous carbon (amorphous carbon, AC). The thickness of the sacrificial layer 130 needs to be greater than or equal to the height of the P/N type semiconductor column required by the super junction device, and the thicknesses of the first dielectric layer 140, the second dielectric layer 150 and the photoresist 160 depend on the thickness requirements of the sacrificial layer 130 and the exposure optimization is required.

In the present invention, the photolithography effect and precision are improved by means of the first dielectric layer 140 and the second dielectric layer 150 under the photoresist 160 . In the present invention, the reasons for using amorphous carbon as the sacrificial layer 130 are: 1. The reflectivity is small, which is beneficial to reduce the thickness of PR, avoid PR collapse, and reduce the cost of photolithography; 2. The reflectivity is small, which can be less than 0.5%. , so that the exposure accuracy can be greatly improved; 3. Reduce the photoresist boundary roughness (LER, line edge roughness) after exposure, thereby improving the flatness of the graphic boundary; 4. Can achieve a larger etching process window (etch process window); 5. , There is a small CD (critical dimension) microloading effect (micro-loading effect) between different line density areas; 6, it is beneficial to improve AEI (After Etch Inspection, inspection after etching) CDU (chemical dispense unit, chemical distribution unit) good CD consistency; 7. It is very easy to remove amorphous carbon through the ashing process (Ashing process), and the removal effect is very good without residue.

A plurality of grooves 210 are formed in the sacrificial layer 130, the first dielectric layer 140, the second dielectric layer 150 and the photoresist 160 above the buffer layer 120 by photolithography (including exposure and development) and etching processes, And at the bottom of the trench 210, a first trench 220 is formed between adjacent remaining sacrificial layers 130, as shown in FIG. 2B. Due to the advanced amorphous carbon process, the width of P-column and N-column can be reduced to less than 40nm, thereby greatly reducing the cell area.

The photoresist 160 and the second dielectric layer 150 are removed by a wet etching process, as shown in FIG. 2C . In order to preserve and protect the amorphous carbon layer (ie, the sacrificial layer 130 ), an ashing process (Ashing process) cannot be used to remove the photoresist. In this embodiment, a wet etching process may be used to remove the photoresist 160 and the second dielectric layer 150, and retain the first dielectric layer 140 on top of the sacrificial layer 130, so as to prevent the sacrificial layer 130 from being damaged by etching. .

In order to ensure the quality of subsequent selective epitaxy, the aspect ratio of the trench 210 is required to be between 5:1 and 1:1, that is, the thickness of the sacrificial layer 130 + the thickness of the first dielectric layer 140 (if the first dielectric layer 140 is not removed) The ratio to the width of the first trench 220 is between 5:1 and 1:1.

Sidewalls 171 covering the remaining sidewalls of the sacrificial layer 130 are formed in the first trench 220 . Specifically, the steps of preparing the sidewall 171 can refer to those shown in FIG. 2D to FIG. 2E: after forming the structure shown in FIG. layer 140 and the exposed surface of the buffer layer 120; then anisotropic dry etching process can be used to etch the sidewall material layer 170, and the first dielectric layer 140 and the sidewall material layer 170 on top of the buffer layer 120 removed to form sidewalls 171 covering the sidewalls of the sacrificial layer 130 and the first dielectric layer 140 .

Since the grain structure of amorphous carbon is close to conventional semiconductor materials (such as silicon and germanium), in order to ensure the quality of semiconductor epitaxy in the subsequent amorphous carbon trench (ie, the first trench 220), it is necessary to deposit or grow a layer of crystal grains. A material whose grain structure is quite different from that of a semiconductor, for example, silicon oxide (such as SiO ₂ ) or silicon nitride (such as Si ₃ N ₄ ) is used as the sidewall material layer 170 . Optionally but not limited, in FIG. 2E , the thickness of the formed side wall 171 is preferably between 5-20 μm. It should be noted that the sidewalls 171 preferably cover the sidewalls of the sacrificial layer 130 and the first dielectric layer 140 at the same time, but in other implementations, the etching reaction conditions can also be adjusted so that the sidewalls 171 only cover The sidewall of the sacrificial layer 130 does not affect the present invention.

Prepare the first epitaxial layer 180 of the second conductivity type opposite to that of the semiconductor substrate, so as to fill the first trench 220 located in the sacrificial layer 130, and make the first epitaxial layer 180 and the sacrificial layer The top surface of the layer 130 is flush, as shown in FIGS. 2F-2G . Optional but not limited, selective epitaxial P-type semiconductor material, that is, while epitaxial, soft etching (soft etch) the sidewall of the trench and the first epitaxial layer 180 on the top, and finally make its epitaxial upper surface exceed the first dielectric layer 140 (if the above steps remove the DARC layer, then the upper surface of the first epitaxial layer 180 exceeds the upper surface of the sacrificial layer 130 ). Among them, the soft-etch can choose the insitu epitaxy + soft-etch machine with Siconi module. In order to ensure the quality of the first epitaxial layer 180 in the trench, it is required that the epitaxial rate is not greater than 1.5 μm/min. After the structure shown in FIG. 2F is formed, the CMP process can be used for grinding to remove the first epitaxial layer 180, the sidewall 171 and the first dielectric layer 140 on the top surface of the sacrificial layer 130, so that the first epitaxial layer 180 and the sacrificial layer 130 top flush.

The sacrificial layer 130 and the sidewall 171 are sequentially removed to form a second trench 230 in the first epitaxial layer 180 . First, an ashing process is used to remove the sacrificial layer 130 of amorphous carbon to form a second trench 230 in the first epitaxial layer 180 , as shown in FIG. 2H . Afterwards, the sidewall 171 is removed by a wet process, as shown in FIG. 2I . If the material of the sidewall 171 is silicon oxide layer, the sidewall 171 can be removed by hydrogen fluoride diluent, and if the material of the sidewall 171 is silicon nitride, the sidewall 171 can be removed by hot phosphoric acid solution. Since the sidewall 171 is made of a material that is very different from the material of the first epitaxial layer 180, during the wet etching process, the etchant can strip the sidewall 171 at a relatively high etching rate, while the first The damage of the epitaxial layer 180 is relatively small, and the P-type columns are very vertical and flat at this time. Please continue to refer to accompanying drawing 2J, which is shown as a perspective view of Fig. 2I.

Prepare the second epitaxial layer 190 of the first conductivity type to cover the first epitaxial layer 180, so as to fill the second trench 230 in the first epitaxial layer 180, and make the upper surface of the second epitaxial layer 190 exceed the first The upper surface of the epitaxial layer 180 is shown in FIG. 2K . Optional but not limiting, the N-type second epitaxial layer 190 can be prepared by a selective epitaxy process, and at the same time, in order to ensure the quality of N-type semiconductor epitaxy in the interval between P-type semiconductor pillars, the epitaxy rate is required to be no greater than 2 μm/min. Afterwards, a planarization treatment is performed to make the top surfaces of the second epitaxial layer 190 and the first epitaxial layer 180 flush, and then an annealing treatment is performed to form overlapping N columns 191 and P columns 181 in the lateral direction, and the P/N The interface is very vertically flat, with a precise and consistent width. Compared with traditional preparation methods, the cell area is greatly reduced.

Meanwhile, in other embodiments of the present invention, after the structure shown in FIG. 2B is formed, the first dielectric layer 140 and the second dielectric layer 150 on the top of the sacrificial layer 130 can also be removed, and then a spacer material layer is deposited. 170 covers the exposed surface of the sacrificial layer 130 and the buffer layer 120, then optionally, the ratio of the thickness of the sacrificial layer 130 to the first groove 220 is preferably between 5:1 and 1:1, as shown in FIG. 3A shown; then the sacrificial layer 130 and the sidewall material layer 170 on top of the buffer layer 120 are removed by a plasma etching process to form the structure shown in FIG. The trenches are filled, as shown in Figure 3C. Afterwards, a grinding treatment is performed so that the top surface of the first epitaxial layer 180 is flush with the top surface of the sacrificial layer 130. The process after FIG. This will not be repeated.

Embodiment two

This embodiment provides a semiconductor device manufacturing process, including the following steps:

Step S1: firstly etching a sacrificial layer to form a plurality of first grooves spaced apart from each other in the sacrificial layer. Optionally but not limited, the sacrificial layer is made of amorphous carbon, and the sacrificial layer is etched by using photolithography and etching processes, so as to form a plurality of first trenches spaced apart therein.

Step S2: preparing a side wall to cover the side wall of the first trench. Optionally but not limited, the sidewall can be made of silicon oxide or silicon nitride. The steps of preparing the sidewall mainly include: first depositing a sidewall material layer to cover the exposed surface of the device, and then using an anisotropic etching process to etch the sidewall material layer to retain the Side walls on side walls.

Step S3: epitaxially growing a first epitaxial layer of a first conductivity type (for example, P-type) in the first trench, and then performing grinding treatment so that the first epitaxial layer is flush with the top surface of the sacrificial layer.

Step S4: removing the sacrificial layer and sidewalls in sequence, forming a plurality of second trenches spaced apart from each other in the first epitaxial layer. Optionally but not limited, the sacrificial layer (namely amorphous carbon) is removed by an ashing process first, and then the sidewall is removed by a wet etching process. Among them, when removing the sidewall, different wet etching solutions are selected according to different materials, for example, when the sidewall is silicon oxide, hydrogen fluoride dilution is used to remove the sidewall; For nitride, remove the sidewalls with hot phosphoric acid.

Step S5: Epitaxially grow a second epitaxial layer of a second conductivity type (for example, N-type) opposite to the first conductivity type in the second trench, and perform grinding treatment, so that the second epitaxial layer and the top of the first epitaxial layer Face flush. Wherein, after the sidewall is removed in the previous step S4, the vertical sidewall profile of the formed second trench with a flat surface ensures that the second epitaxial layer of the second conductivity type in the second trench is compatible with the first conductivity type. The type of PN junction at the interface of the first epitaxial layer is a plane-parallel junction. And by virtue of the pillars formed by the second epitaxial layer with the second conductivity type in the second trench, and the pillars formed by the first epitaxial layer with the first conductivity type between the second trenches, they are alternately arranged at intervals to form a super junction structure.

In summary, since the present invention adopts the above technical scheme, compared with the prior art, by adopting an advanced amorphous carbon process, the interface between the N-type semiconductor material and the P-type semiconductor material of the superjunction structure is vertically flat, and the N The width of the P-type semiconductor material and the P-type semiconductor material are kept exactly the same, which improves the performance of the superjunction device. And due to the use of advanced amorphous carbon technology, the width of P column and N column can be reduced to less than 40nm, thereby greatly reducing the cell area. The invention has little change in the manufacturing process, lower implementation cost, and is suitable for popularization and production.

Figure 4-6 outlines the concept of simultaneously improving Vbd and Rdson of power MOSFETs by superjunction devices using superjunction devices. According to the original invention starting in the early 1980s, the drift region of a superjunction transistor device is formed by a plurality of alternating n and p semiconductor stripes. As long as the stripes are very narrow and the number of charge carriers in adjacent stripes is approximately equal, or so-called charge balanced, it is possible to deplete the stripes at relatively low voltages. Once depleted, the stripe acts as if it were an intrinsic silicon, achieving a near-uniform electric field distribution and thus a high breakdown voltage. Both lateral superjunction devices (Figure 4) and vertical superjunction devices (Figures 5 and 6) can be fabricated using the superjunction concept. However, lateral devices are more suitable for integrated circuits, and vertical superjunction devices are more suitable for discrete devices. Figure 4 shows the arrangement of stripes in the third dimension in the transverse structure, which is called 3D Resurf. Figures 5 and 6 show layouts suitable for vertical Metal-Oxide-Semiconductor Field Effect Transistors (Cool MOS, MDMesh). The most outstanding feature shared by all superjunction devices is that they break the limits imposed on conventional non-superjunction silicon devices.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Under the circumstances of the technical solution of the invention, many possible changes and modifications can be made to the technical solution of the present invention by using the methods and technical contents disclosed above, or be modified into equivalent embodiments with equivalent changes, which does not affect the essence of the present invention . Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (15)

1. a semiconductor device preparation process, is characterized in that, comprises the steps: preparing a sacrificial layer having a plurality of first trenches on a semiconductor substrate of the first conductivity type; preparing a side wall to cover the side wall of the first groove; preparing a first epitaxial layer of the second conductivity type to fill the first trench; sequentially removing the sacrificial layer and sidewalls to form a plurality of second trenches in the first epitaxial layer; preparing a second epitaxial layer of the first conductivity type to fill the second trench; in, The sacrificial layer is amorphous carbon, and the sacrificial layer is removed by ashing treatment; The sidewall is silicon oxide, and after removing the sacrificial layer, hydrogen fluoride solution and/or hot phosphoric acid solution is used to remove the sidewall. 2. The semiconductor device manufacturing process according to claim 1, wherein the semiconductor substrate comprises a base substrate and a buffer layer covering the base substrate; The ion doping concentration of the buffer layer is smaller than the ion doping concentration of the underlying substrate. 3. The semiconductor device manufacturing process as claimed in claim 1, wherein the step of preparing a sacrificial layer with some first grooves comprises: sequentially forming a sacrificial layer, a first dielectric layer, a second dielectric layer and a photoresist on the semiconductor substrate from bottom to top; performing a photolithography process to form a number of openings in the photoresist and the first dielectric layer and the second dielectric layer; The sacrificial layer is etched using the openings to form a plurality of first trenches in the sacrificial layer. 4. The semiconductor device manufacturing process according to claim 3, wherein the first dielectric layer is a DARC layer, and the second dielectric layer is a BARC layer. 5. The semiconductor device manufacturing process according to claim 3, characterized in that, after forming some first trenches in the sacrificial layer, The photoresist and second dielectric layer are removed, leaving the first dielectric layer on top of the sacrificial layer. 6. The semiconductor device manufacturing process according to claim 5, characterized in that, the photoresist and the second dielectric layer are removed by a wet etching process, but the ashing process is not used to avoid damage to the sacrificial layer . 7. The semiconductor device manufacturing process according to claim 3, characterized in that, after forming some first grooves in the sacrificial layer, The photoresist, the second dielectric layer and the first dielectric layer are removed. 8. The semiconductor device manufacturing process according to claim 7, characterized in that, the photoresist, the second dielectric layer and the first dielectric layer are removed by a wet etching process, but the removal method without ashing treatment, Avoid damage to the sacrificial layer. 9. The semiconductor device manufacturing process according to claim 1, wherein the thickness of the sidewall is 5-20 μm. 10. The semiconductor device manufacturing process according to claim 5, wherein the ratio of the sum of the thicknesses of the sacrificial layer and the first dielectric layer to the width of the first trench is between 5:1 and 1:1. 11. The semiconductor device manufacturing process according to claim 7, wherein the ratio of the thickness of the sacrificial layer to the width of the first trench is between 5:1 and 1:1. 12. The process for manufacturing a semiconductor device according to claim 1, wherein when preparing the first epitaxial layer, the epitaxial rate is not greater than 1.5 μm/min. 13. The semiconductor device manufacturing process according to claim 1, wherein when preparing the second epitaxial layer, the epitaxial rate is not greater than 2 μm/min. 14. The process for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type. 15 . The semiconductor device manufacturing process according to claim 1 , wherein after removing the sacrificial layer and sidewalls, the formed second trench has a vertical sidewall shape with a flat surface.