CN104465350B - The manufacture method of trench polysilicon Si-gate - Google Patents
The manufacture method of trench polysilicon Si-gate Download PDFInfo
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- CN104465350B CN104465350B CN201410663738.6A CN201410663738A CN104465350B CN 104465350 B CN104465350 B CN 104465350B CN 201410663738 A CN201410663738 A CN 201410663738A CN 104465350 B CN104465350 B CN 104465350B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 101
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 60
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010936 titanium Substances 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 238000005275 alloying Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 13
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000004886 process control Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 6
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of manufacture method of trench polysilicon Si-gate, including step：It is formed at the polysilicon gate of PSU structures；Form the first oxide layer；Deposit first layer interlayer film；Cmp is carried out until polysilicon gate top surface exposes；Deposit Titanium simultaneously carries out alloying in polysilicon gate top surface formation titanium-silicon compound；Deposit second layer interlayer film.The present invention can reduce gate resistance, simplify peripheral control circuits, be accurately positioned alloy position, reduce the difficulty of Product Process control.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of trench polysilicon Si-gate
Manufacture method.
Background technology
Trench gate is often used in MOSFET, in order to reduce polysilicon gate resistance, is generally required in polysilicon gate table
Face forms metal silicide, generally titanium-silicon compound.It is the manufacturer of existing trench polysilicon Si-gate as shown in Figure 1A to Fig. 1 D
Structural representation in each step of method；Existing method comprises the following steps：
As shown in Figure 1A, groove is formed in silicon substrate 101 using lithographic etch process, fills polycrystalline in the trench afterwards
Si-gate 102, ordinary circumstance also needs first filling the polysilicon gate 102 in groove inner surface formation gate oxide.Need afterwards
Carving technology is returned using polysilicon to remove the polysilicon outside groove, the polysilicon gate 102 at the top of groove can also be gone
Except certain thickness, material is thus formed the structure of the recessed certain distance of the meeting of polysilicon gate 102 as shown in Figure 1A.
Polysilicon gate needs to form sufficiently thick oxide layer in monocrystalline silicon and polysilicon surface after returning quarter, as shown in Figure 1A, many
Crystal silicon grid form oxide layer 103 after 102 times quarters, and oxide layer 103 is covered in the surface of polysilicon gate 102 and with monocrystalline silicon
The surface of the silicon substrate 101 of structure, the surface of silicon substrate 101 includes the side being located in groove and the top table outside groove
Face.
As shown in Figure 1B, the oxide layer 103 on the surface of polysilicon gate 102 is etched totally afterwards, while to ensure in groove
The side of interior silicon substrate 101 has oxide layer 103 to protect.
As shown in Figure 1 C, Titanium deposit and alloying are finally carried out, polysilicon gate 102 can be alloyed to form titanium silication
Compound, and the silicon protected by oxide layer 103 is then got along well metallic titanium alloy, so directly remove non-alloyed metal (AM) titanium so as to
Form the titanium-silicon compound for being only located at the surface of polysilicon gate 102.
The manufacture of polysilicon gate of the top that above-mentioned steps are completed with titanium-silicon compound, deposits interlayer film, subsequently afterwards
Routinely step is carried out, and such as subsequently also needs to form contact hole, front metal layer etc..
In existing method, the top of polysilicon gate 102 needs the region to form titanium-silicon compound to need to use back the quarter carved
Etching technique is defined, and because Hui Keliang is not easily controlled, so technique is more complicated and unstable, state space is smaller, and this also can
So that gate resistance is larger.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of manufacture method of trench polysilicon Si-gate, can reduce grid electricity
Resistance, simplifies peripheral control circuits, is accurately positioned alloy position, reduces the difficulty of Product Process control.
In order to solve the above technical problems, the manufacture method for the trench polysilicon Si-gate that the present invention is provided comprises the following steps：
Step 1: forming the polysilicon gate that polysilicon erects (poly stand up, PSU) structure, the polysilicon gate is filled out
Fill in groove, the PSU structures are higher than the structure of surface of silicon for the top of the polysilicon gate.
Step 2: forming the first oxide layer, first oxide layer is covered in the top surface of the polysilicon gate, side wall
The surface of silicon outside surface and the polysilicon gate region.
Step 3: deposit first layer interlayer film；The first layer interlayer film is covered in the first oxidation layer surface and position
It is higher than the top surface of the polysilicon gate in the top surface of the first layer interlayer film outside the polysilicon gate region.
Step 4: carrying out cmp (CMP) until the polysilicon gate top surface exposes.
Step 5: deposit Titanium and carry out alloying, gold during alloying outside the polysilicon gate region
Category titanium is not alloyed, positioned at the metallic titanium alloy shape of the polysilicon gate top surface by first layer interlayer film protection
Into titanium-silicon compound, it will be removed without alloyed metal (AM) titanium.
Step 6: deposit second layer interlayer film.
Further improve be, after step one forms the polysilicon gate and step 2 formation first oxidation
Before layer, in addition to carry out body injection and body injection activation, carry out the processing step that source injection is source injection activation.
Further improve be, in the trench, the side of the polysilicon gate and lower surface and corresponding described
Isolation has gate dielectric layer between silicon substrate.
Further improve is that the polysilicon gate that the PSU structures are formed in step one comprises the following steps：
Step 11, the surface of silicon formation second dielectric layer, the thickness of the second dielectric layer is according to described more
The top of crystal silicon grid is determined higher than the height of surface of silicon.
Step 12, the region for defining using photoetching process the groove, the groove is sequentially etched using etching technics
The second dielectric layer and silicon in region form the groove.
Step 13, the polysilicon gate is formed by the trench fill.
Step 14, surface and the institute that the polysilicon gate is ground to using chemical mechanical milling tech the polysilicon gate
The surface for stating second dielectric layer is equal.
Step 15, the removal second dielectric layer form the polysilicon gate of the PSU structures.
The inventive method can use CMP works by forming the polysilicon gates of PSU structures after first layer interlayer film is formed
Artistic skill enough directly exposes polysilicon gate top surface, relative to the existing side that polycrystalline silicon gate surface is defined by returning carving technology
Method, the inventive method is easier and stably, can expand state space；Meanwhile, the inventive method is easier and stably, so can essence
The accurate size for defining polysilicon gate top surface, so as to the reduction for the cross section for realizing polysilicon gate, can be obtained smaller
Gate resistance.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Fig. 1 D are the structural representations in each step of manufacture method of existing trench polysilicon Si-gate；
Fig. 2 is the manufacture method of trench polysilicon Si-gate of the embodiment of the present invention；
Fig. 3 A- Fig. 3 E are the structural representations in each step of manufacture method of trench polysilicon Si-gate of the embodiment of the present invention；
Fig. 4 is the comparison curves of the polysilicon gate resistance of present invention method and existing method formation.
Embodiment
As shown in Fig. 2 being the manufacture method of trench polysilicon of embodiment of the present invention Si-gate 2；It is this as shown in Fig. 3 A to Fig. 3 E
Structural representation in each step of manufacture method of inventive embodiments trench polysilicon Si-gate 2；Trench polisilicon of the embodiment of the present invention
The manufacture method of grid 2 comprises the following steps：
Step 1: as shown in Figure 3A, forming the polysilicon gate 2 of PSU structures, the polysilicon gate 2 is filled in groove, described
PSU structures are higher than the structure on the surface of silicon substrate 1 for the top of the polysilicon gate 2.
Preferably, the polysilicon gate 2 for forming the PSU structures comprises the following steps：
Step 11, the surface of silicon substrate 1 formed second dielectric layer, the thickness of the second dielectric layer is according to described more
The top of crystal silicon grid 2 is determined higher than the height on the surface of silicon substrate 1.
Step 12, the region for defining using photoetching process the groove, the groove is sequentially etched using etching technics
The second dielectric layer and silicon in region form the groove.
Step 13, the polysilicon gate 2 is formed by the trench fill.
Step 14, using chemical mechanical milling tech by the polysilicon gate 2 be ground to the polysilicon gate 2 surface and
The surface of the second dielectric layer is equal.
Step 15, the removal second dielectric layer form the polysilicon gate 2 of the PSU structures.
Preferably, in the trench, the side of the polysilicon gate 2 and lower surface and the corresponding silicon substrate 1
Between isolation have gate dielectric layer as using thermal oxidation technology formation grid oxygen.
If the polysilicon gate 2 is to be applied to MOSFET element, also wrapped after step one forms the polysilicon gate 2
Include and carry out body injection and body injection activation, the injection of carry out the source i.e. processing step of source injection activation.
Step 2: as shown in Figure 3 B, forming the first oxide layer 3, first oxide layer 3 is covered in the polysilicon gate 2
Top surface, sidewall surfaces and the region of the polysilicon gate 2 outside the surface of the silicon substrate 1.
Step 3: as shown in Figure 3 B, deposit first layer interlayer film 4；The first layer interlayer film 4 is covered in first oxygen
The top surface for changing the surface of layer 3 and the first layer interlayer film 4 outside the region of polysilicon gate 2 is higher than the polysilicon
The top surface of grid 2.As described first layer interlayer film 4 can using Films Prepared by APCVD (APCVD) formation undoped with
Silica glass (USG) film.
Step 4: as shown in Figure 3 C, carrying out cmp (CMP) until the top surface of polysilicon gate 2 exposes.
Step 5: as shown in Figure 3 D, depositing Titanium and carrying out alloying, the area of polysilicon gate 2 is located at during alloying
First layer interlayer film 4 described in the overseas metallic titanium, which is protected, not to be alloyed, positioned at the top surface of polysilicon gate 2
Metallic titanium alloyization formation titanium-silicon compound 5, will be removed without alloyed metal (AM) titanium.
Step 6: deposit second layer interlayer film 6.The second layer interlayer film 6 can be boron-phosphorosilicate glass (BPSG).
Subsequent step is carried out using existing common process afterwards.If the polysilicon gate 2 is to be applied to MOSFET element,
The front that subsequent step is included in the silicon substrate 1 forms contact hole, and front metal layer.How MOSFET is VDMOS devices
Part, then also needing to be thinned to the back metal of silicon substrate 1 afterwards needs thickness, carries out the back side and injects to form drain region and back-side gold
Belong to layer.
Present invention method, can be after first layer interlayer film 4 be formed by forming the polysilicon gates 2 of PSU structures
Directly the top surface of polysilicon gate 2 can be exposed using CMP, relative to it is existing by return carving technology define polysilicon gate
The method on 2 surfaces, is difficult to control due to returning quarter thickness, so present invention method is easier and stably, can expand technique
Space；Simultaneously as present invention method is easier and stably, so 2 tables at the top of polysilicon gate can be defined accurately
The size in face, so as to the reduction for the cross section for realizing polysilicon gate 2, can obtain smaller gate resistance.As shown in figure 4, dotted line
Curve corresponding to frame 201 is the polysilicon gate resistance curve using existing method formation, and the curve corresponding to dotted line frame 202 is
The polysilicon gate resistance curve formed using present invention method, it is known that, the polysilicon gate resistance of existing method formation is about
For 20.2 milliohms (mohm), and the polysilicon gate resistance of present invention method formation is about 16 milliohms, so the present invention is real
Built-in chip type resistance can be greatly reduced by applying example.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (4)
1. a kind of manufacture method of trench polysilicon Si-gate, it is characterised in that comprise the following steps：
Step 1: forming the polysilicon gate of PSU structures, the polysilicon gate is filled in groove, and the PSU structures are the polycrystalline
The top of Si-gate is higher than the structure of surface of silicon；
Step 2: forming the first oxide layer, first oxide layer is covered in the top surface of the polysilicon gate, sidewall surfaces
And the surface of silicon outside the polysilicon gate region；
Step 3: deposit first layer interlayer film；The first layer interlayer film is covered in the first oxidation layer surface and positioned at institute
The top surface for stating the first layer interlayer film outside polysilicon gate region is higher than the top surface of the polysilicon gate；
Step 4: carrying out cmp until the polysilicon gate top surface exposes；
Step 5: deposit Titanium and carry out alloying, Titanium during alloying outside the polysilicon gate region
Protected and be not alloyed, positioned at the metallic titanium alloyization formation titanium of the polysilicon gate top surface by the first layer interlayer film
Silicon compound, will be removed without alloyed metal (AM) titanium；
Step 6: deposit second layer interlayer film.
2. the manufacture method of trench polysilicon Si-gate as claimed in claim 1, it is characterised in that：The polycrystalline is formed in step one
After Si-gate and before formation first oxide layer of step 2, in addition to carry out body injection and body injection activation, carry out source
Injection is the processing step of source injection activation.
3. the manufacture method of trench polysilicon Si-gate as claimed in claim 1, it is characterised in that：In the trench, it is described many
Isolation has gate dielectric layer between the side of crystal silicon grid and lower surface and the corresponding silicon substrate.
4. the manufacture method of trench polysilicon Si-gate as claimed in claim 1, it is characterised in that：The PSU is formed in step one
The polysilicon gate of structure comprises the following steps：
Step 11, the surface of silicon formation second dielectric layer, the thickness of the second dielectric layer is according to the polysilicon
The top of grid is determined higher than the height of surface of silicon；
Step 12, the region for defining using photoetching process the groove, the trench region is sequentially etched using etching technics
The second dielectric layer and silicon form the groove；
Step 13, the polysilicon gate is formed by the trench fill；
Step 14, the surface and described that the polysilicon gate is ground to using chemical mechanical milling tech the polysilicon gate
The surface of second medium layer is equal；
Step 15, the removal second dielectric layer form the polysilicon gate of the PSU structures.
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| CN201410663738.6A CN104465350B (en) | 2014-11-19 | 2014-11-19 | The manufacture method of trench polysilicon Si-gate |
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| CN201410663738.6A CN104465350B (en) | 2014-11-19 | 2014-11-19 | The manufacture method of trench polysilicon Si-gate |
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| CN104465350B true CN104465350B (en) | 2017-08-08 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521229A (en) * | 2008-03-02 | 2009-09-02 | 万国半导体股份有限公司 | Self-aligned trench accumulation mode field effect transistor structure and method of making same |
| US7994001B1 (en) * | 2010-05-11 | 2011-08-09 | Great Power Semiconductor Corp. | Trenched power semiconductor structure with schottky diode and fabrication method thereof |
| CN102637586A (en) * | 2011-02-12 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
| CN103367145A (en) * | 2012-03-27 | 2013-10-23 | 北大方正集团有限公司 | Trench VDMOS device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9947770B2 (en) * | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
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2014
- 2014-11-19 CN CN201410663738.6A patent/CN104465350B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521229A (en) * | 2008-03-02 | 2009-09-02 | 万国半导体股份有限公司 | Self-aligned trench accumulation mode field effect transistor structure and method of making same |
| US7994001B1 (en) * | 2010-05-11 | 2011-08-09 | Great Power Semiconductor Corp. | Trenched power semiconductor structure with schottky diode and fabrication method thereof |
| CN102637586A (en) * | 2011-02-12 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
| CN103367145A (en) * | 2012-03-27 | 2013-10-23 | 北大方正集团有限公司 | Trench VDMOS device and manufacturing method thereof |
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