CN104464669A - LCD driving circuit, LCD and LCD driving method - Google Patents
LCD driving circuit, LCD and LCD driving method Download PDFInfo
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- CN104464669A CN104464669A CN201410757661.9A CN201410757661A CN104464669A CN 104464669 A CN104464669 A CN 104464669A CN 201410757661 A CN201410757661 A CN 201410757661A CN 104464669 A CN104464669 A CN 104464669A
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Abstract
The invention relates to the technical field of LCD driving and provides an LCD driving circuit, an LCD and an LCD driving method. The LCD driving circuit comprises an LCD module connector M1 and a latch U1. A pin D0/SDA, a pin D1, a pin D2, a pin D3 and a pin D4 of the LCD module connector M1 are correspondingly connected with GPIO8, GPIO9, GPIO10, GPIO11 and GPIO12 respectively. A pin D5, a pin D6, a pin D7, a pin A0 and a pin LCD_RST are correspondingly connected with a pin Q0, a pin Q1, a pin Q2, a pin Q3 and a pin Q4 of the U1 respectively. The GPIO8, the GPIO9, the GPIO10, the GPIO11 and the GPIO12 are further correspondingly connected with the pin D0, the pin D1, the pin D2, the pin D3 and the pin D4 of the U1 respectively. A pin LCD_CS is correspondingly connected with an LCD_CS chip selection signal interface. A pin LCD_WR is correspondingly connected with an LCD_WR signal writing interface. A pin LE is connected with GPIO6. In this way, a field-type driving LCD or a dot-matrix-type driving LCD is realized, and selection of cost control and display velocity efficiency is facilitated.
Description
Technical field
The invention belongs to LCD Driving technique field, particularly relate to a kind of LCD driving circuit, LCD liquid crystal display and LCD driving method.
Background technology
Low cost liquid crystal display (Liquid Crystal Display, LCD) a large amount of uses of driver, for fixed telephone, cellular phone machine and other need low cost LCD display to provide more powerful function and more friendly interface as the electronic electric equipment of display terminal.
Similar low cost lcd driver can drive field formula, dot matrix two kinds of monochrome LCD display, and generally speaking, word section-type LCD many employings two-wire system serial line interface controls and transmits data, and lattice type LCD many employings parallel interface controls and transmit data.
Type of drive all existing defects of field formula and dot matrix, are specially:
Field formula drives and adopts two-wire system serial line interface to control and transmit data, and its circuit structure is simple, and cost is lower, but the speed that data transmit is comparatively slow, and efficiency is lower;
Dot matrix drives employing 8 bit parallel data interface, this 8 bit parallel data interface needs directly to be suspended on the parallel bus of system, its data transfer rate is very fast, but parallel interface signal wire comprises corresponding 12 signal line altogether such as 8 bit parallel data interfaces, reseting interface, write signal interface, need 12 GPIO signal wires accordingly, its cost increases greatly, and circuit structure is complicated, is difficult to realize.
Summary of the invention
The object of the present invention is to provide a kind of LCD driving circuit, being intended to solve field formula type of drive in prior art, to there is the speed that data transmit slower, the problem that efficiency is lower, and there is the comparatively large and complex structure of cost in dot matrix type of drive, is difficult to the problem realized.
The present invention is achieved in that LCD driving circuit, and described LCD driving circuit comprises LCD and shows module connector M1 and latch U1, wherein:
Described LCD shows module connector M1 and is provided with pin D0/SDA, pin D1/CLK, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin A0, pin LCD_CS, pin LCD_WR, pin LCD_RST, pin VDD and pin GND;
Described latch U1 is provided with pin D0, pin D1, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin OE, pin LE, pin Q0, pin Q1, pin Q2, pin Q3, pin Q4, pin Q5, pin Q6, pin Q7, pin VCC and pin GND;
Described LCD shows pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and is connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Described LCD shows pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
Described LCD shows the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node, second current node, 3rd current node, 4th current node and the 5th current node, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by described first current node, second current node, 3rd current node, 4th current node and the 5th current node and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
The pin LCD_CS correspondence that described LCD shows module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
The pin LE of described latch U1 connects latch control signal interface GPIO6.
As a kind of improved plan, the pin VDD correspondence that described LCD shows module connector M1 connects power input port V-IO, lead-in wire between described pin VDD and described power input port V-IO is provided with the 6th current node, the wire ground of described 6th current node.
As a kind of improved plan, between described 6th current node and wire ground end, be provided with filter capacitor C1.
As a kind of improved plan, the pin VCC correspondence of described latch U1 connects power input port V-IO, and the lead-in wire between described pin VDD and described power input port V-IO is provided with the 7th current node, the wire ground of described 7th current node.
As a kind of improved plan, between described 7th current node and wire ground end, be provided with filter capacitor C2.
As a kind of improved plan, described LCD shows the pin GND of module connector M1 and pin OE, the pin GND ground connection respectively of described latch U1.
Another object of the present invention is to provide the LCD liquid crystal display comprising LCD driving circuit.
Another object of the present invention is to provide the LCD driving method based on LCD driving circuit, described LCD driving circuit comprises LCD and shows module connector M1 and latch U1, and described LCD shows module connector M1 and is provided with pin D0/SDA, pin D1/CLK, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin A0, pin LCD_CS, pin LCD_WR, pin LCD_RST, pin VDD and pin GND; Described latch U1 is provided with pin D0, pin D1, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin OE, pin LE, pin Q0, pin Q1, pin Q2, pin Q3, pin Q4, pin Q5, pin Q6, pin Q7, pin VCC and pin GND, and described method comprises the steps:
(1), to the drive pattern of LCD display carry out model selection, the drive pattern of described LCD display comprises field formula and dot matrix;
(2), when the drive pattern of described LCD display is field formula, the pin D0/SDA showing module connector M1 to LCD by the simulation serial line interface GPIO8 of LCD driving circuit carries data-signal, the pin D1/CLK showing module connector M1 to LCD by simulation serial line interface GPIO9 carries serial clock signal, drives described LCD to show module connector M1;
(3), when the drive pattern of described LCD display is dot matrix, signal and reset signal the high three bit data signals in 8 driving data, command/data is selected to be transported on corresponding pin D0, the pin D1 of latch U1, pin D2, pin D3 and pin D4 respectively by simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Latch control signal interface GPIO6 carries latch signal to the pin LE of described latch U1, the high three bit data signals in described 8 driving data, command/data selection signal and reset signal is latched on pin Q0, the pin Q1 of described latch U1, pin Q2, pin Q3 and pin Q4 respectively;
The low five-digit number number of it is believed that in 8 driving data is delivered to described LCD and shows on pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 by described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
LCD_CS chip selection signal interface and LCD_WR write signal interface show the pin LCD_CS of module connector M1 and pin LCD_WR respectively to described LCD and carry low level, the pin Q0 of described latch U1 will be latched into, pin Q1, pin Q2, the high three bit data signals of pin Q3 and pin Q4, command/data selects signal and reset signal and described LCD to show the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, the low five-digit number number of it is believed that in described 8 driving data on pin D3 and pin D4 is written to described LCD in the lump and shows in module connector M1, drive LCD display.
As a kind of improved plan, also comprise the steps: before described step (1)
(101), described LCD is shown pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and be connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
(102), described LCD is shown pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
(103), described LCD is shown the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node, second current node, 3rd current node, 4th current node and the 5th current node, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by described first current node, second current node, 3rd current node, 4th current node and the 5th current node and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
(104) the pin LCD_CS correspondence, by described LCD showing module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
(105), the pin LE of described latch U1 is connected latch control signal interface GPIO6.
Module connector M1 and latch U1 is shown because LCD driving circuit comprises LCD, simulation serial line interface GPIO8 and simulation serial line interface GPIO9 shows the pin D0/SDA of module connector M1 and pin D1/CLK to LCD and carries data-signal and serial clock signal respectively, complete field formula to drive, by simulation serial line interface GPIO8 to simulation serial line interface GPIO12 by the high three bit data signals in 8 driving data, command/data selects signal and reset signal to be transported to the corresponding pin D0 of latch U1, pin D1, pin D2, on pin D3 and pin D4, and carry latch signal to latch by latch control signal interface GPIO6, simultaneously, the low five-digit number number of it is believed that in 8 driving data is delivered to the pin D0/SDA that LCD shows module connector M1 by simulation serial line interface GPIO8 to simulation serial line interface GPIO12, pin D1/CLK, pin D2, on pin D3 and pin D4, then by low level signal that pin LCD_WR carries, 8 driving data write LCD are shown in module connector M1, realize dot matrix and drive LCD display, extend LCD driving circuit, make it more flexible, conveniently select in cost control and display speed efficiency, there is provided convenient for user uses.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of LCD driving circuit provided by the invention;
Wherein, 10-first current node, 20-second current node, 30-the 3rd current node, 40-the 4th current node, 50-the 5th current node, 60-the 6th current node, 70-the 7th current node.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 shows the schematic diagram of the LCD driving circuit that the embodiment of the present invention provides, for convenience of explanation, part related to the present invention is only gived in figure, wherein, this LCD driving circuit is built in LCD liquid crystal display, drives accordingly the liquid crystal display of LCD liquid crystal display.
LCD driving circuit comprises LCD and shows module connector M1 and latch U1, wherein:
Described LCD shows module connector M1 and is provided with pin D0/SDA, pin D1/CLK, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin A0, pin LCD_CS, pin LCD_WR, pin LCD_RST, pin VDD and pin GND;
Described latch U1 is provided with pin D0, pin D1, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin OE, pin LE, pin Q0, pin Q1, pin Q2, pin Q3, pin Q4, pin Q5, pin Q6, pin Q7, pin VCC and pin GND;
Described LCD shows pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and is connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Described LCD shows pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
Described LCD shows the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node 10, second current node 20, 3rd current node 30, 4th current node 40 and the 5th current node 50, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by the first current node 10, second current node 20, 3rd current node 30, 4th current node 40 and the 5th current node 50 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
The pin LCD_CS correspondence that described LCD shows module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
The pin LE of described latch U1 connects latch control signal interface GPIO6.
Wherein, the pin VDD correspondence that LCD shows module connector M1 connects power input port V-IO, and the lead-in wire between pin VDD and described power input port V-IO is provided with the wire ground of the 6th current node the 60, six current node 60; Filter capacitor C1 is provided with between 6th current node 60 and wire ground end.
In this embodiment, the pin VCC correspondence of latch U1 connects power input port V-IO, lead-in wire between described pin VDD and described power input port V-IO is provided with the 7th current node 70, the wire ground of described 7th current node 70, is provided with filter capacitor C2 between the 7th current node 70 and wire ground end.
In the present invention, as shown in Figure 1, LCD shows the pin GND of module connector M1 and pin OE, the pin GND ground connection respectively of described latch U1.
Wherein, above-mentioned latch U1 can adopt model to be 74LS373 or 74HC373, can certainly adopt other models, not repeat them here, but not in order to limit the present invention.This latch U1 can expand the use of GPIO, reaches and saves sharing of GPIO resource.
In above-mentioned LCD driving circuit, according to the actual application environment of this LCD driving circuit, field formula drive pattern can be selected, also can selected element configuration drive pattern, wherein, concrete realizing is as described below:
(1) carry out model selection to the drive pattern of LCD display, the drive pattern of described LCD display comprises field formula and dot matrix;
(2) when the drive pattern of described LCD display is field formula, the pin D0/SDA showing module connector M1 to LCD by the simulation serial line interface GPIO8 of LCD driving circuit carries data-signal, the pin D1/CLK showing module connector M1 to LCD by simulation serial line interface GPIO9 carries serial clock signal, drives described LCD to show module connector M1;
That is, will simulate serial line interface GPIO8 as data line, and be used by simulation serial line interface GPIO9 as serial time clock line, structure is simple, and cost is lower.
(3) when the drive pattern of described LCD display is dot matrix, signal and reset signal the high three bit data signals in 8 driving data, command/data is selected to be transported on corresponding pin D0, the pin D1 of latch U1, pin D2, pin D3 and pin D4 respectively by simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Latch control signal interface GPIO6 carries latch signal to the pin LE of described latch U1, the high three bit data signals in described 8 driving data, command/data selection signal and reset signal is latched on pin Q0, the pin Q1 of described latch U1, pin Q2, pin Q3 and pin Q4 respectively;
The low five-digit number number of it is believed that in 8 driving data is delivered to described LCD and shows on pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 by simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
LCD_CS chip selection signal interface and LCD_WR write signal interface show the pin LCD_CS of module connector M1 and pin LCD_WR respectively to LCD and carry low level, the pin Q0 of described latch U1 will be latched into, pin Q1, pin Q2, the high three bit data signals of pin Q3 and pin Q4, command/data selects signal and reset signal and described LCD to show the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, the low five-digit number number of it is believed that in described 8 driving data on pin D3 and pin D4 is written to described LCD in the lump and shows in module connector M1, drive LCD display.
In embodiments of the present invention, in LCD driving method, comprise the processing mode of field formula drive pattern, also the processing mode of dot matrix drive pattern is comprised, wherein, dot matrix type of drive is divided into two large steps, namely respectively to high in 8 bit data signals three and low five process carrying out different flow process respectively, then the mode of write driver in the lump, does not repeat them here.
Wherein, also comprised the steps: before above-mentioned steps (1)
(101), described LCD is shown pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and be connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
(102), described LCD is shown pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
(103), described LCD is shown the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node, second current node, 3rd current node, 4th current node and the 5th current node, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by described first current node, second current node, 3rd current node, 4th current node and the 5th current node and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
(104) the pin LCD_CS correspondence, by described LCD showing module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
(105), the pin LE of described latch U1 is connected latch control signal interface GPIO6.
That is, complete building the framework that LCD drives, the structure that its concrete content can drive with reference to above-mentioned LCD, does not repeat them here, but not in order to limit the present invention.
In embodiments of the present invention, LCD driving circuit comprises LCD and shows module connector M1 and latch U1, simulation serial line interface GPIO8 and simulation serial line interface GPIO9 shows the pin D0/SDA of module connector M1 and pin D1/CLK to LCD and carries data-signal and serial clock signal respectively, complete field formula to drive, by simulation serial line interface GPIO8 to simulation serial line interface GPIO12 by the high three bit data signals in 8 driving data, command/data selects signal and reset signal to be transported to the corresponding pin D0 of latch U1, pin D1, pin D2, on pin D3 and pin D4, and carry latch signal to latch by latch control signal interface GPIO6, simultaneously, the low five-digit number number of it is believed that in 8 driving data is delivered to the pin D0/SDA that LCD shows module connector M1 by simulation serial line interface GPIO8 to simulation serial line interface GPIO12, pin D1/CLK, pin D2, on pin D3 and pin D4, then by low level signal that pin LCD_WR carries, 8 driving data write LCD are shown in module connector M1, realize dot matrix and drive LCD display, extend LCD driving circuit, make it more flexible, conveniently select in cost control and display speed efficiency, there is provided convenient for user uses.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1.LCD driving circuit, is characterized in that, described LCD driving circuit comprises LCD and shows module connector M1 and latch U1, wherein:
Described LCD shows module connector M1 and is provided with pin D0/SDA, pin D1/CLK, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin A0, pin LCD_CS, pin LCD_WR, pin LCD_RST, pin VDD and pin GND;
Described latch U1 is provided with pin D0, pin D1, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin OE, pin LE, pin Q0, pin Q1, pin Q2, pin Q3, pin Q4, pin Q5, pin Q6, pin Q7, pin VCC and pin GND;
Described LCD shows pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and is connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Described LCD shows pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
Described LCD shows the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node, second current node, 3rd current node, 4th current node and the 5th current node, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by described first current node, second current node, 3rd current node, 4th current node and the 5th current node and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
The pin LCD_CS correspondence that described LCD shows module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
The pin LE of described latch U1 connects latch control signal interface GPIO6.
2. LCD driving circuit according to claim 1, it is characterized in that, the pin VDD correspondence that described LCD shows module connector M1 connects power input port V-IO, lead-in wire between described pin VDD and described power input port V-IO is provided with the 6th current node, the wire ground of described 6th current node.
3. LCD driving circuit according to claim 2, is characterized in that, is provided with filter capacitor C1 between described 6th current node and wire ground end.
4. LCD driving circuit according to claim 1, it is characterized in that, the pin VCC correspondence of described latch U1 connects power input port V-IO, and the lead-in wire between described pin VDD and described power input port V-IO is provided with the 7th current node, the wire ground of described 7th current node.
5. LCD driving circuit according to claim 4, is characterized in that, is provided with filter capacitor C2 between described 7th current node and wire ground end.
6. the LCD driving circuit according to any one of claim 1 to 5, is characterized in that, described LCD shows the pin GND of module connector M1 and pin OE, the pin GND ground connection respectively of described latch U1.
7. comprise the LCD liquid crystal display of the LCD driving circuit described in any one of claim 1-6.
8. based on the LCD driving method of LCD driving circuit, it is characterized in that, described LCD driving circuit comprises LCD and shows module connector M1 and latch U1, and described LCD shows module connector M1 and is provided with pin D0/SDA, pin D1/CLK, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin A0, pin LCD_CS, pin LCD_WR, pin LCD_RST, pin VDD and pin GND; Described latch U1 is provided with pin D0, pin D1, pin D2, pin D3, pin D4, pin D5, pin D6, pin D7, pin OE, pin LE, pin Q0, pin Q1, pin Q2, pin Q3, pin Q4, pin Q5, pin Q6, pin Q7, pin VCC and pin GND, and described method comprises the steps:
(1), to the drive pattern of LCD display carry out model selection, the drive pattern of described LCD display comprises field formula and dot matrix;
(2), when the drive pattern of described LCD display is field formula, the pin D0/SDA showing module connector M1 to LCD by the simulation serial line interface GPIO8 of LCD driving circuit carries data-signal, the pin D1/CLK showing module connector M1 to LCD by simulation serial line interface GPIO9 carries serial clock signal, drives described LCD to show module connector M1;
(3), when the drive pattern of described LCD display is dot matrix, signal and reset signal the high three bit data signals in 8 driving data, command/data is selected to be transported on corresponding pin D0, the pin D1 of latch U1, pin D2, pin D3 and pin D4 respectively by simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
Latch control signal interface GPIO6 carries latch signal to the pin LE of described latch U1, the high three bit data signals in described 8 driving data, command/data selection signal and reset signal is latched on pin Q0, the pin Q1 of described latch U1, pin Q2, pin Q3 and pin Q4 respectively;
The low five-digit number number of it is believed that in 8 driving data is delivered to described LCD and shows on pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 by described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
LCD_CS chip selection signal interface and LCD_WR write signal interface show the pin LCD_CS of module connector M1 and pin LCD_WR respectively to described LCD and carry low level, the pin Q0 of described latch U1 will be latched into, pin Q1, pin Q2, the high three bit data signals of pin Q3 and pin Q4, command/data selects signal and reset signal and described LCD to show the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, the low five-digit number number of it is believed that in described 8 driving data on pin D3 and pin D4 is written to described LCD in the lump and shows in module connector M1, drive LCD display.
9. the LCD driving method based on LCD driving circuit according to claim 8, is characterized in that, also comprises the steps: before described step (1)
(101), described LCD is shown pin D0/SDA, the pin D1/CLK of module connector M1, pin D2, pin D3 and pin D4 and be connected respectively simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12;
(102), described LCD is shown pin D5, the pin D6 of module connector M1, pin D7, pin A0 and pin LCD_RST respectively with pin Q0, pin Q1, pin Q2, the pin Q3 of described latch U1 and pin Q4 is corresponding connects;
(103), described LCD is shown the pin D0/SDA of module connector M1, pin D1/CLK, pin D2, pin D3 and pin D4 and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, on connecting lead wire between simulation serial line interface GPIO11 and simulation serial line interface GPIO12, part is provided with the first current node, second current node, 3rd current node, 4th current node and the 5th current node, wherein, the pin D0 of described latch U1, pin D1, pin D2, pin D3 and pin D4 is respectively by described first current node, second current node, 3rd current node, 4th current node and the 5th current node and described simulation serial line interface GPIO8, simulation serial line interface GPIO9, simulation serial line interface GPIO10, simulation serial line interface GPIO11 and simulation serial line interface GPIO12 correspondence connect,
(104) the pin LCD_CS correspondence, by described LCD showing module connector M1 connects LCD_CS chip selection signal interface, and described pin LCD_WR correspondence connects LCD_WR write signal interface;
(105), the pin LE of described latch U1 is connected latch control signal interface GPIO6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410757661.9A CN104464669B (en) | 2014-12-10 | 2014-12-10 | LCD driving circuit, LCD and LCD driving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410757661.9A CN104464669B (en) | 2014-12-10 | 2014-12-10 | LCD driving circuit, LCD and LCD driving method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104464669A true CN104464669A (en) | 2015-03-25 |
| CN104464669B CN104464669B (en) | 2017-02-08 |
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| CN104464669B (en) | 2017-02-08 |
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