CN201004223Y - Interface host bridging device based on serial high-rank connection technology - Google Patents
Interface host bridging device based on serial high-rank connection technology Download PDFInfo
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- CN201004223Y CN201004223Y CNU2006201373293U CN200620137329U CN201004223Y CN 201004223 Y CN201004223 Y CN 201004223Y CN U2006201373293 U CNU2006201373293 U CN U2006201373293U CN 200620137329 U CN200620137329 U CN 200620137329U CN 201004223 Y CN201004223 Y CN 201004223Y
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Abstract
The utility model provides a serial higher order connection technology interface host bridging device, comprising a pair of physical units respectively connected with a serial higher order connection technology interface host device, providing the electric signal conversion and connection of the serial higher order connection technology interface; a pair of link units respectively connected with the physical units, receiving the data decoding and sending the data coding; a pair of transmission ports separately connected with the link units, controlling the connection of the SATA interface host to the device and the buffer and state of the serial higher order connection technology interface; furthermore, at least a bridging unit is provided to connect two transmission ports, providing the data transmission control of the serial higher order connection technology interface host to host, and thus communicating the serial higher order connection technology interface data between the two transmission ports; besides, the two serial higher order connection technology interface hosts realize a direct data transmission connection. Having the functions of providing a direct data and a signal sending, receiving and connecting, the utility model achieves the function of a high speed data or signal transmission.
Description
One, technical field
The utility model relates to the coupling arrangement of host-to-host, relates in particular to a kind of two data and the direct-connected serial high-order interconnection technique of signal interface main frame bridge-sets between SATA interface main frame that are applied to.
Two, background technology
Existing electronic installation host-to-host (HOST TO HOST) connected mode commonly used, be to connect by USB interface, though USB interface has the convenient linkage function of universalness, but there is the problem of transmission speed and frequency range in USB interface, even up-to-date USB2.0 interface, transmission speed also only can only reach about about 480Mbps, and it is new can't to have loaded gradually, as the high-speed information of main frame high capacity storage device or the transmission demand of signal; Again, the interface that possesses high-speed transfer speed, as existing serial high-order interconnection technique (SATA, Serial Advanced Technology Attachment) interface, though possess the transmission speed that reaches as high as 3Gbps arranged, but also only can only provide main frame to the transmission architecture between device, the connection mode of host-to-host can't be provided, thereby influence data or signal transmission speed and efficient between host-to-host.
Before preceding applying for a patent, aspect the case,, disclose the host-to-host bridge-set of typical USB interface pattern relevant as No. 390984 " the USB bridge-set of host-to-host " patent of invention case of TaiWan, China patent gazette that the applicant checks and approves in application; In addition, M272209 number " improvement of micro harddisk interface structure " novel patent case of TaiWan, China patent gazette, the main frame that discloses typical SATA interface also can't provide the linkage function of host-to-host to device syndeton and technology.
Three, utility model content
Fundamental purpose of the present utility model is to overcome the above-mentioned shortcoming that existing product exists, and provide a kind of serial high-order interconnection technique interface main frame bridge-set, the connection bridge-set of the direct host-to-host of SATA interface is provided, can provides as main frame the direct data between main frame, signal are passed the receipts linkage function.
Another purpose of the present utility model is to provide a kind of serial high-order interconnection technique interface main frame bridge-set, by by host apparatus the SATA interface between host apparatus directly being connected, reaches the high-speed information or the signal transfer function of host-to-host.
The purpose of this utility model is realized by following technical scheme.
The utility model serial high-order interconnection technique interface main frame bridge-set is characterized in that, comprising:
A pair of solid element, each solid element connect a serial high-order interconnection technique interface host apparatus respectively, and this solid element provides the conversion of serial high-order interconnection technique interface electrical signal and connects;
A pair of link unit, each link unit connects solid element, and this link unit receives the coding of data coding and the data of transmission, will decipher or encodes from the serial high-order interconnection technique interface data of solid element or signal respectively;
A pair of transmit port, each transmit port connects link unit, and this transmit port control SATA interface main frame is to the connection of device and buffer, the state of serial high-order interconnection technique interface;
At least one bridge-jointing unit, connect two transmit pories, Data Transmission Controlling for serial high-order interconnection technique interface host-to-host, serial high-order interconnection technique interface data between two transmit pories is interconnected, directly carries out data transmission between dual serial high-order interconnection technique interface host apparatus and connect.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein solid element connects a serial high-order interconnection technique port connections.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein solid element connects a serial high-order interconnection technique interface socket.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein the serial high-order interconnection technique interface host apparatus of solid element connection is a main frame.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein transmit port inside is provided with a control buffer.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein bridge-jointing unit comprises:
One data buffer, temporary for the buffering of the data transmission between two transmit pories, it is temporary and carry out data reading-writing under different clock pulse speed to make data can carry out asynchronous first in first out buffering;
One moderator connects this data buffer, and this moderator is for any one data access and data transfer sequence of arbitration two transmit pories, and the data transmission of controlling between two transmit pories connects sequencing;
One biography/admission controller connects data buffer, and this biography/admission controller is controlled data transmission and accepting state between two transmit pories according to the state of data impact damper.
Aforesaid serial high-order interconnection technique interface main frame bridge-set, wherein bridge-jointing unit is a microprocessor.
The beneficial effect of the utility model serial high-order interconnection technique interface main frame bridge-set is that it comprises a pair of solid element, link unit and transmit port, at least one bridge-jointing unit; Wherein, solid element connects a SATA interface host apparatus respectively, this link unit connects solid element and transmit port, and provide the encoding function of separating that passes the receipts data, this transmit port control SATA interface main frame is to the connection of device and the buffer of SATA interface, State Control, this bridge-jointing unit is connected between two transmit pories, make mutual transmission and the reception that to carry out data between two above-mentioned SATA interface main frames, and then order is connected between the SATA interface host apparatus of solid element and carries out direct signal, data passes to receive and connects, and reaches directly to provide directly to connect between two SATA interface main frames to carry out data, the effect of signal high-speed transfer.
Four, description of drawings
Fig. 1 is the utility model first embodiment square circuit diagram.
Fig. 2 is the utility model second embodiment square circuit diagram.
Fig. 3 is that the utility model the 3rd is implemented square circuit diagram.
Fig. 4 is that the utility model first is used illustration.
Fig. 5 is that the utility model second is used illustration.
Major label description in figure: 100 is serial high-order interconnection technique (SATA) interface main frame bridge-set, 10 solid elements, 20 solid elements, 30 link units, 40 link units, 50 transmit pories, 51 control buffers, 60 transmit pories, 61 control buffers, 70 bridge-jointing units, 71 data buffers, 72 moderators, 73 biography/admission controllers, 200 is SATA interface host apparatus, 300 is SATA interface host apparatus, 400 cables, 410 is the SATA port connections, 420 is the SATA port connections, 510 is the SATA interface socket, 520 is the SATA interface socket, 530 is the SATA interface cable, 540 is the SATA interface cable.
Five, embodiment
Consult shown in Figure 1, first embodiment for the utility model serial high-order interconnection technique (SATA) interface main frame bridge-set 100, wherein, this SATA interface main frame bridge-set 100 comprises a pair of solid element 10 and 20, link unit 30 and 40, transmit port 50 and 60, at least one bridge-jointing unit 70; This solid element 10 and 20 is for conversion of SATA interface electrical signal and connection, solid element 10 connects a SATA interface host apparatus 200, solid element 20 connects a SATA interface host apparatus 300, SATA interface host apparatus 200 and 300 pattern are not limit, be to be that example describes with the main frame in the utility model, other also should belong to technology category of the present utility model as the host apparatus that mobile computer or game host etc. has the SATA interface.
Above-mentioned link unit 30 connects solid element 10, link unit 40 connects solid element 20, link unit 30 and 40 provides the encoding function that receives data coding and the data of transmission, will decipher or encode from the SATA interface data of solid element 10 and 20 or signal respectively.
Above-mentioned transmit port 50 connects link unit 30, and this transmit port 60 connects link unit 40, and this transmit port 50 and 60 provides control to the connection of SATA interface host apparatus and buffer, the State Control of SATA interface.
Above-mentioned bridge-jointing unit 70, connect transmit port 50 and 60 respectively, this bridge-jointing unit 70 provides the Data Transmission Controlling of the host-to-host of SATA interface, the SATA interface data that makes this transmit port 50 and 60 is by bridge-jointing unit 70 transmission controls and can be interconnected, even this SATA interface host apparatus 200 and 300 can directly carry out data transmission and connect.
The pattern of above-mentioned bridge-jointing unit 70 is not limit, and is to be example with a microprocessor in first embodiment of the present utility model, and circuit that other is equivalent or device also should belong to technology category of the present utility model.
Consult shown in Figure 2, second embodiment for the utility model serial high-order interconnection technique (SATA) interface main frame bridge-set 100, promptly be provided with a control buffer 51 in this transmit port 50, be provided with a control buffer 61 in this transmit port 60, this controls buffer 51 and 61, internal reservoir SATA interface control standard is to carry out the SATA main frame to the connection of device and the buffer of SATA interface, the function of State Control.
Consult shown in the 3rd figure, the 3rd embodiment for the utility model serial high-order interconnection technique (SATA) interface main frame bridge-set 100, this bridge-jointing unit 70 comprises a data buffer 71, moderator (ARBITER) 72 and biography/admission controller 73, this data buffer 71 connects above-mentioned transmit port 50 and 60, this data impact damper 71 provides transmit port 50 and 60 s' data transmission buffering temporary, and is temporary and carry out data reading-writing under different clock pulse speed even data can be carried out first in first out (FIFO) buffering of asynchronous (asynchronous).
Above-mentioned moderator 72 connects data impact damper 71, moderator 72 provides arbitration transmit port 50 and 60 any one data access and as shown in Figure 2 control buffer 51 and 61 data transfer sequences, the sequencing that connects with control transmission port 50 and 60 s' data transmission.
Above-mentioned biography/admission controller 73 connects data buffer 71, this biography/admission controller 73 is according to the state of data buffer 71 and control transmission port 50 and 60 s' data transmission and accepting state, for example: when data buffer 71 has a full house, then make transmit port 50 and 60 under stopping to transmit SATA interface computer main frame 200 and 300 data, when data impact damper 71 vacancies, then make transmit port 50 and 60 under stopping to receive SATA interface computer main frame 200 and 300 data.
Consult shown in Figure 4, be first application examples of the present utility model, wherein, this serial high-order interconnection technique (SATA) interface main frame bridge-set 100 is changed to an integrated circuit and is buried underground and contain in a cable 400 by planning is whole, these cable 400 two ends are respectively equipped with a SATA port connections 410 and 420, these SATA port connections 410 inner solid elements 10 that connect SATA interface main frame bridge-set 100, the SATA port connections 420 inner solid elements 20 that connect SATA interface main frame bridge-set 100, be connected to above-mentioned SATA interface host apparatus 200 and 300 respectively by this SATA port connections 410 and 420, make the SATA interface host apparatus 200 and 300 of main frame pattern can directly directly carry out the transmission connection of data or signal by SATA interface main frame bridge-set 100 of the present utility model.
Consult shown in Figure 5, be second application examples of the present utility model, wherein, this serial high-order interconnection technique (SATA) interface main frame bridge-set 100 is a Relay connector pattern, be that solid element 10 and 20 is connected a SATA interface socket 510 and 520 respectively, 200 of this SATA interface socket 510 and SATA interface host apparatus are connected by a SATA interface cable 530, this SATA interface cable 530 is that existing SATA interface main frame is to the device stube cable, equally, 300 of SATA interface socket 520 and SATA interface host apparatus are connected by a SATA interface cable 540, in like manner, can reach the data transmission that makes SATA interface host apparatus 200 and 300 by SATA interface main frame bridge-set 100 of the present utility model and connect effect.
SATA interface main frame bridge-set of the present utility model shown in above Fig. 1 to Fig. 5, the related description that is disclosed and graphic wherein, only for ease of illustrating technology contents of the present utility model and technological means, the preferred embodiment that discloses, be not that the utility model is done any pro forma restriction, every foundation technical spirit of the present utility model all still belongs in the scope of technical solutions of the utility model any simple modification, equivalent variations and modification that above embodiment did.
Claims (7)
1, a kind of serial high-order interconnection technique interface main frame bridge-set is characterized in that, comprising:
A pair of solid element, each solid element connect a serial high-order interconnection technique interface host apparatus respectively, and this solid element provides the conversion of serial high-order interconnection technique interface electrical signal and connects;
A pair of link unit, each link unit connects solid element, and this link unit receives the coding of data coding and the data of transmission, will decipher or encodes from the serial high-order interconnection technique interface data of solid element or signal respectively;
A pair of transmit port, each transmit port connects link unit, and this transmit port control SATA interface main frame is to the connection of device and buffer, the state of serial high-order interconnection technique interface;
At least one bridge-jointing unit, connect two transmit pories, Data Transmission Controlling for serial high-order interconnection technique interface host-to-host, serial high-order interconnection technique interface data between two transmit pories is interconnected, directly carries out data transmission between dual serial high-order interconnection technique interface host apparatus and connect.
2, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that, described solid element connects a serial high-order interconnection technique port connections.
3, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that, described solid element connects a serial high-order interconnection technique interface socket.
4, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that, the serial high-order interconnection technique interface host apparatus that described solid element connects is a main frame.
5, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that, described transmit port inside is provided with a control buffer.
6, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that described bridge-jointing unit comprises:
One data buffer, temporary for the buffering of the data transmission between two transmit pories, it is temporary and carry out data reading-writing under different clock pulse speed to make data can carry out asynchronous first in first out buffering;
One moderator connects this data buffer, and this moderator is for any one data access and data transfer sequence of arbitration two transmit pories, and the data transmission of controlling between two transmit pories connects sequencing;
One biography/admission controller connects data buffer, and this biography/admission controller is controlled data transmission and accepting state between two transmit pories according to the state of data impact damper.
7, serial high-order interconnection technique interface main frame bridge-set according to claim 1 is characterized in that described bridge-jointing unit is a microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201373293U CN201004223Y (en) | 2006-09-22 | 2006-09-22 | Interface host bridging device based on serial high-rank connection technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201373293U CN201004223Y (en) | 2006-09-22 | 2006-09-22 | Interface host bridging device based on serial high-rank connection technology |
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| Publication Number | Publication Date |
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| CN201004223Y true CN201004223Y (en) | 2008-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2006201373293U Expired - Fee Related CN201004223Y (en) | 2006-09-22 | 2006-09-22 | Interface host bridging device based on serial high-rank connection technology |
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| CN (1) | CN201004223Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853235A (en) * | 2009-04-02 | 2010-10-06 | 鸿富锦精密工业（深圳）有限公司 | Switching device of serial ports |
| CN101556572B (en) * | 2008-04-07 | 2011-04-27 | 联咏科技股份有限公司 | Interface control circuit |
-
2006
- 2006-09-22 CN CNU2006201373293U patent/CN201004223Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556572B (en) * | 2008-04-07 | 2011-04-27 | 联咏科技股份有限公司 | Interface control circuit |
| CN101853235A (en) * | 2009-04-02 | 2010-10-06 | 鸿富锦精密工业（深圳）有限公司 | Switching device of serial ports |
| CN101853235B (en) * | 2009-04-02 | 2014-04-30 | 鸿富锦精密工业（深圳）有限公司 | Switching device of serial ports |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |