CN104464668B - control circuit for display - Google Patents
control circuit for display Download PDFInfo
- Publication number
- CN104464668B CN104464668B CN201410749031.7A CN201410749031A CN104464668B CN 104464668 B CN104464668 B CN 104464668B CN 201410749031 A CN201410749031 A CN 201410749031A CN 104464668 B CN104464668 B CN 104464668B
- Authority
- CN
- China
- Prior art keywords
- memory element
- switch
- control circuit
- data form
- switch unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000006870 function Effects 0.000 abstract description 2
- 101000746134 Homo sapiens DNA endonuclease RBBP8 Proteins 0.000 description 7
- 101000969031 Homo sapiens Nuclear protein 1 Proteins 0.000 description 7
- 102100021133 Nuclear protein 1 Human genes 0.000 description 7
- 238000010276 construction Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 101000869896 Homo sapiens Death-inducer obliterator 1 Proteins 0.000 description 3
- 101001053773 Homo sapiens Type I iodothyronine deiodinase Proteins 0.000 description 3
- 102100024063 Type I iodothyronine deiodinase Human genes 0.000 description 3
- 101001053754 Homo sapiens Type II iodothyronine deiodinase Proteins 0.000 description 2
- 102100024060 Type II iodothyronine deiodinase Human genes 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
nullThe present invention provides a kind of control circuit for display，This control circuit includes the first switch element、Second switch unit、First memory element、Second memory element、3rd memory element and the 4th memory element，This first memory element is for the forward scan coded data of storage the first data form，Second memory element is for the forward scan coded data of storage the second data form，3rd memory element is for the reverse scan coded data of storage the first data form，4th memory element is for the reverse scan coded data of storage the second data form，This first switch element is for selecting signal to select two memory element of corresponding data form from first to fourth memory element according to a data form，This second switch unit is for selecting signal to select a memory element of corresponding scanning direction further from two memory element selected by this first switch element according to a positive counter-scanning.This control circuit low cost, can realize several functions switching.
Description
Technical field
The present invention relates to field of display, particularly to a kind of for just realizing the picture to display
Counter-scanning switching and the control circuit of input data form switching.
Background technology
At present, to display, during such as liquid crystal display is developed, it usually needs use
Special timing controller realizes the switching of the positive counter-scanning to picture and enters input data form
Row switching.But, described special timing controller is that display development producer is the most outside
The chip factory in portion agrees to purchase gained, and polytropy is poor and relatively costly；And producer carries from display development
Going out demand and complete the supply of described special timing controller to chip manufacturer, its process is more time-consuming,
The construction cycle directly resulting in display is elongated, and to display development, producer brings economic loss.
Summary of the invention
In order to solve in prior art for realizing the switching of the positive counter-scanning to picture and to input data
The problem that timing controller development process is time-consuming, cost is high and polytropy is poor that form switches over,
Embodiments of the invention provide a kind of simple in construction, low cost and can realize the control of several functions switching
Circuit.
A kind of control circuit that embodiments of the invention are provided, for realizing the picture to display
Positive counter-scanning switching and input data form switching, this control circuit include the first switch element, the
Two switch elements, the first memory element, the second memory element, the 3rd memory element and the 4th storage
Unit, this first memory element for storage the first data form forward scan coded data, second
Memory element is for the forward scan coded data of storage the second data form, and the 3rd memory element is used for
Storing the reverse scan coded data of the first data form, the 4th memory element is for storage the second data
The reverse scan coded data of form, this first switch element is for selecting signal according to a data form
Two memory element of corresponding data form, this second switch is selected from first to fourth memory element
Unit is for selecting signal further from two selected by this first switch element according to a positive counter-scanning
Memory element selects a memory element of corresponding scanning direction.
Preferably, to set up this second switch unit final for this first switch element and this second switch unit
The electrical connection of this selected memory element and time schedule controller, so that this time schedule controller is according to
The coded data that this memory element selected by end is stored configures.
Preferably, this second switch unit receive further this time schedule controller provide a picture start
Signal, and select signal to provide correspondence according to this positive counter-scanning after receiving this picture commencing signal
Scanning direction control signal give the source electrode driver of this display and gate drivers.
Preferably, this second switch unit selects signal the most just providing according to this positive counter-scanning
The source drive of this display is given to scan control signal or the reverse scan control signal turned left from the right side
Device, it is provided that forward scan control signal from top to bottom or reverse scan control signal from bottom to up
To the gate drivers of this display.
Preferably, this first switch element, this second switch unit, this first memory element, this
Two memory element, the 3rd memory element, the 4th memory element and this time schedule controller are by string
Row bus connects.
Preferably, this first switch element and this second switch unit are respectively integrated switch chip.
Preferably, this first memory element, this second memory element, the 3rd memory element and should
4th memory element is respectively EEPROM.
Preferably, this first switch element and this second switch unit all use model to be G3204D61U
Integrated switch chip.
Preferably, this first memory element, this second memory element, the 3rd memory element and should
The storage chip that 4th memory element all uses model to be CAT24C16YI
Preferably, this first data form and the second data form are respectively 6, the data form of 8.
Due to above-mentioned control circuit only with first, second switch element and respectively storage have different number
According to form and first to fourth memory element of positive and negative scanning encoding data, select institute by twice
The memory element needed, to be supplied to general sequential control by the coded data that this memory element is stored
Device processed configures, and without using special timing controller to display picture just to realize
Counter-scanning switches and switches over input data form, is therefore effectively shortened the exploitation of display
Cycle.
Further, memory element, switch element and the sequencing contro that above-mentioned control circuit is used
Device all can use general standard chips, it is not necessary to special, and described control circuit simple in construction, because of
This cost is relatively low, reduces development cost and the construction cycle of display.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the present invention's
Technological means, can be practiced according to the content of description, and in order to make the present invention above-mentioned purpose,
Feature and advantage can become apparent from understandable, below especially exemplified by preferred embodiment, and coordinates accompanying drawing, in detail
It is described as follows.
Accompanying drawing explanation
The circuit block diagram of a kind of control circuit that Fig. 1 is provided by embodiments of the invention.
The particular circuit configurations schematic diagram that Fig. 2 is used by the control circuit shown in Fig. 1.
Fig. 3 to Fig. 5 is the operation principles schematic diagram of the control circuit shown in Fig. 2.
Detailed description of the invention
By further illustrating the technological means and merit that the present invention taked by reaching predetermined goal of the invention
Effect, below in conjunction with accompanying drawing and preferred embodiment, to according to liquid crystal indicator proposed by the invention and
Its detailed description of the invention, method, structure, feature and effect, after describing in detail such as.
Refer to the circuitry block of a kind of control circuit that Fig. 1, Fig. 1 are provided by embodiments of the invention
Figure.As it is shown in figure 1, control circuit 100 is for realizing the positive counter-scanning switching of the picture to display
And input data form switching, this control circuit 100 includes the first switch element U5, second switch
Unit U6, the first memory element U10, the second memory element U11, the 3rd memory element U12, the 4th
Memory element U13 and time schedule controller 110.This first to fourth memory element U10, U11, U12
And U13, the first switch element U5, can lead between second switch unit U6 and time schedule controller 110
Cross universal serial bus to connect.
In the present embodiment, the first memory element U10 is for the forward scan of storage the first data form
Coded data, the second memory element U11 is used for the forward scan coded data of storage the second data form,
3rd memory element U12 is for the reverse scan coded data of storage the first data form, the 4th storage
Unit U13 is for the reverse scan coded data of storage the second data form.This first to fourth storage
Unit U10, U11, U12 and U13 can be EEPROM (Electrically
Erasable Programmable Read-Only Memory, EEPROM).This first data form with
Second data form can be respectively 6 (bit), the data form of 8.
This first switch element U5 can use integrated switch chip, for receiving the number that external circuit provides
Select signal SEL according to form, and select signal SEL single from first to fourth storage according to this data form
Unit U10 to U13 selects two memory element of corresponding data form.Such as, set when these data
When form selects signal SEL to be high level, select the first data form；When this data form selects letter
When number SEL is low level, select the second data form, then received as this first switch element U5
When data form selects signal SEL to be high level, this first switch element U5 selects corresponding first data
First memory element U10 of form and the 3rd memory element U12, and set up the first memory element U10 and
3rd memory element U12 and the electrical connection of second switch unit U6, say, that this first switch is single
Unit U5 makes the first memory element U10 and the 3rd memory element U12 electric with second switch unit U6 respectively
Connect；When this first switch element U5 received data form selects signal SEL to be low level,
This first switch element U5 selects the second memory element U11 and the 4th storage of corresponding second data form
Unit U13, and set up the second memory element U11 and the 4th memory element U13 and second switch unit
The electrical connection of U6, say, that this first switch element U5 makes the second memory element U11 and the 4th deposit
Storage unit U13 electrically connects with second switch unit U6 respectively.In other embodiments, it is possible to set and work as
When this data form selects signal SEL to be low level, select the first data form；When this data form
When selection signal SEL is high level, select the second data form.
This second switch unit U6 can use integrated switch chip, is just providing for receiving external circuit
Counter-scanning selects signal REV, and selects signal REV further from this first switch according to this positive counter-scanning
Two memory element selected by unit U5 select a memory element of corresponding scanning direction.Such as,
Set when this positive counter-scanning selects signal REV as high level, select forward scan；Sweep when this is positive and negative
Retouch selection signal REV when being low level, select reverse scan, if then this first switch element U5 root
According to data form select signal SEL have selected corresponding first data form the first memory element U10 and
3rd memory element U12, and work as the positive counter-scanning selection signal REV that this second switch unit U6 is received
During for high level, this second switch unit U6 is from this first memory element U10 and the 3rd memory element U12
Middle the first memory element U10 selecting corresponding forward scan, and set up this first memory element U10 and time
The electrical connection of sequence controller 110, say, that this second switch unit U6 makes this first memory element
U10 electrically connects with time schedule controller 110；And work as the positive counter-scanning that this second switch unit U6 is received
Select signal REV when being low level, this second switch unit U6 from this first memory element U10 and the
Three memory element U12 select the 3rd memory element U12 of corresponding reverse scan, and sets up the 3rd and deposit
Storage unit U12 and the electrical connection of time schedule controller 110, say, that this second switch unit U6 makes
3rd memory element U12 electrically connects with time schedule controller 110.In like manner, if this first switch is single
Unit U5 selects signal SEL to have selected the second memory element of corresponding second data form according to data form
U11 and the 4th memory element U13, and work as the positive counter-scanning selection that this second switch unit U6 is received
When signal REV is high level, this second switch unit U6 deposits from this second memory element U11 and the 4th
Storage unit U13 selects the second memory element U11 of corresponding forward scan, and it is single to set up this second storage
The electrical connection of unit U11 and time schedule controller 110, say, that this second switch unit U6 make this
Two memory element U11 electrically connect with time schedule controller 110；And when this second switch unit U6 is received
Positive counter-scanning select signal REV when being low level, this second switch unit U6 is single from this second storage
Unit U11 and the 4th memory element U13 select the 4th memory element U13 of corresponding reverse scan, and builds
The electrical connection of vertical 4th memory element U13 and time schedule controller 110, say, that this second is opened
Closing unit U6 makes the 4th memory element U13 electrically connect with time schedule controller 110.In other embodiments
In, it is possible to set when this positive counter-scanning selects signal REV as low level, select forward scan；When
When this positive counter-scanning selects signal REV to be high level, select reverse scan.
It is to say, the first switch element U5 selects signal SEL from first to the according to this data form
Four memory element U10 to U13 select two memory element of corresponding data form, to complete first
Secondary selection；And this second switch unit U6 according to this positive counter-scanning select signal REV further from this
The storage selecting corresponding scanning direction in two memory element selected by one switch element U5 is single
Unit, to complete to select for the second time.By twice selection, the first switch element U5 and second switch unit
U6 sets up finally selected for this second switch unit U6 memory element and time schedule controller 110
Electrical connection, this time schedule controller 110 reads the coded data stored of this memory element, and according to
This coded data configures, to provide suitable image coding data and timing control signal to correspondence
The source electrode driver of display and gate drivers.
Additionally, this second switch unit U6 receives the picture that this time schedule controller 110 provides further
Commencing signal STV, and select signal REV to provide corresponding scanning direction to control letter according to this positive counter-scanning
Number give the source electrode driver of this display and gate drivers.Such as, connect as this second switch unit U6
Receiving this picture commencing signal STV, if this positive counter-scanning selects signal REV to be high level, this second is opened
Close unit U6 and forward scan control signal is provided, such as, scan control signal DIO1 from left to right is provided
To source electrode driver so that source electrode driver provides display data signal to aobvious according to order from left to right
Show panel, and provide scan control signal STVU from top to bottom to gate drivers so that this grid
Driver to display floater according to scanning direction from top to bottom；If this positive counter-scanning selects signal REV
For low level, this second switch unit U6 provides reverse scan control signal, such as, provides and turn left from the right side
Scan control signal DIO2 to source electrode driver so that this source electrode driver is according to the order turned left from the right side
There is provided display data signal to display floater, and provide scan control signal STVD from bottom to up to
Gate drivers so that this gate drivers to display floater according to scanning direction from bottom to up.
As it has been described above, this control circuit 100 only with first, second switch element U5, U6 and is divided
Cun Chu there be different data format and first to fourth memory element of positive and negative scanning encoding data
U10-U13, selects required memory element by twice, with the volume this memory element stored
Code data are supplied to time schedule controller 110 and configure, and without using special timing controller
Realize the switching of the positive counter-scanning to display picture and input data form is switched over, therefore
It is effectively shortened the construction cycle of display.Further, the storage that this control circuit 100 is used
Unit, switch element and time schedule controller all can use general standard chips, it is not necessary to special, and
And this control circuit 100 simple in construction, therefore cost is relatively low, reduce display development cost and
Construction cycle.
Refer to the particular circuit configurations that Fig. 2, Fig. 2 used by the control circuit 100 shown in Fig. 1 show
It is intended to.Such as, first, second switch element U5, U6 of this control circuit 100 can use the model to be
The integrated switch chip of G3204D61U, first to fourth memory element U10, U11, U12 and U13 can
Using model is the storage chip of CAT24C16YI.This first, second switch element U5, U6, first
Can pass through between the 4th memory element U10, U11, U12 and U13 and time schedule controller 110
I2C (Inter-Integrate Circuit) universal serial bus connects.
During as in figure 2 it is shown, this first to fourth memory element U10, U11, U12 and U13 all include
Clock end SCL, data terminal SDA, power end VCC, earth terminal VSS, write-protect end WP and three choosings
Select signal end A0, A1 and A2.These three select signal end A0, A1 and A2 all to connect with earth terminal VSS
Ground, this power end VCC is used for receiving voltage signal DVDD, and this clock end SCL and data terminal SDA uses
Electrically connect in the corresponding end with the first switch element U5.
This first switch element U5 and second switch unit U6 all includes power end V+, Enable Pin EN,
Input IN, earth terminal GND, first to fourth normally opened end NO1, NO2, NO3, NO4, first to
4th normal-closed end NC1, NC2, NC3, NC4 and the first to fourth the second common port COM1, COM2,
COM3、COM4.The power end V of this first switch element U5+For receiving voltage signal DVDD, enable
End EN and earth terminal GND ground connection, input IN is used for receiving data form and selects signal SEL, first,
Second normally opened end NO1, NO2 for respectively with clock end SCL and the data terminal of the first memory element U10
SDA electrically connect, the three, the 4th normally opened end NO3, NO4 for respectively with the second memory element U11
Clock end SCL and data terminal SDA electrical connection, the three, the 4th normal-closed end NC3, NC4 for respectively with
The clock end SCL of the 3rd memory element U12 and data terminal SDA electrical connection, first, second normal-closed end
NC1, NC2 are for electrically connecting with the clock end SCL and data terminal SDA of the 4th memory element U13 respectively.
The first common port COM1 of this first switch element U5 is used for and the first of second switch unit U6
Normally opened end NO1 electrically connects, and the second common port COM2 of this first switch element U5 is for opening with second
Close the second normally opened end NO2 electrical connection of unit U6, the 3rd common port COM3 of this first switch element U5
Electrically connect for the first normal-closed end NC1 with second switch unit U6, this first switch element U5's
4th common port COM4 is for electrically connecting with the second normal-closed end NC2 of second switch unit U6.
The power end V of this second switch unit U6+For receiving voltage signal DVDD, Enable Pin EN with
Earth terminal GND ground connection, input IN is used for receiving positive counter-scanning and selects signal REV, the 3rd normally opened end
NO3 and the 3rd normal-closed end NC3 is for providing scan control signal DIO1 from left to right respectively and from the right side
The scan control signal DIO2 turned left to source electrode driver, the 4th normally opened end NO4 and the 4th normal-closed end NC4
For providing scan control signal STVU from top to bottom and scan control signal from bottom to up respectively
STVD is to gate drivers, and the first common port COM1 is used for providing serial clock signal SCL ' to sequential
Controller 110, the second common port COM2 is used for providing serial data signal SDA ' to time schedule controller
110, the 3rd common port COM3 is used for receiving voltage signal DVDD, and the 4th common port COM4 is used for receiving
The picture commencing signal STV that time schedule controller 110 provides.
Refer to the operation principles that Fig. 3 to Fig. 5, Fig. 3 to Fig. 5 are the control circuit 100 shown in Fig. 2
Schematic diagram.Set when data form selects signal SEL as high level, select the first data form；
When this data form selects signal SEL to be low level, select the second data form；Set when positive and negative
When scanning selects signal REV to be high level, select forward scan；When this positive counter-scanning selects signal REV
During for low level, select reverse scan.
Fig. 3 show when this first switch element U5 received data form selects signal SEL and the
When the positive counter-scanning that two switch element U6 are received selects signal REV to be high level, this first switch
Unit U5 and second switch unit U6 is by selecting the first memory element U10 for twice and setting up first
Data channel between memory element U10 and time schedule controller 110 (see Fig. 2).Specifically, when
This first switch element U5 received data form selects signal SEL when being high level, and this first is opened
Close unit U5 by connecting the second common port COM2 and the second normally opened end NO2 to select storage to have first
First memory element U10 of data format coded data, this first switch element U5 is by connecting the 4th
Common port COM4 and the 4th normal-closed end NC4 is to select to store equally to have the first data format coded data
3rd memory element U12.The second normally opened end NO2 and first storage due to this first switch element U5
Unit U10 data terminal SDA electrical connection, the second common port COM2 of this first switch element U5 with
The second normally opened end NO2 electrical connection of second switch unit U6, the data terminal of this first memory element U10
SDA is electrically connected to the second normally opened end NO2 of this second switch unit U6 via this first switch element U5.
The 4th normal-closed end NC4 and the data terminal SDA of the 3rd memory element U12 due to this first switch element U5
Electrical connection, the second of the 4th common port COM4 and second switch unit U6 of this first switch element U5
Normal-closed end NC2 electrically connects, and the data terminal SDA of the 3rd memory element U12 is single via this first switch
Unit U5 is electrically connected to the second normal-closed end NC2 of this second switch unit U6.
Now, when the positive counter-scanning that second switch unit U6 is received selects signal REV to be high level,
This second switch unit U6 is by electrically connecting the second common port COM2 and the second normally opened end NO2 to select
Storage has the first memory element U10 of forward scan coded data.Due to second switch unit U6
Two common port COM2 be used for providing serial data signal SDA ' to time schedule controller 110, so far, the
Data channel between one memory element U10 and time schedule controller 110 is single via first, second switch
Unit U5, U6 set up.
Fig. 4 show when this first switch element U5 received data form selects signal SEL and the
When the positive counter-scanning that two switch element U6 are received selects signal REV to be high level, this first switch
Unit U5 and second switch unit U6 is by selecting the first memory element U10 for twice and setting up first
Clock lane between memory element U10 and time schedule controller 110 (see Fig. 2).Specifically, when
This first switch element U5 received data form selects signal SEL when being high level, and this first is opened
Close unit U5 by connecting the first common port COM1 and the first normally opened end NO1 to select storage to have first
First memory element U10 of data format coded data, this first switch element U5 is by connecting the 3rd
Common port COM3 and the 3rd normal-closed end NC3 is to select to store equally to have the first data format coded data
3rd memory element U12.The first normally opened end NO1 and first storage due to this first switch element U5
Unit U10 clock end SCL electrical connection, the first common port COM1 of this first switch element U5 with
The first normally opened end NO1 electrical connection of second switch unit U6, the clock end of this first memory element U10
SCL is electrically connected to the first normally opened end NO1 of this second switch unit U6 via this first switch element U5.
The 3rd normal-closed end NC3 and the clock end SCL of the 3rd memory element U12 due to this first switch element U5
Electrical connection, the first of the 3rd common port COM3 and second switch unit U6 of this first switch element U5
Normal-closed end NC1 electrically connects, and the clock end SCL of the 3rd memory element U12 is single via this first switch
Unit U5 is electrically connected to the first normal-closed end NC1 of this second switch unit U6.
Now, when the positive counter-scanning that second switch unit U6 is received selects signal REV to be high level,
This second switch unit U6 is by electrically connecting the first common port COM1 and the first normally opened end NO1 to select
Storage has the first memory element U10 of forward scan coded data.Due to second switch unit U6
One common port COM1 be used for providing serial clock signal SCL ' to time schedule controller 110, so far, the
Clock lane between one memory element U10 and time schedule controller 110 is single via first, second switch
Unit U5, U6 set up.
Data channel between the first memory element U10 and time schedule controller 110 and clock lane warp
After having been set up by first, second switch element U5, U6, time schedule controller 110 just can be by being somebody's turn to do
Data channel and clock lane read the coded data of the first memory element U10 to configure, to carry
Source electrode driver and the grid of corresponding display are given for suitable image coding data and timing control signal
Driver.
Additionally, refer to Fig. 5, the 3rd common port COM3 of this second switch unit U6 receives voltage letter
The picture that number DVDD, the 4th common port COM4 receive time schedule controller 110 (see Fig. 2) and provide starts
Signal STV, the positive counter-scanning received as this second switch unit U6 selects signal REV to be high level
Time, this second switch unit U6 electrical connection the 3rd common port COM3 and the 3rd normally opened end NO3 is with by electricity
Pressure signal DVDD carries through the 3rd normally opened end NO3 as forward scan control signal DIO1 from left to right
Supply source driver, so that source electrode driver provides display data letter according to order from left to right
Number give display floater；This second switch unit U6 electrical connection the 4th common port COM4 and the 4th normally opened end
NO4 is to provide forward scan control signal STVU from top to bottom to drive to grid through the 4th normally opened end NO4
Dynamic device so that this gate drivers to display floater according to scanning direction from top to bottom.
This control circuit 100 is utilized to select other different data formats and positive and negative scanning encoding data
Working method is similar to the selection mode of above-mentioned first data form and forward scan, the most superfluous at this
State.
Being described in detail control circuit provided by the present invention above, it passes through specific embodiment
Principle and embodiment to the present invention are set forth, and the explanation of above example is only intended to help
Understand method and the core concept thereof of the present invention, but be not limited to the present invention, any familiar
Professional and technical personnel, in the range of without departing from technical solution of the present invention, when available above-mentioned
The technology contents disclosed is made a little change or is modified to the Equivalent embodiments of equivalent variations, as long as
It is that the technical spirit of the foundation present invention is to above example without departing from technical solution of the present invention content
Any simple modification, equivalent variations and the modification made, all still falls within technical solution of the present invention
In the range of.
Claims (10)
1. a control circuit, for realizing the switching of positive counter-scanning and the input of the picture to display
Data form switches, it is characterised in that this control circuit includes the first switch element, second switch list
Unit, the first memory element, the second memory element, the 3rd memory element and the 4th memory element, should
First memory element is for the forward scan coded data of storage the first data form, the second memory element
For storing the forward scan coded data of the second data form, the 3rd memory element is used for storage first
The reverse scan coded data of data form, the 4th memory element is anti-for storage the second data form
To scanning encoding data, this first switch element for according to one data form select signal from first to
Selecting two memory element of corresponding data form in 4th memory element, this second switch unit is used for
Select signal further from two memory element selected by this first switch element according to a positive counter-scanning
The middle memory element selecting corresponding scanning direction.
Control circuit the most according to claim 1, it is characterised in that this first switch element with
This second switch unit sets up this finally selected memory element of this second switch unit and a sequential control
The electrical connection of device processed, so that what this time schedule controller was stored according to final this selected memory element
Coded data configures.
Control circuit the most according to claim 2, it is characterised in that this second switch unit enters
One step receives the picture commencing signal that this time schedule controller provides, and starts letter receiving this picture
Signal is selected to provide the scanning direction control signal of correspondence to this display according to this positive counter-scanning after number
Source electrode driver and gate drivers.
Control circuit the most according to claim 3, it is characterised in that this second switch unit root
Signal is selected to provide forward scan control signal from left to right or turn left from the right side according to this positive counter-scanning
Reverse scan control signal gives the source electrode driver of this display, it is provided that forward scan control from top to bottom
Signal processed or reverse scan control signal from bottom to up give the gate drivers of this display.
Control circuit the most according to claim 2, it is characterised in that this first switch element,
This second switch unit, this first memory element, this second memory element, the 3rd memory element,
4th memory element and this time schedule controller are connected by universal serial bus.
Control circuit the most according to claim 1, it is characterised in that this first switch element and
This second switch unit is respectively integrated switch chip.
Control circuit the most according to claim 1, it is characterised in that this first memory element,
This second memory element, the 3rd memory element and the 4th memory element are respectively electric erasable and programmable
Journey read only memory.
Control circuit the most according to claim 1, it is characterised in that this first switch element and
The integrated switch chip that this second switch unit all uses model to be G3204D61U.
Control circuit the most according to claim 1, it is characterised in that this first memory element,
This second memory element, the 3rd memory element and the 4th memory element all use the model to be
The storage chip of CAT24C16YI.
Control circuit the most according to claim 1, it is characterised in that this first data form
It is respectively 6, the data form of 8 with the second data form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410749031.7A CN104464668B (en) | 2014-12-09 | 2014-12-09 | control circuit for display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410749031.7A CN104464668B (en) | 2014-12-09 | 2014-12-09 | control circuit for display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104464668A CN104464668A (en) | 2015-03-25 |
| CN104464668B true CN104464668B (en) | 2016-11-09 |
Family
ID=52910625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410749031.7A Active CN104464668B (en) | 2014-12-09 | 2014-12-09 | control circuit for display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104464668B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098004A (en) * | 2016-08-11 | 2016-11-09 | 昆山龙腾光电有限公司 | Control device and control method for liquid crystal indicator |
| CN107526979A (en) * | 2017-08-28 | 2017-12-29 | 惠科股份有限公司 | Method and system for protecting software data in display panel |
| CN109979405B (en) * | 2019-03-27 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Time sequence control circuit and display device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060028049A (en) * | 2004-09-24 | 2006-03-29 | 삼성전자주식회사 | Display device and method of driving thereof |
| CN1763705A (en) * | 2004-10-19 | 2006-04-26 | 南京Lg同创彩色显示系统有限责任公司 | EDID data format switching device for image display |
| CN101004883A (en) * | 2006-01-17 | 2007-07-25 | 厦门火炬福大显示技术有限公司 | Control device of flat panel display of field emission |
| CN201518214U (en) * | 2009-09-29 | 2010-06-30 | 深圳市巨潮科技有限公司 | Display die set apparatus for medical application |
| JP5830866B2 (en) * | 2011-02-02 | 2015-12-09 | セイコーエプソン株式会社 | Control device, electro-optical device, driving method of electro-optical device, and electronic apparatus |
| JP5864876B2 (en) * | 2011-03-25 | 2016-02-17 | オリンパス株式会社 | Image processing apparatus and image processing method |
| CN203588650U (en) * | 2013-10-24 | 2014-05-07 | 中航华东光电有限公司 | Display module gray scale expansion circuit |
| CN103871386B (en) * | 2014-03-25 | 2015-11-25 | 昆山龙腾光电有限公司 | A kind of scan control circuit and use its display device |
-
2014
- 2014-12-09 CN CN201410749031.7A patent/CN104464668B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104464668A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101097704B (en) | Liquid crystal display device and driving method thereof | |
| CN104252841B (en) | LED display control method and control card, LED display screen system | |
| CN104485060B (en) | Grid control unit, grid control circuit, array substrate and display panel | |
| CN101925946B (en) | Display device driving method and mobile terminal driving method | |
| CN104464668B (en) | control circuit for display | |
| CN105788551B (en) | A kind of drive system of compatible plurality of display modes | |
| CN101561597B (en) | Liquid crystal panel and driving method thereof | |
| CN104137170B (en) | Display device | |
| CN103155027B (en) | Display device | |
| CN102543018B (en) | Liquid crystal display device and method of driving the same | |
| CN102610201A (en) | Data processing method, data driving circuit and display device including the same | |
| CN104091558A (en) | LED display panel driving method and system | |
| CN113066423A (en) | LED display drive control method and device | |
| CN101996553A (en) | Timing controller, image display device, and reset signal output method | |
| CN105741808A (en) | Gate driving circuit, array substrate, display panel and driving method of display panel | |
| CN103578446A (en) | Scan driving device and driving method thereof | |
| CN103247255A (en) | Scan driving device for a display device and driving method thereof | |
| CN102103837A (en) | Liquid crystal display device | |
| CN105513552A (en) | Driving circuit, driving method and display device | |
| CN101587688B (en) | Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit | |
| CN103871388B (en) | Display panel, gate driver and control method | |
| CN103971656B (en) | Display panel and gate driver | |
| CN102770898B (en) | Source driver circuit of liquid crystal display device | |
| CN102262851A (en) | Gate driver and display device having gate driver | |
| CN103810962A (en) | Display device and method for driving the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |