CN104462626A - RFIF verification platform based on VMM verification methodology and implementation method - Google Patents
RFIF verification platform based on VMM verification methodology and implementation method Download PDFInfo
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Abstract
The invention discloses an RFIF verification platform based on the VMM verification methodology. The RFIF verification platform comprises a radio frequency data generator, an RFIF upper layer control module, an AHB read-write transaction processor, a bus monitor, an AHB main device reference verification model, a scoreboard, a PCD upper layer control module and a radio frequency data coding and decoding module. The invention further discloses an implementation method of the RFIF verification platform. Two behavior class simulation models, namely, the RFIF upper layer control module and the PCD upper layer control module which are used for managing an RFIF and simulating behaviors of an RF card reader respectively are established, and an AHB VIP is adopted as a control bus between the RFIF upper layer control module and the RFIF; due to a transaction driving mechanism with a VMM verification frame, the random activation, the automatic data comparison and the automatic collection function coverage rate are achieved for the whole RFIF verification platform. By means of the RFIF verification platform and the implementation method, the verification efficiency can be effectively improved, the verification time can be effectively saved, and led-in manual errors can be effectively reduced.
Description
Technical field
The present invention relates to a kind of RFIF(radio frequency digital interface) verification platform, particularly relate to a kind of can automatic Verification RFIF based on VMM(Verification Methodology Manual verification methodology) RFIF verification platform.The invention still further relates to a kind of implementation method of described verification platform.
Background technology
Using RFIF as contactless chip core, the function accuracy of RFIF module and performance power need most checking.Due to RF(radio frequency) polytrope of communication data waveform, and the diversity of RFIF configuration and the complicacy of communication protocol, if will spend plenty of time and human input by artificial comparison result, and become more and more difficult along with the increase of test case.
A usual project can experience repeatedly flow, if for the little change of each design, all need again to carry out manpower comparing pair to regression test result, will have a strong impact on the project cycle, and cannot the correctness of index guarantee result of consumption.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of RFIF verification platform based on VMM verification methodology, effectively can improve verification efficiency, saves the proving time, reduces the introducing of mistake; For this reason, the present invention also will provide a kind of implementation method of described RFIF verification platform.
For solving the problems of the technologies described above, the RFIF verification platform based on VMM verification methodology of the present invention, comprising:
One rf data generator, the effect of contraction done by test case is in radio frequency digital interface configuration data class affairs, and the configuration information of RFIF and communication data are passed to RFIF top level control module by the first radio frequency digital interface configuration data class passage by these radio frequency digital interface configuration data class affairs;
One RFIF top level control module, is connected with described rf data generator, for managing design under test and RFIF behavior by the first radio frequency digital interface configuration data class passage;
One AHB(Advanced High-Performance Bus) read and write transaction processor, be connected with described RFIF top level control module by data channel, the affairs handled by this RFIF top level control module converted to AHB VIP(Advanced High-Performance Bus checking intellecture property) the accessible transaction format of control bus;
One bus monitor, is connected with described RFIF top level control module by the second radio frequency digital interface configuration data class passage; Read and write transaction processor by the 2nd AHB data channel with described AHB to be connected; Be used for monitoring the read-write behavior on AHB VIP control bus, and notify described RFIF top level control module; The affairs that described RFIF top level control module sends are passed to PCD top level control module, and it is to be compared that the data that the fifo fifo register of RFIF top level control module is received and dispatched are delivered to scoring plug etc.;
One AHB main equipment is with reference to verification model, i.e. AHB VIP control bus, and it is read and write transaction processor by an AHB data channel with described AHB and is connected, and is connected with described bus monitor by the 2nd AHB data channel; For the operational order of described RFIF top level control module specifically being changed into the read-write sequence of AHB VIP control bus; Be connected with the AHB VIP control bus interface of described RFIF by AHB host device interface, thus the inner each register of described RFIF is operated;
One rf data coding/decoding module, by the 4th radio frequency digital interface configuration data class passage and PCD(card reader) top level control module is connected; Communicated with described RFIF by RFIF module interface; To sending to the data of described RFIF to encode, the decoding data that described RFIF is sent also is sent to PCD top level control module;
One PCD top level control module, is connected with described bus monitor, for the behavior of management simulation radio frequency card reader by the 3rd radio frequency digital interface configuration data class passage; ;
One scoring plug, is connected with described bus monitor by the first readjustment passage, is connected with described PCD top level control module by the second readjustment passage; For the data that more described RFIF top level control module and PCD top level control module send, and determine whether described test case passes through according to comparative result.
The implementation method of described RFIF verification platform adopts following technical scheme to realize:
Design under test RFIF adopts Verilog HDL(hardware description language) language compilation, the RFIF top level control module of described verification platform and PCD top level control module adopt System Verilog(hardware verification language) language compilation; The top layer of whole verification platform adopts Verilog HDL language compilation;
Adopting Synopsys(Synopsys) the AHB VIP of company is as the control bus between RFIF top level control module and RFIF; RFIF top level control module as the main equipment of AHB VIP control bus, RFIF as AHB VIP control bus from equipment;
Configuration parameters all for RFIF and transceiving data are put into VMM_DATA(VMM data base class) extension class RF_DATA(radio frequency digital interface configuration data class), realize the random constraints to these parameters and data;
Adopt RAL(Register Abstraction Layer register level of abstraction) configuration parameter of RFIF is write RFIF by RFIF top level control module by AHB VIP control bus, thus RFIF is configured;
PCD top level control module is set up with RFIF by the configuration parameter of resolving RFIF and is communicated, and realizes all functions required by ISO/IEC14443-2/3;
Judge whether test case passes through by the transceiving data of automatic comparison radio frequency digital interface RFIF top level control module and card reader PCD top level control module.
The present invention can build a portable, reusable, easily extensible, has the RFIF verification platform of arbitrary excitation and automatic comparison; Easily the authentication module of maturation and test case can be multiplexed in high-level verification platform and new projects, thus effectively improve verification efficiency, save the proving time, reduce the introducing of mistake.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the hierarchical structure figure of existing VMM basic framework;
Fig. 2 is the existing verification platform overall construction drawing realized based on VMM basic framework;
Fig. 3 is the described RFIF verification platform structured flowchart based on VMM verification methodology.
Embodiment
Because chip-scale constantly expands, function constantly increases, and also becomes and become increasingly complex the while that checking work will becoming more and more important.Build and the work of chip checking to more efficiently complete verification environment, Synopsys company combines with ARM company and is proposed VMM verification methodology.This verification method is a kind of transaction-level object module environment set up based on System Verilog language in fact.Utilize the Object Oriented Characteristic of System Verilog language, VMM achieves the checking structure of stratification, and there is the randomized feature of constraint, being the verification environment (i.e. verification platform) with automatic comparison function of target drives by building with function coverage on this basis, effectively can promoting verification efficiency.
VMM is a kind of based on transaction-level, the verification methodology with hierarchical structure.In FIG, test layer (Test Layer) is for writing test cases.The constraint of generator (Generator) can be revised at test layer, define multiple random scene (Scenario), synchronous each transaction processor (Transactor) and the directed excitation of generation.
Scene layer (Scenario Layer) provide maker (Generator), for generation of data and affairs (Transaction).So-called scene just refers to the sequence of the random affairs of certain relation.
Functional layer (Functional Layer) has abstractness, provides some application oriented functional blocks (as transaction processor, scoring plug) and is used for processing application layer affairs.
Instruction level (Instruction Layer) is linking functions layer and DUT(design to be measured) between bridge, with the various interface in DUT and physical layer protocol closely related.Instruction level module comprises bus functionality module, physical layer protocol driver, monitor and detector.
Signals layer (Singal Layer) is the articulamentum between verification environment (i.e. verification platform) and DUT, is directly coupled together by the interface (Interface) of the pin of DUT with verification environment.
Fig. 2 illustrates a complete verification platform.Whole VMM verification environment is built and is started in program (program), by program example in the top-level module of verification platform, and is connected with DUT by signals layer, so whole verification platform has been built.
RFIF numeral IP(intellecture property based on VMM builds) verification platform (based on the RFIF verification platform of VMM verification methodology namely) has portability and extensibility, the functions such as arbitrary excitation, automaticdata comparison, automatic collection function coverage rate can be realized, can transplant quickly in income order and carry out checking work.
Described based on the RFIF verification platform of VMM verification methodology in the DUT that verifies be the digital IP module of a RFIF.This digital IP module mainly realizes the controlling functions of the RF circuit of non-contact card, is responsible for the communications protocol process between non-contact card radio circuit and cpu circuit and data transmission.Data interaction between card reader and non-contact card, through the modulation /demodulation of antenna and analog module, then delivers to RFIF, by AHB(Advanced High-Performance Bus after RFIF process) bus carries out data transmission with CPU.
The major function of RFIF: support ISO/IEC14443-2TypeA/TypeB(type A/ type B) agreement, comprise the highest 847Kbps(bps) communication speed; Hardware handles ISO/IEC14443-3TypeA anti-collision flow process; Hardware handles certification and communication streams encryption; Use 256byte(byte) FIFO(first in first out) register carries out data transmission; The multiple transmission modes such as sleep reception, sleep transmission, automatic reception transmission, stream reception, stream transmission are provided.
The described RFIF verification platform based on VMM verification methodology possesses following function according to the main functional characteristics of RFIF:
(1) the RF(radio frequency that PCD produces TypeA/TypeB two type can, be simulated) data complete basic transmission-receiving function.
(2) the RF data that PCD receives and dispatches various baud rate can, be simulated.
(3) the anti-collision flow process of TypeA can, be simulated.
(4) PCD, can be simulated and coordinate PICC(proximity card) carry out authenticated encryption flow process.
(5) ability produced continuously more than 256byte data, is possessed.
(6), all transmission modes are supported.
(7), support that RF data compare automatically.
Fig. 3 is the described RFIF verification platform one example structure block diagram based on VMM verification methodology, comprising:
One rf data generator, a RFIF top level control module, described rf data generator is connected with RFIF top level control module by the first radio frequency digital interface configuration data class passage 1.
One AHB reads and writes transaction processor, is connected with described RFIF top level control module by data channel 7.
One bus monitor, is connected with described RFIF top level control module by the second radio frequency digital interface configuration data class passage 2.
One AHB main equipment is with reference to verification model, and it is read and write transaction processor by an AHB data channel 5 with described AHB and is connected.Described bus monitor is read and write transaction processor respectively by the 2nd AHB data channel 6 and is connected with reference to verification model with AHB main equipment with AHB.
One scoring plug, is connected with described bus monitor by the first readjustment passage.
One PCD top level control module, it is connected with described bus monitor by the 3rd radio frequency digital interface configuration data class passage 3; Be connected with described scoring plug by the second readjustment passage.
One rf data coding/decoding module, is connected with described PCD top level control module by the 4th radio frequency digital interface configuration data class passage 4.
In Fig. 3, test case can customize different constraints for the fc-specific test FC object of each test (test), such as specify that this test is TypeA stream mode or TypeB sleep pattern etc., the characteristic that retrains is not done then to its random arrangement for other, length of such as random RF data to be sent etc.
The constraint that test case does will be applied to a RF_Data(radio frequency digital interface configuration data class by rf data generator) in class affairs.RF_Data is an extension class, and it is from vmm_data(VMM data base class) base class expands.The class members comprised in extension class RF_Data, according to register parameters definition in RFIF, is used for configuring RFIF and RFIF verification platform.The VMM scene generator class that rf data generator class is then provided by VMM according to extension class RF_Data produces, and this scene generator class is the expansion of VMM transaction processor class, inherits whole common interface elements that this VMM transaction processor class provides.Affairs must be transmitted between transaction processor by passage.Rf data generator only has an output channel, i.e. the first radio frequency digital interface configuration data class passage 1, it is generated by VMM channel types, and some configuration informations of RFIF and communication data are passed to RFIF top level control module by the first radio frequency digital interface configuration data class passage 1 by RF_Data class affairs.
RFIF top level control module class (RFIF top level control module is by RFIF top level control module class exampleization) expansion, from VMM transaction processor class, is positioned at functional layer.This RFIF top level control module class, for managing design under test and RFIF behavior, comprising: select testing process according to the affairs that rf data generator hands down; Control AHB VIP bus is read and write, and monitors RFIF by AHB main equipment (instruction level); RFIF sends fifo register when testing, communication data being write RFIF, and is delivered to bus monitor; After RFIF receives ED, read the data in the fifo register of RFIF, and be delivered to bus monitor; By the configuration parameter of RFIF by AHB VIP control bus write RFIF, RFIF is configured; Realize all functions of ISO/IEC14443-2/3 protocol requirement.The AHB VIP control bus of what Advanced High-Performance Bus main equipment here adopted is Synopsys company, namely the AHB main equipment in Fig. 3 is with reference to verification model, the operational order of RFIF top level control module is specifically changed into the read-write sequence of AHB VIP control bus with reference to verification model by this AHB main equipment, be connected with the AHB VIP control bus interface of RFIF by AHB host device interface, thus each register in RFIF inside is operated.Need affairs to change the mechanism in this process, read and write transaction processor by AHB and complete, it converts the affairs handled by RFIF top level control module to AHB VIP control bus accessible transaction format.
Bus monitor class (bus monitor is generated by bus monitor class exampleization) expansion, from VMM transaction processor class, is used for monitoring the read-write behavior on AHB VIP control bus, and notifies class notice RFIF top level control module by VMM.In addition be also responsible for the affairs that RFIF top level control module sends to pass to PCD top level control module, and it is to be compared the FIFO transceiving data of RFIF top level control module to be delivered to scoring plug etc.
PCD top level control module and rf data coding/decoding module class are all expanded from VMM transaction processor class, and the former belongs to functional layer, and latter is the specific implementation of upper surface function, belongs to instruction level.
Described rf data coding/decoding module, to sending to the data of described RFIF to encode, the decoding data that described RFIF is sent also is sent to card reader PCD top level control module.
Described PCD top level control module is used for the behavior of management simulation radio frequency card reader, comprising: by resolving the affairs that described bus monitor is brought, judging that it needs the flow process performed, is this time such as TypeA or TypeB communication, be transmission flow or reception flow process, whether encrypt etc.The data of transmitting-receiving are delivered to scoring plug simultaneously, compare with the data of RFIF top level control module side.To set up with RFIF communicate by resolving the configuration parameter of RFIF, realize all functions required by ISO/IEC14443-2/3 agreement.
The data that scoring plug completes RFIF top level control module and PCD top level control module both sides compare, and respectively by VMM readjustment, two side datas are adjusted back scoring plug.Whether final test example is passed through, then determine according to the comparison result of scoring plug.
Except the assembly that the structure verification platform indicated except Fig. 3 is required, also increased the assembly of a collecting function coverage rate in this verification environment newly, the assembly of this collecting function coverage rate adopts the expansion of VMM transaction processor readjustment class to realize.The assembly of this collecting function coverage rate obtains affairs from RFIF top level control module, different coverage rate groups is defined by function, each coverage rate group creates storehouse and alternate covering rate according to the emphasis of checking again, finally carries out sampling to collect coverage rate to each coverage rate group at fixed time.Coverage rate table can be produced with emulation tool after the emulation of all test cases terminates, wherein comprise function coverage table, analysis be carried out to function coverage table and can understand which function point and do not test, foundation is provided to the adequacy of checking.
Above all component is all packaged in verification environment class, and such is the extension class of VMM register level of abstraction verification environment, and design achieves the reusability of verification environment like this.
The described RFIF verification platform based on VMM verification methodology is adopted and is realized with the following method:
Design under test RFIF adopts Verilog HDL language compilation.Construct two behavioral scaling realistic models, namely adopt System Verilog language compilation can realize RFIF top level control module and the PCD top level control module of ISO/IEC14443-2/3 protocol requirement function, be respectively used to management RFIF and analog RF card reader (i.e. PCD) behavior.The top layer of whole verification platform adopts Verilog HDL language compilation.
Adopt the AHB VIP control bus of Synopsys company as the control bus between RFIF top level control module and RFIF.RFIF top level control module as the main equipment of AHB VIP control bus, RFIF as AHB VIP control bus from equipment.
Configuration parameters all for radio frequency digital interface RFIF and transceiving data are put into the extension class radio frequency digital interface configuration data class RF_DATA of verification methodology VMM data base class VMM_DATA, realize the random constraints to these parameters and data.
Adopt register level of abstraction RAL by Advanced High-Performance Bus, the configuration parameter of radio frequency digital interface RFIF is verified that intellecture property AHB VIP control bus writes radio frequency digital interface RFIF by radio frequency digital interface RFIF top level control module, thus radio frequency digital interface RFIF is configured.
Card reader PCD top level control module is set up with radio frequency digital interface RFIF by the configuration parameter of resolving radio frequency digital interface RFIF and is communicated, and realizes all functions required by ISO/IEC14443-2/3 agreement.
Judge whether test case passes through by the transceiving data of automatic comparison radio frequency digital interface RFIF top level control module and card reader PCD top level control module.
Described RFIF verification platform realizes the self-verifying to RF communication data, and the function coverage realizing all test feature of RFIF is collected automatically.The special function register paid close attention to by some is defined as functional coverage model, and when this special function register is configured in RFIF top level control module, described RFIF verification platform is by automatic collection function coverage rate.After all test cases have all returned, generate a final function coverage report.
Described radio frequency digital interface RFIF top level control module and card reader PCD module can realize the function of ISO/IEC14443-2/3 protocol requirement.
All test and excitations are all produced by radio frequency digital interface configuration data class RF_DATA, automatically generate the arbitrary excitation meeting ISO/IEC14443-2/3 protocol requirement.
Can realize one according to process described above can arbitrary disposition test parameter, the duty of the whole RFIF of complete survey, and has corresponding function coverage as the RFIF verification environment of quantized result.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (14)
1., based on a radio frequency digital interface RFIF verification platform of verification methodology VMM, it is characterized in that, comprising:
One rf data generator, the effect of contraction done by test case is in radio frequency digital interface configuration data class affairs, and the configuration information of radio frequency digital interface RFIF and communication data are passed to radio frequency digital interface RFIF top level control module by the first radio frequency digital interface configuration data class passage by these radio frequency digital interface configuration data class affairs;
Radio frequency digital interface RFIF top level control module described in one, is connected with described rf data generator by the first radio frequency digital interface configuration data class passage, for managing design under test and radio frequency digital interface RFIF behavior;
One Advanced High-Performance Bus AHB reads and writes transaction processor, be connected with described radio frequency digital interface RFIF top level control module by data channel, the affairs handled by this radio frequency digital interface RFIF top level control module converted to the accessible transaction format of Advanced High-Performance Bus checking intellecture property AHB VIP control bus;
One bus monitor, is connected with described radio frequency digital interface RFIF top level control module by the second radio frequency digital interface configuration data class passage; Read and write transaction processor by the second Advanced High-Performance Bus AHB data channel with described Advanced High-Performance Bus AHB to be connected; Be used for monitoring the read-write behavior on Advanced High-Performance Bus checking intellecture property AHB VIP control bus, and notify described radio frequency digital interface RFIF top level control module; The affairs that described radio frequency digital interface RFIF top level control module sends are passed to card reader PCD top level control module, and it is to be compared that the data that the fifo fifo register of radio frequency digital interface RFIF top level control module is received and dispatched are delivered to scoring plug etc.;
One Advanced High-Performance Bus AHB main equipment is with reference to verification model, i.e. Advanced High-Performance Bus checking intellecture property AHB VIP control bus, it is read and write transaction processor by the first Advanced High-Performance Bus AHB data channel with described Advanced High-Performance Bus AHB and is connected, and is connected with described bus monitor by the second Advanced High-Performance Bus AHB data channel; For the operational order of described radio frequency digital interface RFIF top level control module specifically being changed into the read-write sequence of Advanced High-Performance Bus checking intellecture property AHB VIP control bus; Verify that intellecture property AHB VIP control bus interface is connected by Advanced High-Performance Bus AHB host device interface and the Advanced High-Performance Bus of described radio frequency digital interface RFIF, thus the inner each register of described radio frequency digital interface RFIF is operated;
One rf data coding/decoding module, is connected with card reader PCD top level control module by the 4th radio frequency digital interface configuration data class passage; Communicated with described radio frequency digital interface RFIF by radio frequency digital interface RFIF module interface; To sending to the data of described radio frequency digital interface RFIF to encode, the decoding data that described radio frequency digital interface RFIF is sent also is sent to card reader PCD top level control module;
One card reader PCD top level control module, is connected with described bus monitor, for the behavior of management simulation radio frequency card reader by the 3rd radio frequency digital interface configuration data class passage;
One scoring plug, is connected with described bus monitor by the first readjustment passage, is connected with described card reader PCD top level control module by the second readjustment passage; For the data that more described radio frequency digital interface RFIF top level control module and card reader PCD top level control module send, and determine whether described test case passes through according to comparative result.
2. verification platform as claimed in claim 1, it is characterized in that: the class members comprised in described radio frequency digital interface configuration data class RF_DATA, according to register parameters definition in described radio frequency digital interface RFIF, is used for configuring radio frequency digital interface RFIF and radio frequency digital interface RFIF verification platform.
3. verification platform as claimed in claim 1, is characterized in that: described management radio frequency digital interface RFIF behavior, comprising: select testing process according to the affairs that rf data generator hands down; Control the read-write of Advanced High-Performance Bus checking intellecture property AHB VIP control bus, monitor described radio frequency digital interface RFIF by Advanced High-Performance Bus AHB main equipment with reference to verification model; When described radio frequency digital interface RFIF sends test, communication data is write the fifo fifo register of radio frequency digital interface RFIF, and be delivered to bus monitor; After described radio frequency digital interface RFIF receives ED, read the data in the fifo fifo register of radio frequency digital interface RFIF, and be delivered to bus monitor; By the configuration parameter of radio frequency digital interface RFIF by Advanced High-Performance Bus checking intellecture property AHB VIP control bus write radio frequency digital interface RFIF, radio frequency digital interface RFIF is configured; Realize all functions of ISO/IEC14443-2/3 protocol requirement.
4. verification platform as claimed in claim 1, is characterized in that: by verification methodology VMM, described bus monitor notifies that the read-write behavior on the Advanced High-Performance Bus checking intellecture property AHB VIP control bus that it monitors by class notifies described radio frequency digital interface RFIF top level control module.
5. verification platform as claimed in claim 1, is characterized in that: the behavior of described management simulation radio frequency card reader, comprising: by resolving the affairs that described bus monitor is brought, and judges that it needs the flow process performed, the data of transmitting-receiving is delivered to scoring plug simultaneously; To be set up with radio frequency digital interface RFIF by the configuration parameter of resolving radio frequency digital interface RFIF and communicate, realize all functions required by ISO/IEC14443-2/3 agreement.
6. as the verification platform as described in arbitrary in claim 1-5, it is characterized in that, also comprise: the assembly of a collecting function coverage rate, affairs are obtained from described radio frequency digital interface RFIF top level control module, different coverage rate groups is defined by function, each coverage rate group creates storehouse and alternate covering rate according to the emphasis of checking again, finally carries out sampling to collect coverage rate to each coverage rate group at fixed time.
7. verification platform as claimed in claim 6, it is characterized in that: all component is all packaged in verification environment class, this verification environment class is the extension class of verification methodology VMM register level of abstraction verification environment, realizes the reusability of verification platform.
8. verification platform as claimed in claim 6, it is characterized in that: all test case emulation terminates rear emulation tool and produces coverage rate table, wherein comprise function coverage table, which function point of analysis understanding is carried out to function coverage table and does not test, provide foundation to the adequacy of checking.
9. verification platform as claimed in claim 1, it is characterized in that: all test case emulation terminates rear emulation tool and produces coverage rate table, wherein comprise function coverage table, which function point of analysis understanding is carried out to function coverage table and does not test, provide foundation to the adequacy of checking.
10. verification platform as claimed in claim 1, it is characterized in that: all component is all packaged in verification environment class, this verification environment class is the extension class of verification methodology VMM register level of abstraction verification environment, realizes the reusability of verification platform.
11. 1 kinds, based on the radio frequency digital interface RFIF verification platform implementation method of verification methodology VMM, is characterized in that:
Design under test radio frequency digital interface RFIF adopts hardware description language Verilog HDL to write, the radio frequency digital interface RFIF top level control module of described verification platform and card reader PCD top level control module adopt hardware verification language System Verilog to write, and the top layer of described verification platform adopts hardware description language Verilog HDL to write;
Adopt Advanced High-Performance Bus checking intellecture property AHB VIP as the control bus between radio frequency digital interface RFIF top level control module and radio frequency digital interface RFIF; Radio frequency digital interface RFIF top level control module as the main equipment of Advanced High-Performance Bus checking intellecture property AHB VIP control bus, radio frequency digital interface RFIF as Advanced High-Performance Bus checking intellecture property AHB VIP control bus from equipment;
Configuration parameters all for radio frequency digital interface RFIF and transceiving data are put into the extension class radio frequency digital interface configuration data class RF_DATA of verification methodology VMM data base class VMM_DATA, realize the random constraints to these parameters and data;
Adopt register level of abstraction RAL by Advanced High-Performance Bus, the configuration parameter of radio frequency digital interface RFIF is verified that intellecture property AHB VIP control bus writes radio frequency digital interface RFIF by radio frequency digital interface RFIF top level control module, thus radio frequency digital interface RFIF is configured;
Card reader PCD top level control module is set up with radio frequency digital interface RFIF by the configuration parameter of resolving radio frequency digital interface RFIF and is communicated, and realizes all functions required by ISO/IEC14443-2/3 agreement;
Judge whether test case passes through by the transceiving data of automatic comparison radio frequency digital interface RFIF top level control module and card reader PCD top level control module.
12. methods as claimed in claim 11, it is characterized in that: the special function register that needs are paid close attention to is defined as functional coverage model, when described special function register is configured in radio frequency digital interface RFIF top level control module, by described verification platform automatic collection function coverage rate; After all test cases have all returned, generate a final function coverage report.
13. methods as claimed in claim 11, is characterized in that: described radio frequency digital interface RFIF top level control module and card reader PCD module can realize the function of ISO/IEC14443-2/3 protocol requirement.
14. methods as claimed in claim 11, is characterized in that: all test and excitations are all produced by radio frequency digital interface configuration data class RF_DATA, automatically generate the arbitrary excitation meeting ISO/IEC14443-2/3 protocol requirement.
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| CN106096123B (en) * | 2016-06-07 | 2019-05-21 | 无锡键桥电子科技有限公司 | A kind of VMM verifying system and method for passive label chip |
| CN108154022A (en) * | 2016-12-02 | 2018-06-12 | 龙芯中科技术有限公司 | Low Pin Count LPC slave devices and LPC main equipment verification methods |
| CN108154022B (en) * | 2016-12-02 | 2020-11-06 | 龙芯中科技术有限公司 | Low pin type interface LPC slave device and LPC master device verification method |
| CN109189565A (en) * | 2018-08-02 | 2019-01-11 | 深圳忆联信息系统有限公司 | A kind of AHB burst transfer based on more equipment interrupts verification method and its system |
| CN112699695A (en) * | 2021-03-23 | 2021-04-23 | 广州智慧城市发展研究院 | RFID reader-writer software verification device and method and electronic equipment |
| CN112699695B (en) * | 2021-03-23 | 2021-07-20 | 广州智慧城市发展研究院 | RFID reader-writer software verification device and method and electronic equipment |
| CN113377587A (en) * | 2021-06-01 | 2021-09-10 | 珠海昇生微电子有限责任公司 | System and method for testing scan chain circuit based on FPGA chip |
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