CN104425493A - Semiconductor device having 3D channels, and method of fabricating semiconductor device having 3D channels - Google Patents
Semiconductor device having 3D channels, and method of fabricating semiconductor device having 3D channels Download PDFInfo
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- CN104425493A CN104425493A CN201410058492.XA CN201410058492A CN104425493A CN 104425493 A CN104425493 A CN 104425493A CN 201410058492 A CN201410058492 A CN 201410058492A CN 104425493 A CN104425493 A CN 104425493A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000011810 insulating material Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 75
- 229910052751 metal Inorganic materials 0.000 claims description 75
- 239000000463 material Substances 0.000 claims description 26
- 230000006835 compression Effects 0.000 claims description 10
- 238000007906 compression Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 239000012528 membrane Substances 0.000 description 103
- 102100026620 E3 ubiquitin ligase TRAF3IP2 Human genes 0.000 description 17
- 101710140859 E3 ubiquitin ligase TRAF3IP2 Proteins 0.000 description 17
- 238000000034 method Methods 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 10
- 101100215341 Arabidopsis thaliana ACT12 gene Proteins 0.000 description 9
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- 101100215339 Arabidopsis thaliana ACT11 gene Proteins 0.000 description 8
- 101100217138 Mus musculus Actr10 gene Proteins 0.000 description 8
- 102100031102 C-C motif chemokine 4 Human genes 0.000 description 7
- 101000777470 Mus musculus C-C motif chemokine 4 Proteins 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 101100215368 Dictyostelium discoideum act21 gene Proteins 0.000 description 5
- 101100161922 Dictyostelium discoideum act22 gene Proteins 0.000 description 5
- 101000945093 Homo sapiens Ribosomal protein S6 kinase alpha-4 Proteins 0.000 description 5
- 102100033644 Ribosomal protein S6 kinase alpha-4 Human genes 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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Abstract
A semiconductor device includes a substrate having first, second and third fins longitudinally aligned in a first direction. A first trench extends between the first and second fins, and a second trench extends between the second and third fins. A first portion of field insulating material is disposed in the first trench, and a second portion of field insulating material is disposed in the second trench. An upper surface of the second portion of the field insulating material is recessed in the second trench at a level below uppermost surfaces of the second and third fins. A first dummy gate is disposed on an upper surface of the first portion of the field insulating material, and a second dummy gate at least partially extends into the second trench to the upper surface of the second portion of the field insulating material.
Description
Technical field
The present invention's design relates to the semiconductor device with three-dimensional (3D) raceway groove and manufactures the method with the semiconductor device of 3D raceway groove.
Background technology
Multiple technologies are developed to increase the integrated level of semiconductor device.Current technology is to provide a multiple-gate transistor structure, in this multiple-gate transistor structure, form fin-shaped (or nanometer is linear) silicon main body by substrate, and on the surface of silicon main body, forms multiple grid to limit 3D channel region in silicon main body.
3D raceway groove is conducive to the reduction of scale, is because need not increase the transistor that grid length (or channel length) realizes having relatively enough current handling capability at least partly.In addition, the electromotive force of the channel region of wherein transistor can be effectively suppressed to be subject to the short-channel effect (SCE) of drain voltage impact.
Summary of the invention
According to the one side of the present invention's design, a kind of semiconductor device is provided, this semiconductor device comprises: substrate, first, second, and third fin that there are the first and second grooves and longitudinally aim in a first direction, wherein the first groove extends between the first fin and the second fin, and the second groove extends between the second fin and the 3rd fin.This semiconductor device also comprises the Part I of an insulating material and the Part II of field insulating material, the Part I of field insulating material is arranged in the first groove be plugged between the first fin and the second fin, the Part II of insulating material is arranged in the second groove be plugged between the second fin and the 3rd fin, and the upper surface of the Part II of its midfield insulating material level place in the second groove below the upper space of the second fin and the 3rd fin is recessed.This semiconductor device also comprises: multiple active gate, is arranged on the first fin, the second fin and the 3rd fin; First dummy gate electrode, arranges on the upper surface of the Part I of insulating material on the scene; And second dummy gate electrode, extend to the upper surface to the Part II of field insulating material in the second groove at least in part.
The degree of depth of the first groove can be less than the degree of depth of the second groove, and the first groove width in a first direction can be less than the second groove width in a first direction.
Semiconductor device also can comprise and strides across the second groove three dummy gate electrode relative with the second dummy gate electrode, and wherein the 3rd dummy gate electrode extends to the upper surface to the Part II of field insulating material in the second groove at least in part.
The Part I of the second dummy gate electrode can extend above the upper surface of the second fin adjacent with the edge of the second groove, and the Part II of the second dummy gate electrode can extend the upper surface of the Part II of insulating material of showing up along the sidewall of groove.In addition, the second dummy gate electrode can comprise the first metal layer of wherein restriceted envelope and occupy second metal level in this space, and both the Part I of the second dummy gate electrode and Part II can comprise the first metal layer and the second metal level.Alternatively, the only Part I of the second dummy gate electrode can comprise both the first metal layer and the second metal level, makes the space limited by the first metal layer completely on the level of the upper surface of the second fin.
Second dummy gate electrode can be included in the first side wall sept above the upper surface of the second fin and in the second groove the Part II of insulating material on the scene upper surface above the second sidewall spacer of extending.
Second dummy gate electrode can comprise at least one metal level, and this at least one metal level is all positioned at above the upper surface of the Part II of an insulating material.In addition, the second dummy gate electrode can comprise the first metal layer of wherein restriceted envelope and occupy second metal level in this space, above the first metal layer and the whole upper surfaces that can be positioned at the Part II of an insulating material both the second metal level.
This semiconductor device can also be included in the source/drain regions between neighboring active grid, between the first dummy gate electrode and a neighboring active grid and between the second dummy gate electrode and another neighboring active grid.In addition, source/drain regions can be that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
According to the another aspect of the present invention's design, there is provided a kind of semiconductor device, this semiconductor device comprises: substrate, comprises the first active area and the second active area, first active area comprises the first groove, is demarcated by the second groove be plugged on therebetween in the first active area and the second active area.This semiconductor device also comprise longitudinally aim in a first direction the first fin, the second fin and the 3rd fin multiple parallel group, first fin of each group and the second fin are included in the first active area, 3rd fin of each group is included in the second active area, wherein the first groove extends between first fin of each group and the second fin, and the second groove extends between second fin of each group and the 3rd fin.This semiconductor device also comprises the Part I of an insulating material and the Part II of field insulating material, the Part I of field insulating material is arranged in the first groove be plugged between the first fin of each respective sets and the second fin, the Part II of insulating material is arranged in the second groove between the second fin and the 3rd fin being plugged on each respective sets, and the upper surface of the Part II of its midfield insulating material level place in the second groove below the upper space of the second fin of each respective sets and the 3rd fin is recessed.This semiconductor device also comprises: multiple active gate, is arranged on first fin of each group, the second fin and the 3rd fin; First dummy gate electrode, is arranged on the upper surface of the Part I of corresponding field insulating material; Second dummy gate electrode, extends to the upper surface to the Part II of the corresponding field insulating material adjacent to second fin of each group in the second groove at least in part; And the 3rd dummy gate electrode, extend to the upper surface to the Part II of the corresponding field insulating material adjacent to the 3rd fin of each group in the second groove at least in part.
The degree of depth of the first groove can be less than the degree of depth of the second groove, and the first groove width in a first direction can be less than the second groove width in a first direction.
The Part I of each second dummy gate electrode can extend above the upper surface of the second corresponding fin adjacent to the edge of the second groove, and the Part II of each second dummy gate electrode can extend the upper surface of the Part II of insulating material of showing up along the sidewall of the second groove.In addition, the Part I of each 3rd dummy gate electrode can extend above the upper surface of the 3rd corresponding fin adjacent to the opposite edges of the second groove, and the Part II of each 3rd dummy gate electrode can extend the upper surface of the Part II of insulating material of showing up along the opposing sidewalls of the second groove.In addition, active gate and each of first, second, and third dummy gate electrode can comprise the first metal layer of wherein restriceted envelope and occupy second metal level in this space.The Part I of the second dummy gate electrode and the 3rd dummy gate electrode and Part II can comprise the first metal layer and the second metal level.Alternatively, second and the 3rd the only Part I of dummy gate electrode can comprise both the first metal layer and the second metal level, make the space that limited by the first metal layer completely corresponding second and the 3rd fin upper surface level on.
Each second dummy gate electrode can be included in the first side wall sept above the upper surface of corresponding second fin and in the second groove the Part II of insulating material on the scene upper surface above the second sidewall spacer of extending.In addition, each 3rd dummy gate electrode can be included in the 3rd sidewall spacer above the upper surface of corresponding 3rd fin and in the second groove the Part II of insulating material on the scene upper surface above the 4th sidewall spacer that extends.
Second dummy gate electrode and each of the 3rd dummy gate electrode can comprise the first metal layer of wherein restriceted envelope and occupy second metal level in this space, above whole upper surfaces that can be positioned at the Part II of an insulating material of both the first and second metal levels.
This semiconductor device can also be included in the source/drain regions between neighboring active grid, between each first dummy gate electrode and a neighboring active grid, between each second dummy gate electrode and another neighboring active grid and between each 3rd dummy gate electrode and another neighboring active grid.In addition, source/drain regions can be that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
According to the another aspect of the present invention's design, provide a kind of semiconductor device, this semiconductor device comprises: substrate, has groove; And first fin and the second fin, longitudinally aim in a first direction, wherein groove extends between the first fin and the second fin.Semiconductor device also comprises a part of field insulating material in the groove being arranged on and being plugged between the first fin and the second fin, and wherein the upper surface of this part field insulating material is arranged on the level place below the upper space of the first fin and the second fin.This semiconductor device also comprises: be arranged on the multiple active gate on the first fin and the second fin; First dummy gate electrode, extends to the upper surface to this part field insulating material in groove at least in part; And second dummy gate electrode, stride across groove relative with the first dummy gate electrode, the second dummy gate electrode extends to the upper surface to this part field insulating material in groove at least in part.
Groove can be demarcate in the first and second active areas, and the first fin can in the first active area and the second fin can in the second active area.
The Part I of the first dummy gate electrode can extend above the upper surface of the first fin adjacent with the edge of groove, and the Part II of each first dummy gate electrode can extend to the upper surface of this part field insulating material along the sidewall of groove.In addition, the Part I of the second dummy gate electrode can extend above the upper surface of the second fin adjacent with the opposite edges of groove, and the Part II of the second dummy gate electrode can extend to the upper surface of this part field insulating material along the opposing sidewalls of groove.
The each of first and second dummy gate electrode can comprise at least one metal level, and this at least one metal level is all positioned at above the upper surface of this part field insulating material.
This semiconductor device can also be included in source/drain regions in corresponding first and second active areas and adjacent with the first and second corresponding dummy gate electrode.In addition, source/drain regions can be that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
According to the another aspect of the present invention's design, provide a kind of semiconductor device, this semiconductor device comprises: substrate, has the first and second grooves; And the first fin, the second fin and the 3rd fin longitudinally aimed in a first direction, wherein the first groove extends between the first fin and the second fin, and the second groove extends between the second fin and the 3rd fin.This semiconductor device also comprises: the Part I of field insulating material, is arranged in the first groove be plugged between the first fin and the second fin; The Part II of insulating material, is arranged in the second groove be plugged between the second fin and the 3rd fin, and the upper surface of the Part II of its midfield insulating material is arranged on the level place above the upper space of the second fin and the 3rd fin.This semiconductor device also comprises: multiple active gate, is arranged on the first fin, the second fin and the 3rd fin; First dummy gate electrode, arranges on the upper surface of the Part I of insulating material on the scene; And second and the 3rd dummy gate electrode, be at least partially disposed on the upper surface of the Part II of an insulating material.
The degree of depth of the first groove can be less than the degree of depth of the second groove, and the first groove width in a first direction can be less than the second groove width in a first direction.
Second and the 3rd dummy gate electrode can include: the Part I extended above the upper surface of the Part II of insulating material on the scene; And the Part II below the upper space extending to the second fin and the 3rd fin respectively.
This semiconductor device can also be included in the source/drain regions between neighboring active grid, between the first dummy gate electrode and a neighboring active grid, between the second dummy gate electrode and another neighboring active grid and between the 3rd dummy gate electrode and another neighboring active grid.In addition, source/drain regions can be that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
According to the another aspect of the present invention's design, a kind of semiconductor device is provided, this semiconductor device comprises: substrate, comprise the first and second active areas, first active area comprises the first groove, demarcated by the second groove be plugged on therebetween in first and second active areas, the second groove has the degree of depth larger than the first groove.This semiconductor device also comprise longitudinally aim in a first direction the first fin, the second fin and the 3rd fin multiple parallel group, first fin of each group and the second fin are included in the first active area, 3rd fin of each group is included in the second active area, wherein the first groove extends between first fin of each group and the second fin, and the second groove extends between described second fin of each group and the 3rd fin.This semiconductor device also comprises the Part I of an insulating material and the Part II of field insulating material, the Part I of field insulating material is arranged in the first groove be plugged between the first fin of each respective sets and the second fin, the Part II of field insulating material is arranged in the second groove between the second fin and the 3rd fin being plugged on each respective sets, and the upper surface of the Part II of its midfield insulating material is arranged on the level place of more than the second fin of each respective sets and the upper space of the 3rd fin.This semiconductor device also comprises: multiple active gate, is arranged on first fin of each group, the second fin and the 3rd fin; First dummy gate electrode, is arranged on the upper surface of the Part I of corresponding field insulating material; Second dummy gate electrode, is at least partially disposed on the upper surface of the Part II of the corresponding field insulating material adjacent to second fin of each group; And the 3rd dummy gate electrode, be at least partially disposed on the upper surface of the Part II of the corresponding field insulating material adjacent to the 3rd fin of each group.
Accompanying drawing explanation
Above and other object, the feature and advantage of the present invention's design will become more obvious from the detailed description of carrying out preferred implementation below in conjunction with accompanying drawing, in the accompanying drawings:
Fig. 1 is the diagram of layout of the various elements of semiconductor device according to the present invention's design;
Fig. 2 is the plane graph of fin and field insulating membrane in the layout of Fig. 1;
Fig. 3 is the perspective view of the first execution mode of the semiconductor device according to the present invention's design;
Fig. 4 is the fin of the semiconductor device of Fig. 3 and the perspective view of field insulating membrane;
Fig. 5 is the perspective view of the fin of the semiconductor device with Fig. 3 and the substrate of groove;
Fig. 6 A is the example cross section intercepted along the line A-A of Fig. 3;
Fig. 6 B is the example cross section intercepted along the line D-D of Fig. 1;
Fig. 7 is the example cross section intercepted along the line B-B of Fig. 3;
Fig. 8 A is the sectional view of an example of the second execution mode of semiconductor device according to the present invention's design;
Fig. 8 B is the sectional view of another example of the second execution mode of semiconductor device according to the present invention's design;
Fig. 8 C is the sectional view of another example of the second execution mode of semiconductor device according to the present invention's design;
Fig. 9 is the sectional view of the 3rd execution mode of the semiconductor device according to the present invention's design;
Figure 10 is the sectional view of the 4th execution mode of the semiconductor device according to the present invention's design;
Figure 11 is the sectional view of the 5th execution mode of the semiconductor device according to the present invention's design;
Figure 12 A is the plane graph of the dummy gate electrode of one or more execution modes for illustration of the semiconductor device conceived according to the present invention;
Figure 12 B is the example cross section intercepted along the line G-G of Figure 12 A;
Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22 are describing in the manufacture method according to the semiconductor device of the present invention's design for the layout of reference and perspective view;
Figure 23 is the block diagram of the electronic device of the semiconductor device of the one or more execution modes comprised according to the present invention's design; And
Figure 24 is the block diagram of the electronic system of the semiconductor device of the one or more execution modes comprised according to the present invention's design.
Embodiment
The advantage of the present invention's design and feature and the method completing it can be understood more readily by detailed description of the preferred embodiment and accompanying drawing by reference to following.But the present invention's design can be implemented in many different forms, and should not be understood to be limited to execution mode set forth herein.But provide these execution modes to make the disclosure by comprehensively and complete and the present invention will be passed on to conceive to those skilled in the art comprehensively, the present invention's design only will be defined by the claims.In the drawings, in order to clear, exaggerate the thickness in layer and region.
In addition, identical Reference numeral is used to indicate identical element in whole accompanying drawing.Therefore, for simplicity, when the similar elements of other execution mode is described in detail, the detailed description of some elements of some execution mode can be omitted.
To understand, when an element or layer be called as another element or layer " on " or " being connected to " another element or layer time, directly on another element described or layer or be directly connected to another element described or layer, or can there is intervening elements or layer in it.On the contrary, when an element be called as " directly existing " another element or layer " on " or " being directly connected to " another element or layer time, then there is no intervening elements or layer.Identical Reference numeral refers to identical element all the time.When this uses, term "and/or" comprises any of one or more associated listed items and all combinations.
For convenience of description, can in this usage space relative terms, such as " ... below ", " below ", D score, " in ... top ", " on " etc. the relation of an element or feature and other element or feature in orientation shown in the figure is described.In addition, because accompanying drawing will briefly show, therefore term " on " upper space of particular element in implicit orientation shown in the figure can be used to.Similarly, term D score can be used to the lowest surface of particular element in implicit orientation shown in the figure.
(in the text particularly in claim) uses in text of the present invention term " " and " described " are being described and similar indicant will be understood to contain both odd number and plural number, unless clearly separately had expression at this or clearly conflicted with context.Term " comprises ", " having ", " comprising " etc. will be understood to open-ended term (that is, referring to " including but not limited to "), unless otherwise indicated.
To understand, although term first, second etc. can be used to describe different element at this, these elements do not limit by these terms.The order that these terms are only used to be mentioned in the specification and in the claims according to them distinguishes an element and another element.Thus, although an element can be called as the first element in a position of the present disclosure, identical element can be called as the second element in another location of the present disclosure.
With reference to showing the perspective view of the preferred embodiment of the present invention, sectional view and/or plane graph wherein to describe the present invention's design.In fact, region or feature can have due to manufacturing technology and/or tolerance and shown different shape or relative size.That is, the region illustrated in the drawings illustrates with exemplary form, and the shape in region is by diagramatic way not conduct restriction by presenting simply.
Unless additionally defined, all technology and scientific terminology have the identical meanings usually understood with the those of ordinary skill in the field belonging to the present invention as used herein.In addition, term " film " can be used to the separate section referring to same material layer, even if these parts are adjoined.
The first execution mode of the present invention's design is described in detail referring now to Fig. 1 to Fig. 7.
First with reference to figure 1 and Fig. 2.Here, Fig. 1 is the diagram of layout of each element of semiconductor device according to the present invention's design, and Fig. 2 is the plane graph of fin and field insulating membrane in the layout of Fig. 1.
Semiconductor device 1 according to the first execution mode of the present invention's design comprises multiple active area ACT1 to ACT2, ACT11 to ACT21 and ACT12 to ACT22, multiple fin F1 to F8, F11 to F81 and F12 to F82, multiple grid 147_1,147_2,147_5 and 147_6 and multiple dummy gate electrode 247_1 and 347_1 to 347_4.
Active area ACT1 to ACT2, ACT11 to ACT21 and ACT12 to ACT22 can arrange with a matrix type, as directed.Such as, active area ACT1 can on second direction Y1 adjacent active regions ACT11 and ACT12, and can perpendicular to adjacent active regions ACT2 on the first direction X1 of second direction Y1.Multiple active area ACT1 to ACT2, ACT11 to ACT21 and ACT12 to ACT22 can be limited by the 3rd field insulating membrane (113 in Fig. 3 describes subsequently).
At least one in fin F1 to F8, F11 to F81 and F12 to F82 be arranged on corresponding active area ACT1 to ACT2, ACT11 to ACT21 and ACT12 to ACT22 each in.Such as, multiple fin F1 to F2, F11 to F21 and F12 to F22 can be arranged in the ACT1 of active area, and multiple fin F3 to F4, F31 to F41 and F32 to F42 can be arranged in the ACT2 of active area.
Multiple fin F1 to F8, F11 to F81 and F12 to F82 longitudinally extend when all can have line form (that is, elongated horizontal cross-section) and see in plan view on second direction Y1.
Some fins (such as F1, F2, F5 and F6) can (that is, along the line on second direction Y1, therefore second direction Y1 can hereinafter referred to as " length " direction of fin) be aimed in their length direction.In addition, some fins (such as F2, F21 and F22) can (that is, on first direction X1, therefore first direction X1 also can hereinafter referred to as " width " direction of fin) be spaced apart from each other in its width direction.
As shown in Figure 2, between active area adjacent one another are on second direction Y1, the distance W2 of (such as between ACT1 and ACT11 and between ACT1 and ACT12) can be greater than the distance W1 between on second direction Y1 (that is, on the length direction of fin) first fin F1 adjacent one another are and the second fin F2.
As shown in Figure 1, mask MSK2 and MSK3 is the linear pattern of each longitudinal extension on first direction X1.But the present invention's design is not limited thereto.Mask MSK2 is the second field insulating membrane 112 for the formation of being described subsequently, and mask MSK3 is the 3rd field insulating membrane 113 for the formation of being described subsequently.
Multiple grid (active gate) 147_1,147_2,147_5 and 147_6 also can equal longitudinal extensions on first direction X1, multiple dummy gate electrode 247_1 and 347_1 to 347_4 also can on first direction X1 longitudinal extension.
Fig. 3 is the perspective view of the first execution mode of the semiconductor device according to the present invention's design, and Fig. 4 is the fin of the semiconductor device of Fig. 3 and the perspective view of field insulating membrane, and Fig. 5 is the perspective view of the fin of the semiconductor device with Fig. 3 and the substrate of groove.
Illustrate as best in Fig. 3 to Fig. 5, fin F1, F2, F5 and F6 can be the parts of substrate 101, and can comprise the epitaxial loayer of the bulk grown from substrate 101.These figures show that a group in the fin that many groups are longitudinally aimed at, wherein four fins F1, F2, F5 and F6 longitudinally aim on length direction Y1.But will understand, the present invention's design is not limited to aim at often organizing in the fin longitudinally aimed at only four fins.Exemplarily, substrate 101 can be made up of one or more semi-conducting materials being selected from the group be made up of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP.In addition, as another example, substrate can by the such as SOI(silicon-on-insulator of structure below) semiconductor layer of thereon forms.
Fin F1, F2, F5 and F6 are also shown as the form with cuboid by Fig. 3 to Fig. 5, but the present invention's design is not limited thereto.Such as, instead, fin F1, F2, F5 and F6 all can have its relatively short side (M1 and M2 of fin F1 and F2) and be chamfered or the top of sphering.On the other hand, the corresponding minor face in the relative short edge of fin adjacent one another are is in the longitudinal direction facing with each other, as illustrative by the first minor face S1 of fin the F1 facing with each other and second minor face S2 of fin F2 in the drawings.Even wherein the top of fin have cut sth. askew or sphering limit execution mode in, obviously relatively long limit M1 and M2 still can be conceived one of skill in the art by the present invention and easily differentiate with minor face S1 and S2.
Fin F1, F2, F5 and F6 form the active patterns of multiple-gate transistor device.That is, the raceway groove be connected to each other can be formed along three of fin F1, F2, a F5 and F6 limit or can be formed on the limit facing with each other of fin F1, F2, F5 and F6.
In addition, as shown in Figure 5, the first groove 501 is that long limit M1 and M2 of fin F1 and F2 demarcates.Second groove 502 is that minor face S1 and S2 of fin F1 and F2 facing with each other demarcates.Each 3rd groove 503 is that the minor face of fin F2 and F6 facing with each other and the minor face of fin F1 and F5 facing with each other are demarcated.
In the example illustrated of present embodiment, the first groove 501 and the second groove 502 are shallow trenchs, and the 3rd groove 503 is deep trench.That is, the degree of depth D3 of the 3rd groove 503 is greater than the degree of depth D1 of the first groove 501 and degree of depth D2 of the second groove 502.The degree of depth D1 of the first groove 501 and degree of depth D2 of the second groove 502 can be equal to each other when first groove 501 and the second groove 502 are formed simultaneously wherein, but can be different from each other when the first groove 501 and the second groove 502 are formed during the different phase of manufacturing process wherein.
Refer again to Fig. 3, field insulating membrane 111,112 and 113 can be arranged on the substrate 101, and around the part of fin F1, F2, F5 and F6.
In addition, in the example illustrated of present embodiment, the first field insulating membrane 111 longitudinal extension on second direction Y1, the second field insulating membrane 112 and the 3rd field insulating membrane 113 longitudinal extension on first direction X1.Exemplarily, field insulating membrane 111,112 or 113 can by oxide, nitride, nitrogen oxide or its be combined to form.
In addition, the first field insulating membrane 111 be formed in the first groove 501 at least partially in, the second field insulating membrane 112 be formed in the second groove 502 at least partially in, each 3rd field insulating membrane 113 be formed in each 3rd groove 503 at least partially in.In other words, the first field insulating membrane 111 can contact with long limit M1 with M2 of fin F1 with F2, and the second field insulating membrane 112 can contact the minor face faced by minor face S1 and S2 of fin F1 and F2.That is, the second field insulating membrane 112 contacts the sidewall surfaces of fin F1 and F2.3rd field insulating membrane 113 can contact the minor face faced by the minor face of fin F2 and F6, and another the 3rd field insulating membrane 113 can contact the minor face faced by the minor face of fin F1 and F5.
But the first field insulating membrane 111 only can occupy a part for the first groove 501, the second field insulating membrane 112 can fill the second groove the 502, three field insulating membrane 113 can fill the 3rd groove 503.In this case, the upper surface of upper surface lower than the second field insulating membrane 112 of the first field insulating membrane 111 and the upper surface of the 3rd field insulating membrane 113.In Fig. 3 and Fig. 4 (and at some other figure that this describes subsequently), the height of the first field insulating membrane 111 is H0, and the height of the second field insulating membrane 112 is H0+H1, and the height of the 3rd field insulating membrane 113 is H2.That is, the second field insulating membrane 112 can than the first field insulating membrane 111 height (or thick) H1, and the 3rd field insulating membrane 113 can than the second field insulating membrane 112 height (or thick) H2-(H0+H1).In addition, the width W 2 of the 3rd field insulating membrane 113 can be greater than the width W 1 of the second field insulating membrane 112.
Grid 147_1,147_2,147_5 and 147_6 can be arranged on fin F1, F2, F5 and F6 and to intersect with fin F1, F2, F5 and F6.Such as, the first and second grid 147_1 and 147_2 all can be arranged on the first fin F1 and to intersect with the first fin F1, and the 5th and the 6th grid 147_5 and 147_6 can be arranged on the second fin F2 and to intersect with the second fin F2.
In the example of present embodiment, only first dummy gate electrode is formed on the second field insulating membrane 112.This is illustrated by the first dummy gate electrode 247_1 be arranged on the second field insulating membrane 112 in figure 3.The layout dimension of device is retained to minimum by being provided for of single dummy gate electrode.As mentioned above, wherein field insulating membrane 112 and disposed thereon dummy gate electrode 247_1 structure be plugged on together between adjacent fin (such as F1 and F2) are referred to herein as and singly spread disconnection (single diffusion break).In addition, in the example of present embodiment, the first dummy gate electrode 247_1 narrower than the second field insulating membrane 112 (Fig. 7 see describing subsequently).Therefore, the first dummy gate electrode 247_1 stably can be formed on the second field insulating membrane 112 and to be supported by the second field insulating membrane 112.
In addition, in the example of present embodiment, the second dummy gate electrode 347_1 is formed on the 3rd field insulating membrane 113 and the first fin F1, and the 3rd dummy gate electrode 347_2 is formed on the 3rd field insulating membrane 113 and the 5th fin F5.Similarly, the 4th dummy gate electrode 347_3 is formed on the 3rd field insulating membrane 113 and the second fin F2, and the 5th dummy gate electrode 347_4 is formed on the 3rd field insulating membrane 113 and the 6th fin F6.Comprise the structure being plugged on field insulating membrane 113 between adjacent fin (such as F1 and F5) and disposed thereon two dummy gate electrode (such as 347_1 and 347_2) to be referred to herein as double diffusion and to disconnect (doublediffusion break).
With reference now to Fig. 6 A and Fig. 7, wherein Fig. 6 A is the example cross section intercepted along the line A-A of Fig. 3, and Fig. 7 is the example cross section intercepted along the line B-B of Fig. 3.
Each grid (such as 147_1) can comprise two or more metal levels MG1 and MG2.In this case, the first metal layer MG1 is for adjusting work function.For this reason, the first metal layer MG1 can such as be formed by least one material being selected from the group be made up of TiN, TaN, TiC and TaC.On the other hand, the second metal level MG2 is for filling the space stayed by the first metal layer MG1.Second metal level MG2 can such as be formed by W or Al.Grid 147_1 can pass through replacing process (or rear grid technique) or other already known processes formation in essence.
Each dummy gate electrode (such as 247_1) can have the cross section structure being similar to grid 147_1.Such as, in the embodiment as shown, dummy gate electrode 247_1 comprises two metal level MG1 and MG2 with the shape of cross section identical with grid 147_1 and size and identical component.
Gate insulating film 145 is plugged between the first fin F1 and grid 147_1.As shown in Figure 6A, gate insulating film 145 can extend on the upper surface of the first fin F1 and in the upper part of the side surface of the first fin F1.In addition, gate insulating film 145 can be plugged between grid 147_1 and the first field insulating membrane 111.Gate insulating film 145 can comprise high-k dielectric, namely has the material of the dielectric constant higher than the dielectric constant of Si oxide.Exemplarily, gate insulating film 145 can be the film of HfO2, ZrO2 or Ta2O5.
As shown in Figure 7, multiple source/drain 161 and 162 can be provided in multiple between grid 147_1,147_2,147_5 and 147_6 and between grid (such as 147_1) and dummy gate electrode (such as 247-1).Source/drain 161 and 162 can be the source/drain of lifting outstanding on the level of the upper surface of fin F1, F2, F5 and F6.In addition, source/drain 161 and 162 can be formed as making its sept 151 and/or 251 and/or 351 that partly overlaps.In the example in figure 7, the side of source/drain 161 is aimed at the outward flange of sept 251, the opposite side section gap thing 151 of source/drain 161, the part of source/drain 162 section gap thing 151 and 351.
The upper surface copline in fact of the upper surface being arranged in each source/drain 162 between the neighboring gates in grid 147_1,147_2,147_5 and 147_6 and one that is arranged in grid 147_1,147_2,147_5 and 147_6 each source/drain 161 between grid and corresponding dummy gate electrode 247_1.At this, there are some vertical shifts by thinking due to the error naturally existed in a manufacturing process in the use of term " in fact " in surface.
When semiconductor device 1 is PMOS transistor, source/drain 161 and 162 can comprise compression and to induct material.Such as, compression material of inducting can be the material compared with Si with macrolattice constant, such as, can be SiGe.Compression inducts material can by improve the mobility of charge carrier in channel region to the first fin F1 applying compression.
On the other hand, when semiconductor device 1 is nmos pass transistor, source/drain 161 and 162 can have the material identical with substrate 101 or tensile stress and to induct material.Such as, if substrate 101 is made up of Si, then source/drain 161 and 162 can be Si, can be maybe the material (such as, SiC) with the lattice constant less than silicon.
Under arbitrary situation of PMOS and NMOS, described structure can to form groove, then manufacture in groove epitaxial growth source/drain regions 161 and 162 by utilizing active gate and dummy gate electrode in the first fin F1 as etching mask.
In another example of present embodiment, source/drain can by being formed with impurity doping fin F1 and F2.
Sept 151 and 251 can comprise at least one in nitride film and oxynitride film.Sept 151 and 251 can be formed in the sidewall surfaces of multiple fin F1 and F2, multiple grid 147_1,147_2,147_5 and 147_6 and multiple dummy gate electrode 247_1.
In the example of present embodiment shown in Figure 7, the upper surface of the second field insulating membrane 112 can be positioned on the planar S UR1 identical with the upper surface of adjacent fin F1 with F2.The upper surface of the 3rd field insulating membrane 113 is positioned on the planar S UR1 identical with the upper surface of F5 with adjacent fins F1.But again, term " in fact " is used to contain the error naturally existed in a manufacturing process, and it may cause the slight shift from common plane in upper surface.Therefore, the height L1 being formed in the grid (such as 147_1) on fin (such as F1) can equal to be formed in the height L2 of dummy gate electrode 247_1 on the second field insulating membrane 112 and the 3rd field insulating membrane 113 and 347_1 to 347_4.That is, the change of the height L1 of multiple grid 147_1,147_2,147_5 and 147_6 can reduce greatly.As mentioned above, grid 147_1,147_2,147_5 and 147_6 can utilize metal to be formed, and the change in the middle of the height of grid 147_1,147_2,147_5 and 147_6 causes operating characteristic also to change.Therefore, because the height of grid is in fact identical, so the operating characteristic of grid 147_1,147_2,147_5 and 147_6 is in fact homogeneous.
In addition, the upper surface of the 3rd field insulating membrane 113 can be positioned on the planar S UR1 identical with the upper surface of the second field insulating membrane 112.
In addition, the second field insulating membrane 112 is wider than dummy gate electrode 247_1.Therefore, dummy gate electrode 247_1 stably can be supported by the second field insulating membrane 112.
In addition, the Part I 166a forming the semiconductor layer of fin F1 can be plugged on the second field insulating membrane 112(or the second groove 502) and source/drain 161 between.In addition, the Part II 166 forming the semiconductor layer of fin F1 can be plugged on the 3rd field insulating membrane 113(or the 3rd groove 503) and source/drain 162 between.As shown in Figure 7, the width E1 of the Part I 166a of semiconductor layer is less than the width E2 of the Part II 166 of semiconductor layer.In other words, the part 166a be positioned at below single diffusion disconnection just of semiconductor layer can be less than the part 166 be positioned at below double diffusion disconnection just.
Fig. 6 B is the example cross section intercepted along the line D-D of Fig. 1, which show the example of the source/drain overlap of adjacent fins.With reference to figure 6B, in this example, source/drain 1161a and 1161b is formed on the upper fin (F1 and F11 in such as Fig. 1) adjacent one another are of Width (the first direction X1 in Fig. 1).As shown, source/drain 1161a and 1161b can contact with each other or can be in conjunction with.This can be caused by the combination of epitaxial grown material, and/or is caused by the overlap of diffusion region.Therefore, electrically equal voltage signal can be applied on it.This combination or overlap (on X1 direction) can occur about the source/drain 161 and/or 162 shown in Fig. 7, although the present invention's design is not limited thereto.
Describe the second execution mode of the semiconductor device according to the present invention's design referring now to Fig. 8 A, Fig. 8 B and Fig. 8 C, Fig. 8 A, Fig. 8 B and Fig. 8 C are the sectional views of the respective examples that the second execution mode is shown.In order to avoid redundancy, be omitted with the detailed description of the element of same or similar second execution mode of the element of the first execution mode described before.
In the example of the semiconductor device 2a illustrated in fig. 8 a, the upper surface of the 3rd field insulating membrane 113 is lower than the upper surface of adjacent fin F1 or F5.As shown, the upper surface of the second field insulating membrane 112 is positioned in fact on the planar S UR1 identical with the upper surface of fin F1 or F2.In addition, the upper surface of the second field insulating membrane 112 can be arranged on the level place higher than the upper surface of fin F1 or F2.Therefore, the upper surface of the 3rd field insulating membrane 113 can be arranged on the level place lower than the upper surface of the second field insulating membrane 112.
In addition, the height H 2b of the 3rd field insulating membrane 113 can lower than the height H 1+H0 of the second field insulating membrane 112.
Because the upper surface of the 3rd field insulating membrane 113 is arranged on the level place lower than the upper surface of adjacent fin F1 or F5, so the second dummy gate electrode 347_1 part can be positioned on the upper surface of fin F1, its another part can be arranged in the 3rd groove 503.A part of the 3rd dummy gate electrode 347_2 can be positioned on the upper surface of fin F5, and its another part can be arranged in the 3rd groove 503.
In addition, the part of metal level MG1 and MG2 of the second dummy gate electrode 347_1 can be arranged in the 3rd groove 503.That is, metal level MG1 and MG2 of the second dummy gate electrode 347_1 can be formed along the upper surface of the side of the 3rd groove 503 and fin F1.In addition, the part of metal level MG1 and MG2 of the 3rd dummy gate electrode 347_2 also can be arranged in the 3rd groove 503.That is, metal level MG1 and MG2 of the 3rd dummy gate electrode 347_2 can be formed along the upper surface of the side of the 3rd groove 503 and fin F5.Metal level MG1 and MG2 of the second dummy gate electrode 347_1 and metal level MG1 and MG2 of the 3rd dummy gate electrode 347_2 is the material for adjusting work function.
In the example of the semiconductor device 2b shown in Fig. 8 B, the metal level MG2 that the metal level MG1 of the second dummy gate electrode 347_1 is arranged in the 3rd groove 503, second dummy gate electrode 347_1 is outstanding on the level of fin F1.The metal level MG1 of the second dummy gate electrode 347_1 extends along the side of the 3rd groove 503 and the upper surface of fin F1.In addition, the metal level MG1 of the 3rd dummy gate electrode 347_2 metal level MG2 that is arranged in the 3rd groove the 503, three dummy gate electrode 347_2 is outstanding on the level of fin F5.The metal level MG1 of the 3rd dummy gate electrode 347_2 extends along the side of the 3rd groove 503 and the upper surface of fin F5.
In the example of the semiconductor device 2c shown in Fig. 8 C, metal level MG1 and MG2 of the second dummy gate electrode 347_1 is arranged in the 3rd groove 503 completely, and the sept 351 only on the side of the second dummy gate electrode 347_1 extends on the upper surface of fin F1.Metal level MG1 and MG2 of the 3rd dummy gate electrode 347_2 is arranged in the 3rd groove 503 completely, and the sept 351 only on the side of the 3rd dummy gate electrode 347_2 extends on the upper surface of fin F5.
3rd execution mode of the semiconductor device 3 according to the present invention's design is described referring now to Fig. 9.In order to avoid redundancy, be omitted with the detailed description of the element of same or similar 3rd execution mode of the element of the first and second execution modes described before.
In semiconductor device 3, the upper surface of the second field insulating membrane 112 is arranged on the level place higher than the upper surface of adjacent fin F1 or F2.The upper surface of the 3rd field insulating membrane 113 also can be arranged on the level place higher than the upper surface of adjacent fin F1 or F5.In addition, the upper surface of fin F1, F2 and F5 can be arranged in planar S UR1, and the upper surface of the second field insulating membrane 112 and the upper surface of the 3rd field insulating membrane 113 can be arranged in identical planar S UR2.The height of the second field insulating membrane 112 can be H1a+H0, and the height of the 3rd field insulating membrane 113 is H2.
Therefore, the height L3 of the first dummy gate electrode 247_1 is less than the height L1 of grid 147_1.Because the first dummy gate electrode 247_1 and grid 147_1 utilizes replacing process to be formed, the upper surface of the upper surface of the first dummy gate electrode 247_1 and grid 147_1 is positioned in identical plane.In addition, because the height being positioned at the second field insulating membrane 112 in the lower part of the first dummy gate electrode 247_1 is less than the height of the fin F1 in the lower part being positioned at grid 147_1, the height L3 of the first dummy gate electrode 247_1 is less than the height L1 of grid 147_1.
Because the upper surface of the 3rd field insulating membrane 113 is arranged on the level place higher than the upper surface of adjacent fin F1 or F5, so the second dummy gate electrode 347_1 part can be positioned on the upper surface of fin F1, its another part can be positioned on the 3rd outstanding field insulating membrane 113.A part of the 3rd dummy gate electrode 347_2 can be positioned on the upper surface of fin F5, and its another part can be positioned on the 3rd outstanding field insulating membrane 113.
The upper surface of upper surface and the 3rd field insulating membrane 113 that Fig. 9 shows the second field insulating membrane 112 is positioned on identical planar S UR2.But alternatively, the upper surface of the second field insulating membrane 112 and the upper surface of the 3rd field insulating membrane 113 can be positioned in different planes.
4th execution mode of the semiconductor device 4 according to the present invention's design is described referring now to Figure 10.In order to avoid redundancy, be omitted with the detailed description of the element of same or similar 4th execution mode of the element of the describe before first to the 3rd execution mode.
In semiconductor device 4, single diffusion disconnection is formed between fin F1 and fin F2, and single diffusion disconnects and is also formed in (namely between fin F1 and fin F5) between active area ACT1 and active area ACT12.That is, only a dummy gate electrode 347_1 is arranged on the 3rd field insulating membrane 113 between adjacent active area.
In addition, the upper surface of the 3rd field insulating membrane 113 can be positioned on the planar S UR1 identical with the upper surface of fin with the upper surface of the second field insulating membrane 112.
On the other hand, in order to the clearly isolation between active area ACT1 and active area ACT12,3rd field insulating membrane 113 can have relatively large height H 2c(such as, deeper can extend to substrate 101 from the planar S UR1 of the upper surface of fin F1 and F2 than the second field insulating membrane 112).
5th execution mode of the semiconductor device 5 according to the present invention's design is described referring now to Figure 11.In order to avoid redundancy, be omitted with the detailed description of the element of same or similar 5th execution mode of the element of first to fourth execution mode described before.
In semiconductor device 5, the second field insulating membrane 112 has T section in vertical plane.
Particularly, the second field insulating membrane 112 comprises the protuberance 1122 in the sidepiece of the upper part being projected into fin F1 and F2 respectively.The thickness of protuberance 1122 can from
arrive
scope in.
Due to such protuberance 1122, even if there is alignment error in the process forming dummy gate electrode 247_1, there is the high likelihood that dummy gate electrode 247_1 will still be formed on the second field insulating membrane 112.In addition, if dummy gate electrode 247_1 is formed on fin (such as F1 or F2) instead of on the second field insulating membrane 112, then defect (such as bridge defects) may occur between dummy gate electrode 247_1 and fin F1 or F2.
3rd field insulating membrane 113 also can have similar T section.
In the above-described embodiment, it should be noted that term " dummy gate electrode " not necessarily refers to the conductive trace (or wiring) forming dummy gate electrode and do not have electrically functional along its whole length.Then, this aspect of the execution mode of the present invention's design is discussed with reference to the plane graph of figure 12A and the sectional view of Figure 12 B.
With reference to figure 12A and Figure 12 B, in semiconductor device 6, grid 1247_1 is longitudinal extension on first direction X1.Grid 1247_1 can work as the dummy gate electrode in the I of first area, and can work as normal (that is, electricity the is active) grid in second area II.That is, as shown, grid 1247_1 can be arranged on field insulating membrane 1112(corresponding to the film 112 in Fig. 3 in the I of first area) on to be used as dummy gate electrode, and can intersect with as normal gate in second area II with fin F99.
In this case, grid 1247_1 can have different thickness.Such as, the thickness of the grid 1247_1 on the field insulating membrane 1112 in the I of first area can be L11, and the thickness of the grid 1247_1 on the fin F99 in second area II can be L10>L11.On the other hand, because grid 1247_1 is made by flatening process, thus the upper surface of grid 1247_1 can in I and II of region copline.
Hereinafter, the illustrative methods of the manufacture semiconductor device according to the present invention's design is described with reference to the plane graph of Figure 13 to Figure 22 and perspective view.In order to these objects, the manufacture with reference to display in Fig. 1 to Fig. 7 and referring to figs. 1 to the device of the type of Fig. 7 description describes the method.But it will be easily significantly that the method is applicable to manufacture according to other execution mode of the semiconductor device of the present invention's design.
First, formed on the substrate 101 with reference to Figure 13 and Figure 14, mask MSK, multiple elementary fin PF1 to PF7 and PF11 to PF71 utilizes mask MSK to be formed.More specifically, shallow trench 501 and 502 is formed by utilizing mask MSK to carry out etching substrates 101 as etching mask, to form elementary fin PF1 to PF7 and PF11 to PF71.
Multiple elementary fin PF1 to PF7 and PF11 to PF71 longitudinal extension on second direction Y1.Multiple elementary fin PF1 to PF7 and PF11 to PF71 can be arranged to matrix.In this case, such as, elementary fin PF1 and elementary fin PF11 can aim in their length direction, and elementary fin PF1 and elementary fin PF2 can be arranged in its width direction adjacent to each other.
With reference to Figure 15, dielectric film 2111 is formed as around multiple elementary fin PF1 to PF7 and PF11 to PF71 and mask MSK.Particularly, insulating barrier is formed as covering multiple elementary fin PF1 to PF7 and PF11 to PF71 and mask MSK completely, and insulating barrier is flattened until expose the upper surface of mask MSK.Here, dielectric film 2111 can by oxide, nitride, nitrogen oxide or its be combined to form.
With reference to Figure 16 and Figure 17, then, deep trench 503 and 504 is formed by etching away the part of the part of multiple elementary fin PF1 to PF7 and PF11 to PF71, the part of mask MSK and dielectric film 2111.As a result, multiple active area ACT1, ACT2, ACT11, ACT21, ACT12 and ACT22 is defined.In addition, multiple fin F1 to F2, F11 to F21 and F12 to F22 are formed by multiple elementary fin PF1 to PF7 and PF11 to PF71.In this respect, consider that elementary fin PF1 to PF7 and PF11 to PF71, mask MSK and dielectric film 2111 are etched simultaneously, the dry etching process not having high etch-selectivity can be used.
Each deep trench 503 is formed as longitudinal extension on first direction X1, and each deep trench 504 is formed as longitudinal extension on second direction Y1.Deep trench 503 and 504 is intersected with each other.
With reference to Figure 18, then, dielectric film 2211 is formed as filling deep trench 503 and 504.Particularly, insulating barrier is formed as covering multiple fin F1 to F2, F11 to F21 and F12 to F22 and mask MSK completely, and insulating barrier is flattened until expose the upper surface of mask MSK.Dielectric film 2211 can by oxide, nitride, nitrogen oxide or its be combined to form.Dielectric film 2211 can be made up of the material identical from dielectric film 2111 or different materials.
With reference to Figure 19, then, the sidewall of mask MSK exposes by removing the upper part of dielectric film 2211 and dielectric film 2111, such as, expose by eat-backing dielectric film 2211 and 2111.
With reference to Figure 20, then, the mask MSK of exposure is removed.
Be formed in the region of formation second field insulating membrane 112 with reference to Figure 21 and Figure 22, mask MSK2, mask MSK3 is formed in each region of formation the 3rd field insulating membrane 113.Mask MSK2 and MSK3 can be formed as longitudinal extension on first direction X1.
Then, mask MSK2 and MSK3 is utilized as etching mask to perform the recessed technique in field.That is, the part of dielectric film 2211 and the part of dielectric film 2111 are removed to form the first field insulating membrane 111 and the second field insulating membrane 112 by controlled etch technique, leave the 3rd field insulating membrane 113 simultaneously.Because the recessed technique in field, expose the upper part of sidewall of fin F1 to F2, F11 to F21 and F12 to F22.In addition, the second field insulating membrane 112 and the 3rd field insulating membrane 113 to the first field insulating membrane 111 extend higher.
Refer again to Fig. 1 and Fig. 3, multiple transistor gate (such as 147_1,147_2,147_5 and 147_6) is formed on each fin (such as F1, F2, F11, F21, F12 and F22) in each active area (such as ACT1), and multiple dummy gate electrode (such as 247_1,347_1 and 347_3) is formed in and makes the fin of each active area separated from one another and on first, second, and third field insulating membrane 111,112 and 113 that active area is separated from each other.
Such as, in the representative part of the first execution mode, multiple grid 147_1,147_2 are formed in intersect on each fin F1, F11 and F12 and with each fin F1, F11 and F12 and extend, and each fin F2, F21 and F22 that multiple grid 147_5 and 147_6 is formed in the first active area ACT1 intersect with each fin F2, F21 and F22 of the first active area ACT1 and extend.Dummy gate electrode 247_1 be formed in the ACT1 of active area make fin F1, F11 and F12 and fin F2, F21 be separated with F22 respectively the second field insulating membrane 112 on, dummy gate electrode 347_1 be formed in active area ACT1 is separated with active area ACT12 the 3rd field insulating membrane 113 on, dummy gate electrode 347_2 be formed in active area ACT1 is separated with active area ACT11 the 3rd field insulating membrane 113 on.
Figure 23 shows the example of the electronic device 7 of the semiconductor device of the one or more above-mentioned execution mode that can comprise according to the present invention's design.
Electronic device 7 has logic area 1410 and SRAM district 1420, and logic area 1410 and each of SRAM district 1420 can comprise such as transistor device described herein.In addition, different types of diffusion disconnection can be used in logic area 1410 and SRAM district 1420.Such as, single diffusion disconnection can be used in logic area 1410, and double diffusion disconnects and can be used in SRAM district 1420.
Figure 24 shows the example of the electronic system 1100 of the semiconductor device comprised according to the present invention's design.
The electronic system 1100 of this example comprises controller 1110, I/O (I/O) device 1120, memory 1130, interface 1140 and bus 1150.Controller 1110, I/O device 1120, memory 1130 and/or interface 1140 can be coupled mutually by bus 1150.The path that bus 1150 provides data to be transmitted by it.
At least one that controller 1110 can comprise microprocessor, digital signal processor, microcontroller and can perform in the logic element of similar functions.I/O device 1120 can comprise keyboard, key plate and/or display device.Memory 1130 can store data and/or order.Interface 1140 may be used for transmitting data to communication network or receiving data from communication network.Interface 1140 can be wired or wireless type.Such as, interface 1140 can comprise antenna or wire/wireless transceiver.Although not shown, electronic system 1100 can also comprise high-speed DRAM and/or the SRAM operational store as the operation for improving controller 1110.Device 1130 can be stored according to the semiconductor device of one or more execution modes of the present invention's design to adopt, or a part for controller 1110 and I/O device 1120 can be provided as.
Electronic system 1100 can be PDA(personal digital assistant), laptop computer, net book, radio telephone such as mobile phone, digital music player, storage card or can wirelessly launch and/or receive any other dissimilar electronic device of information.
Finally, the execution mode of the present invention's design is being described in detail above with its example.But the present invention's design can be implemented in many different forms, and should not be understood to be limited to execution mode described above.But, describe these execution modes and make the disclosure comprehensively with complete, and the present invention will be passed on to conceive to those skilled in the art comprehensively.Thus, the present invention design practicalness and scope by execution mode described above and example restriction but be defined by the claims.
This application claims the priority enjoying the 10-2013-0099402 korean patent application that on August 22nd, 2013 submits in Korean Intellectual Property Office, it is open is incorporated into this by quoting in full.In addition, the 14/021st of the common transfer that the disclosure and on September 9th, 2013 submit to, No. 465 U.S.'s non-provisional applications are relevant, and it is openly incorporated into this by quoting in full.
Claims (20)
1. a semiconductor device, comprising:
Substrate, the first fin, the second fin and the 3rd fin that there is the first groove and the second groove and longitudinally aim in a first direction, wherein said first groove extends between described first fin and described second fin, and described second groove extends between described second fin and described 3rd fin;
The field Part I of insulating material and the Part II of field insulating material, the Part I of described field insulating material is arranged in described first groove be plugged between described first fin and described second fin, the Part II of described field insulating material is arranged in described second groove be plugged between described second fin and described 3rd fin, and the upper surface of the Part II of the wherein said field insulating material level place in described second groove below the upper space of described second fin and described 3rd fin is recessed;
Multiple active gate, is arranged on described first fin, described second fin and described 3rd fin;
First dummy gate electrode, is arranged on the upper surface of the Part I of described field insulating material; And
Second dummy gate electrode, extends to the described upper surface to the Part II of described field insulating material in described second groove at least in part.
2. semiconductor device according to claim 1, the degree of depth of wherein said first groove is less than the degree of depth of described second groove.
3. semiconductor device according to claim 2, wherein said first groove width is in said first direction less than described second groove width in said first direction.
4. semiconductor device according to claim 1, also comprise and stride across described second groove three dummy gate electrode relative with described second dummy gate electrode, described 3rd dummy gate electrode extends to the described upper surface to the Part II of described field insulating material in described second groove at least in part.
5. semiconductor device according to claim 1, the Part I of wherein said second dummy gate electrode extends above the upper surface of described second fin adjacent with the edge of described second groove, and the Part II of described second dummy gate electrode extends to the described upper surface of the Part II of described field insulating material along the sidewall of described second groove.
6. semiconductor device according to claim 5, wherein said second dummy gate electrode comprises the first metal layer of wherein restriceted envelope and occupies second metal level in described space, and
The described Part I of wherein said second dummy gate electrode and described both Part II comprise described the first metal layer and described second metal level.
7. semiconductor device according to claim 5, wherein said second dummy gate electrode comprises the first metal layer of wherein restriceted envelope and occupies second metal level in described space, and
The only described Part I of wherein said second dummy gate electrode comprises described the first metal layer and described both second metal levels, makes the described space limited by described the first metal layer completely on the level of the described upper surface of described second fin.
8. semiconductor device according to claim 5, the second sidewall spacer that wherein said second dummy gate electrode is included in the first side wall sept above the described upper surface of described second fin and extends above the described upper surface of the Part II of described field insulating material in described second groove.
9. semiconductor device according to claim 1, wherein said second dummy gate electrode comprises at least one metal level, above whole described upper surfaces being positioned at the Part II of described field insulating material of at least one metal level described.
10. semiconductor device according to claim 9, wherein said second dummy gate electrode comprises the first metal layer of wherein restriceted envelope and occupy second metal level in described space, above described the first metal layer and the whole described upper surfaces being positioned at the Part II of described field insulating material both the second metal level.
11. semiconductor device according to claim 1, are also included in the source/drain regions between neighboring active grid, between described first dummy gate electrode and a neighboring active grid and between described second dummy gate electrode and another neighboring active grid.
12. semiconductor device according to claim 11, wherein said source/drain regions is that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
13. 1 kinds of semiconductor device, comprising:
Substrate, comprises the first active area and the second active area, and described first active area comprises the first groove, is demarcated by the second groove be plugged on therebetween in described first active area and described second active area;
The multiple parallel group of the first fin longitudinally aimed in a first direction, the second fin and the 3rd fin, described first fin of each group and described second fin are included in described first active area, described 3rd fin of each group is included in described second active area, wherein said first groove extends between described first fin of each group and described second fin, and described second groove extends between described second fin of each group and described 3rd fin;
The field Part I of insulating material and the Part II of field insulating material, the Part I of described field insulating material is arranged in described first groove be plugged between described first fin of each respective sets and described second fin, the Part II of described field insulating material is arranged in described second groove between described second fin and described 3rd fin being plugged on each respective sets, and the upper surface of the Part II of the wherein said field insulating material level place in described second groove below the upper space of described second fin of each respective sets and described 3rd fin is recessed;
Multiple active gate, is arranged on described first fin of each group, described second fin and described 3rd fin;
First dummy gate electrode, is arranged on the upper surface of the Part I of corresponding field insulating material;
Second dummy gate electrode, extends to the described upper surface to the Part II of the corresponding field insulating material adjacent to described second fin of each group in described second groove at least in part; And
3rd dummy gate electrode, extends to the described upper surface to the Part II of the corresponding field insulating material adjacent to described 3rd fin of each group in described second groove at least in part.
14. semiconductor device according to claim 13, the degree of depth of wherein said first groove is less than the degree of depth of described second groove, and wherein said first groove width is in said first direction less than described second groove width in said first direction.
15. semiconductor device according to claim 13, wherein the Part I of each second dummy gate electrode extends above the upper surface of the second corresponding fin adjacent to the edge of described second groove, the Part II of each second dummy gate electrode extends to the described upper surface of the Part II of described field insulating material along the sidewall of described second groove, and
Wherein the Part I of each 3rd dummy gate electrode extends above the upper surface of the 3rd corresponding fin adjacent to the opposite edges of described second groove, and the Part II of each 3rd dummy gate electrode extends to the described upper surface of the Part II of described field insulating material along the opposing sidewalls of described second groove.
16. semiconductor device according to claim 15, wherein said active gate and each of described first dummy gate electrode, described second dummy gate electrode and described 3rd dummy gate electrode comprise the first metal layer of wherein restriceted envelope and occupy second metal level in described space, and
The described Part I of wherein said second dummy gate electrode and described 3rd dummy gate electrode and described both Part II comprise described the first metal layer and described second metal level.
17. semiconductor device according to claim 15, wherein said active gate and each of described first dummy gate electrode, described second dummy gate electrode and described 3rd dummy gate electrode comprise the first metal layer of wherein restriceted envelope and occupy second metal level in described space, and
The only described Part I of wherein said second dummy gate electrode and described 3rd dummy gate electrode comprises described the first metal layer and described both second metal levels, makes the described space that limited by described the first metal layer completely on the level of the described upper surface of corresponding second fin and the 3rd fin.
18. semiconductor device according to claim 13, wherein each described second dummy gate electrode the second sidewall spacer of being included in the first side wall sept above the described upper surface of corresponding second fin and extending above the described upper surface of the Part II of described field insulating material in described second groove, and
Wherein each described 3rd dummy gate electrode the 4th sidewall spacer of being included in the 3rd sidewall spacer above the described upper surface of corresponding 3rd fin and extending above the described upper surface of the Part II of described field insulating material in described second groove.
19. semiconductor device according to claim 13, wherein said second dummy gate electrode and each of described 3rd dummy gate electrode comprise the first metal layer of wherein restriceted envelope and occupy second metal level in described space, above whole described upper surfaces being positioned at the Part II of described field insulating material of described the first metal layer and described both second metal levels.
20. semiconductor device according to claim 13, also be included in the source/drain regions between neighboring active grid, between each first dummy gate electrode and a neighboring active grid, between each second dummy gate electrode and another neighboring active grid and between each 3rd dummy gate electrode and another neighboring active grid, and
Wherein said source/drain regions is that induct material or tensile stress of compression is inducted the epitaxial region of one of them of material.
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20150022091A (en) | 2015-03-04 |
| US8878309B1 (en) | 2014-11-04 |
| JP6291694B2 (en) | 2018-03-14 |
| KR102025309B1 (en) | 2019-09-25 |
| CN107248503A (en) | 2017-10-13 |
| TW201508838A (en) | 2015-03-01 |
| TWI623978B (en) | 2018-05-11 |
| CN104425493B (en) | 2019-01-04 |
| CN107248503B (en) | 2020-11-10 |
| JP2015041771A (en) | 2015-03-02 |
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