CN107393921A - Semiconductor devices and its manufacture method - Google Patents

Semiconductor devices and its manufacture method Download PDF

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Publication number
CN107393921A
CN107393921A CN201710346560.6A CN201710346560A CN107393921A CN 107393921 A CN107393921 A CN 107393921A CN 201710346560 A CN201710346560 A CN 201710346560A CN 107393921 A CN107393921 A CN 107393921A
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active patterns
along
area
double diffusion
interruptive area
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CN201710346560.6A
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CN107393921B (en
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吴旼哲
朴世镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to CN202310300354.7A priority Critical patent/CN116344582A/en
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclose a kind of semiconductor devices and its manufacture method.This method includes：Active patterns are formed on substrate, the substrate includes the first logic cells area and the second logic cells area adjacent to each other in a first direction；And the device isolation layer on the top of exposure active patterns is formed on substrate.Forming active patterns includes：Formation extends parallel to each other and across the First Line mask pattern of the first logic cells area and the second logic cells area in a first direction；Separating mask pattern on being formed on First Line mask pattern, upper separating mask pattern include the first opening of at least two in overlapping First Line mask pattern；The first hard mask pattern is formed from least two First Lines mask pattern；And substrate is etched to form the groove of restriction active patterns.

Description

Semiconductor devices and its manufacture method
Technical field
Here the embodiment discussed relates generally to semiconductor devices and its manufacture method, more particularly, to including The semiconductor devices and its manufacture method of fin formula field effect transistor.
Background technology
Semiconductor devices includes the integrated circuit being made up of MOS (metal-oxide semiconductor (MOS)) FET.With semiconductor devices Size and design rule reduce, the MOSFET of integrated circuit also reduces.When MOSFET becomes smaller, can produce in MOSFET Short-channel effect, and therefore the operating characteristic of semiconductor devices can deteriorate.
The content of the invention
The embodiment of present inventive concept provides semiconductor devices and its manufacture method with improved reliability.
According to some exemplary embodiments of present inventive concept, a kind of method being used for producing the semiconductor devices can wrap Include：Active patterns are formed on substrate, the substrate includes the first logic cells area adjacent to each other along a first direction and the Two logic cells areas；And the device isolation layer on the top of exposure active patterns is formed on substrate.Form active patterns Step can include：Formation extends parallel to each other and across the first logic cells area and the second logic list along a first direction The First Line mask pattern in first region；Separating mask pattern on being formed on First Line mask pattern, wherein upper separating mask figure Case is located on the first module border between the first logic cells area and the second logic cells area, and including overlapping first At least two the first opening in line mask pattern；The first etching work is performed using upper separating mask pattern as etching mask Skill, to form the first hard mask pattern from least two First Lines mask pattern；And by using the first hard mask figure Case etches the top of substrate to form the groove of restriction active patterns as the second etch process of etching mask.
According to some exemplary embodiments of present inventive concept, a kind of semiconductor devices can include：Substrate, it includes The multiple logic units set along a first direction；Active patterns；And the device isolation layer on substrate.Device isolation layer can With including：First double diffusion interruptive area, its there is the first width for measuring along a first direction and be arranged on a pair it is adjacent Between logic unit；And the second double diffusion interruptive area, it has be more than the first width the measured along a first direction Two width are simultaneously arranged between the adjacent logic unit of another pair.Active patterns can include：Multipair first active patterns, each pair In the first active patterns be spaced apart from each other along a first direction and make the first double diffusion interruptive area plant therebetween；It is and more To the second active patterns, the second active patterns per centering are spaced apart from each other and make the second double diffusion discontinuity area along a first direction Plant therebetween in domain.First active patterns can be included with the side of the first double diffusion interruptive area adjacent and along intersecting first The second direction in direction first end aligned with each other.Second active patterns can include one with the second double diffusion interruptive area The adjacent the second end in side, and one in the second end can along a first direction from the second end another is inclined Move.
According to some exemplary embodiments, a kind of semiconductor devices can include：Substrate, it is included along a first direction First module region and second unit region adjacent to each other, first module border plant therebetween and along intersect first direction Second direction extension；First active patterns, it is arranged on first module region and second unit region along second direction, Each extension along a first direction of first active patterns does not still intersect first module border；Device isolation layer, it is in substrate Go up and expose the top of active patterns.Device isolation layer can include：First double diffusion interruptive area, it is single that it is arranged on first On first border and the first paired active patterns on different unit areas and along a first direction adjacent to each other it Between, first active patterns are at least two pairs；And the first single diffusion interruptive area, it is arranged on from by first module area Selected in the group that domain and second unit region are formed it is at least one on, and on same unit region and along first party To each other between the first adjacent pairs of active patterns.Semiconductor devices can also include the grid for intersecting the first active patterns Pattern.
According to some exemplary embodiments, a kind of semiconductor devices can include：Substrate, it is included along a first direction First module region and second unit region adjacent to each other, elementary boundary are plugged on first module region and second unit region Between and along intersect first direction second direction extend；Active patterns, it is arranged in first module region along second direction On second unit region, each of active patterns extends still not cross unit border along a first direction；Device isolation layer, It is on substrate and exposes the part of active patterns, and the part that is exposed of wherein active patterns includes active fin, and wherein device Part separation layer includes double diffusion interruptive area, and the double diffusion interruptive area is arranged on elementary boundary and positioned at first module On region and second unit region and along a first direction between paired active patterns adjacent to each other, the active patterns are At least two pairs；Gate pattern, it arranges and intersects active fin along second direction along a first direction；And first source/drain Polar region domain, it is disposed in the top of the active patterns between the adjacent gate pattern in gate pattern, wherein the first source At least one in pole/drain region is including epitaxial layer and has the top parallel with least one top surface in active patterns Surface.
Brief description of the drawings
Fig. 1 is the top view for the semiconductor devices for showing some exemplary embodiments according to present inventive concept.
Fig. 2A is active in the semiconductor devices according to some exemplary embodiments of present inventive concept for illustrating The figure of the configuration of pattern, more specifically, being to show the boundary member between Fig. 1 the first logic unit and the second logic unit The top view of one example.
Fig. 2 B are the top views of a part for the semiconductor devices for the active patterns for exemplarily showing to include Fig. 2A.
Fig. 3 A are active in the semiconductor devices according to some exemplary embodiments of present inventive concept for illustrating The figure of the configuration of pattern, more specifically, being to show the boundary member between Fig. 1 the first logic unit and the second logic unit The top view of one example.
Fig. 3 B are the top views for exemplarily showing to include a part for the semiconductor devices of Fig. 3 A active patterns.
Fig. 4 is to show that the double diffusion in the semiconductor devices according to some exemplary embodiments of present inventive concept is interrupted The top view of one example of the arrangement in region.
Fig. 5 A to Figure 15 A be show according to some exemplary embodiments of present inventive concept be used to manufacture include it is active The top view of the method for the semiconductor devices of pattern.
Fig. 5 B to Figure 15 B are the sectional views respectively along Fig. 5 A to Figure 15 A line I-I' and II-II' interception.
Fig. 5 C to Figure 15 C are the sectional views respectively along Fig. 5 A to Figure 15 A line III-III' and IV-IV' interception.
Embodiment
Fig. 1 is the top view for the semiconductor devices for showing some exemplary embodiments according to present inventive concept.
Reference picture 1, multiple logic unit C1, C2, C3 and C4 can be provided in the exemplary implementation according to present inventive concept On the substrate of the semiconductor devices of mode.Logic unit C1, C2, C3 and C4's (can not show each including multiple transistors Go out).For example, logic unit C1, C2, C3 and C4 can include：First logic unit C1；Second logic unit C2, it is first It is spaced apart on the D1 of direction with the first logic unit C1；3rd logic unit C3, it is intersecting (such as perpendicular to) first direction D1 Second direction D2 on be spaced apart with the first logic unit C1；And the 4th logic unit C4, it is in a second direction d 2 with Two logic unit C2 are spaced apart.4th logic unit C4 can be spaced apart with the 3rd logic unit C3 in the first direction dl.It is single First border CB can be limited between the adjacent logic unit in logic unit C1, C2, C3 and C4.
Logic unit C1, C2, C3 and C4's can each include what is be separated respectively by device isolation layer ST PMOSFET active region PR and NMOSFET active regions NR.For example, logic unit C1, C2, C3 and C4 each PMOSFET Active region PR and NMOSFET active region NR can be spaced apart from each other in a second direction d 2 respectively.In a second direction d 2 The active region that logic unit C1, C2, C3 and C4 adjacent to each other is arranged to its identical conduction type is facing with each other. For example, the first logic unit C1 is arranged to its PMOSFET active regions PR and the 3rd logic unit C3 PMOSFET Active region PR is adjacent.In this manual, any logic unit, which can be referred to herein as, is used to perform boolean logic function (for example, INVERTER (non-) and (AND) or (OR), NAND (with non-) etc.) or store function (such as trigger (FLIP- FLOP unit)).Although only showing four logic units, but it would be recognized that any number of logic unit can be provided.
In some embodiments, logic unit C1, C2, C3 and C4 each transistor included can be based on FinFET structure configures.For example, logic unit C1, C2, C3 and C4 it is each in PMOSFET active regions PR and NMOSFET active regions NR can include the active patterns with the fin-shaped shape protruded from substrate.Form the grid electricity of transistor Extremely can be across at least one active patterns.
Fig. 2A is active in the semiconductor devices according to some exemplary embodiments of present inventive concept for illustrating The figure of the configuration of pattern, more specifically, being to show the boundary member between Fig. 1 the first logic unit and the second logic unit The top view of one example.
A referring to Figures 1 and 2, can provide multiple active patterns AP, and the plurality of active patterns AP has D1 in the first direction The length of measurement and along a first direction D1 and second direction D2 are set.Active patterns AP can have in third direction D3 (examples As it is perpendicular to first direction D1 and second direction D2) on the fin-shaped shape that is protruded from the top surface of substrate.First logic unit C1 Active patterns AP may be constructed the first logic unit C1 PMOSFET active region PR or NMOSFET active regions NR, second PMOSFET the active regions PR or NMOSFET that logic unit C2 active patterns AP may be constructed the second logic unit C2 are active Region NR.First logic unit C1 active patterns AP can have the active patterns AP identicals with the second logic unit C2 to lead Electrically.
Device isolation layer ST can make active patterns AP be separated.It is, device isolation layer ST can be provided in Between adjacent active patterns in the pattern AP of source.In some embodiments, device isolation layer ST can be included in first party Extend on to D1 and limit first the separated region IR1n and IR1w of active patterns AP first (such as relatively long) side wall, and Extend in a second direction d 2 and limit active patterns AP second (such as relatively short) side wall the second separated region IR2s and IR2d.In one embodiment, the first separated region IR1n and IR1w and the second separated region IR2s and IR2d can be A part for single integral insulating barrier.In another embodiment, the first separated region IR1n and IR1w and second separates The part of one or more insulating barriers that can be formed separately in region IR2s and IR2d.
First separated region IR1n and IR1w can be set along second direction D2, and active patterns AP width can be with Corresponding between the first separated region IR1n and IR1w along second direction D2 interval.For example, the first separated region IR1n and IR1w can be comparably spaced apart each other along second direction D2, therefore active patterns AP can have substantially the same width Degree.
In one embodiment, the first separated region IR1n and IR1w can include being arranged on outermost along second direction D2 Wide a pair of the first separated region IR1w on side and this is arranged on to narrow first between the first wide separated region IR1w Separated region IR1n.The width of the first wide separated region IR1w can be more than the width of the first narrow separated region IR1n.Example Such as, the first wide separated region IR1w may be used to PMOSFET active region PR and NMOSFET active regions NR and be separated To limit the region for transistor, for making adjacent logic unit be separated in a second direction d 2, but should Recognize, the first wide separated region IR1w can be used for other purposes.
The first narrow separated region IR1n can have at least substantially identical width.Active patterns AP can be along Two direction D2 are spaced apart from each other with identical interval, make one in the first narrow separated region IR1n be plugged on it is paired adjacent Between active patterns AP.Single more fin transistors can be by active across being comparably spaced apart each other along second direction D2 Pattern AP single gate pattern is realized.Although only four active patterns AP are shown as being configured to by single gate figure Single more fin transistors that case is realized, but it would be recognized that it is single to form to provide any amount of active patterns AP More fin transistors.In other words, although only three the first narrow separated region IR1n are shown as the first separation at wide a pair Between the IR1w of region, but it would be recognized that any amount of the first narrow separated region IR1n can wide a pair first Between separated region IR1w.
Second separated region IR2s and IR2d can be defined as intersecting the first separated region IR1n and IR1w.Second separates Region IR2s and IR2d can therefore with the first separated region IR1n and IR2w partly coextensives.Second separated region IR2s and IR2d can be set with D1 along a first direction, and active patterns AP length can correspond to the second separated region IR2s and D1 interval along a first direction between IR2d.For example, active patterns AP can in the longitudinal direction have respectively with second point Opposite end adjacent septal area domain IR2s and IR2d, D1 is spaced the second separated region IR2s and IR2d along a first direction Open.As illustrated, active patterns AP can have various length.
In one embodiment, the second separated region IR2s and IR2d can include：Single diffusion interruptive area IR2s, its quilt There is provided logic unit C1 and C2 it is each in the paired active patterns AP that are spaced apart from each other of D1 along a first direction between； And double diffusion interruptive area IR2d, its be provided at the paired logic unit adjacent to each other of D1 along a first direction (such as First logic unit C1 and the second logic unit C2) between.
Single diffusion interruptive area IR2s can have the first width W1 of D1 measurements along a first direction.First width W1 can To be limited by the interval between a pair of active patterns AP, to active patterns AP, D1 is adjacent to each other and with slotting along a first direction for this Put single diffusion interruptive area IR2s therebetween.In some embodiments, active patterns AP spreads interruptive area at it with single There can be substantially the same flat shape at respective end adjacent IR2s.Active patterns AP with common single diffusion The end that disconnected region IR2s phase homonymy is adjacent can be aligned with each other along second direction D2.Therefore, across common list diffusion Active patterns APs of the interruptive area IR2s along a first direction in the paired active patterns AP of D1 adjacent to each other can be spaced Open identical interval.It is, single diffusion interruptive area IR2s the first width W1 can be uniform along second direction D2 (or at least substantially uniform).
Double diffusion interruptive area IR2d can have the second width W2 of D1 measurements along a first direction.Second width W2 can With it is adjacent to each other by D1 along a first direction and with the active patterns AP for planting double diffusion interruptive area IR2d therebetween it Between interval limit.In this manual, the second width W2 can correspond to be provided in adjacent to each other in the first direction dl The minimum widith of double diffusion interruptive area IR2d between paired logic unit.Double diffusion interruptive area with the second width W2 IR2d can also be referred to herein as narrow double diffusion interruptive area IR2dn.
In some embodiments, active patterns AP is in its respective end adjacent with narrow double diffusion interruptive area IR2dn There can be substantially the same flat shape at portion.In one embodiment, active patterns AP with narrow double diffusion End adjacent disconnected region IR2dn can or phase identical with the active patterns AP end adjacent with single diffusion interruptive area IR2s Seemingly.
When in a top view be observed when, the first logic unit C1 active patterns AP with narrow double diffusion interruptive area End ed adjacent IR2dn can be aligned with each other along second direction D2.Similarly, when being observed in a top view, second The logic unit C2 active patterns AP end ed adjacent with narrow double diffusion interruptive area IR2dn can be in second direction D2 It is upper aligned with each other.Identical interval can be in being provided in double diffusion interruptive area adjacent to each other and narrow in the first direction dl IR2dn is planted between active patterns AP therebetween.It is, narrow double diffusion interruptive area IR2dn the second width W2 can It is uniform (or at least substantially uniform) with D2 in a second direction.Narrow double diffusion interruptive area IR2dn the second width W2 can be more than single diffusion interruptive area IR2s the first width W1.
In one embodiment, active patterns AP can be by forming the technique of groove and shape including patterned substrate Into wherein groove limits active patterns AP.Single Patternized technique can be performed such that groove is formed simultaneously.It can provide Insulating barrier to fill the bottom of groove, so as to formed the first separated region IR1n and IR1w and the second separated region IR2s and IR2d.Therefore, in one embodiment, active patterns AP and device isolation layer ST can be by single trench process and single Fill process is formed.The detailed description of the formation about active patterns AP will then be discussed.
Fig. 2 B are the top views of a part for the semiconductor devices for the active patterns for exemplarily showing to include Fig. 2A.
Reference picture 2B, gate pattern GP can be provided as across active patterns AP.For example, gate pattern GP can have edge The linear or bar shaped that second direction D2 extends and D1 is provided at regular intervals along a first direction.Although not shown, but It is that each gate pattern GP can include gate electrode and gate-dielectric pattern.
One or more in gate pattern GP can overlap the second separated region IR2s or IR2d.Overlapping second separates Region IR2s and IR2d gate pattern GP can be referred to herein as dummy gate electrode pattern GP_DM.As unshowned, single diffusion Interruptive area IR2s can be overlapped by single dummy gate electrode pattern GP_DM.Double diffusion interruptive area IR2d can be by least two Or more a dummy gate electrode pattern GP_DM overlap.Narrow double diffusion interruptive area IR2dn can overlap two dummy gate electrode patterns GP_DM.An active patterns AP that can jointly overlap the first logic unit C1 in the two dummy gate electrode patterns GP_DM The end adjacent with narrow double diffusion interruptive area IR2dn, and another in the two dummy gate electrode patterns GP_DM can Jointly to overlap the second logic unit C2 active patterns AP end adjacent with narrow double diffusion interruptive area IR2dn. In some embodiments, narrow double diffusion interruptive area IR2dn the second width W2 can be with gate pattern GP pitch (example As D1 along a first direction is measured) substantially the same or pitch less than gate pattern GP is (i.e. so that narrow double diffusion interruption Region IR2dn is still overlapped by two dummy gate electrode pattern GP_DM).
Fig. 3 A are active in the semiconductor devices according to some exemplary embodiments of present inventive concept for illustrating The figure of the configuration of pattern, more specifically, being to show the boundary member between Fig. 1 the first logic unit and the second logic unit The top view of one example.Fig. 3 B are the vertical views for exemplarily showing to include a part for the semiconductor devices of Fig. 3 A active patterns Figure.For simplicity, repetitive description will be omitted.
Reference picture 1 and Fig. 3 A, double diffusion interruptive area IR2d can have the 3rd width of D1 measurements along a first direction W3, it is adjacent to each other by D1 along a first direction and with the active patterns AP for plugging double diffusion interruptive area IR2d therebetween Between interval limit.3rd width W3 can be more than narrow double diffusion interruptive area IR2dn the second width W2 (for example, such as What reference picture 2A and Fig. 2 B were discussed).In other words, double diffusion interruptive area IR2d can have the width more than the second width W2 Degree, and the second width W2 is considered double diffusion interruptive area IR2d minimum widith.It is double with the 3rd width W3 Diffusion interruptive area IR2d can also be referred to herein as wide double diffusion interruptive area IR2dw.
In some embodiments, wide double diffusion interruptive area IR2dw the 3rd width W3 can be according to it along Two direction D2 position and change.The active patterns AP end adjacent with wide double diffusion interruptive area IR2dw can have Different shapes, its basis change along second direction D2 relevant position.This discusses reference picture 3B in further detail.
Reference picture 3B, the active patterns AP adjacent with wide double diffusion interruptive area IR2dw can be included along second party It is located at the outmost active patterns AP_O in outermost and the inside between outmost active patterns AP_O to D2 Active patterns AP_I.Outmost active patterns AP_O can have adjacent with wide double diffusion interruptive area IR2dw side First end ed1, internal active patterns AP_I can have adjacent with the wide double diffusion interruptive area IR2dw side the Two end ed2.First end ed1 and the second end ed2 can be offset from one another with D1 along a first direction.For example, the first logic list First C1 can have internal active patterns AP_I and outmost active patterns AP_O, they respectively have with wide double diffusion Disconnected region IR2dw phase homonymy adjacent the second end ed2 and first end ed1, and the second end ed2 can compare first end Portion ed1 deeper protrudes towards elementary boundary CB.Similarly, the second logic unit C2 can have internal active patterns AP_I and Outmost active patterns AP_O, they have adjacent with wide double diffusion interruptive area IR2dw phase homonymy second respectively End ed2 and first end ed1, and the second end ed2 can deeper dash forward than first end ed1 towards elementary boundary CB Go out.Therefore, it is adjacent to each other and by wide double diffusion interruptive area to can be provided in D1 along a first direction for relatively large interval Between the paired outmost active patterns AP_O that IR2dw is spaced apart from each other, and relatively small interval can be provided in The adjacent to each other and active figure in paired inside that is spaced apart from each other by wide double diffusion interruptive area IR2dw on first direction D1 Between case AP_I.In other words, the wide double diffusion interruptive area IR2dw part adjacent with outmost active patterns AP_O The 3rd width W3 can be more than wide double diffusion interruptive area IR2dw the part adjacent with internal active patterns AP_I the Three width W3.
Outmost active patterns AP_O can at the respective end ed1 adjacent with wide double diffusion interruptive area IR2dw So that with first shape, internal active patterns AP_I is at the respective end ed2 adjacent with wide double diffusion interruptive area IR2dw There can be the second shape.Outmost active patterns AP_O first shape can be differently configured from the of internal active patterns AP_I Two shapes.For example, outmost active patterns AP_O end ed1 can have the shape of sphering, and internal active patterns AP_ I end can have the flat shape for example with angled turning.
In some embodiments, wide double diffusion interruptive area IR2dw can be by least three or more illusory grid Pole figure case GP_DM is overlapped.For example, as shown in Figure 3 B, wide double diffusion interruptive area IR2dw can overlap three dummy gate electrode figures Case GP_DM.One in overlapping wide double diffusion interruptive area IR2dw three dummy gate electrode pattern GP_DM can be jointly Overlapping first logic unit C1 active patterns AP the end ed1 and ed2 adjacent with wide double diffusion interruptive area IR2dw, Another in overlapping wide double diffusion interruptive area IR2dw three dummy gate electrode pattern GP_DM can jointly overlap the Two logic unit C2 active patterns AP the end ed1 and ed2 adjacent with wide double diffusion interruptive area IR2dw.Three void If another in gate pattern GP_DM can be arranged on wide double diffusion interruptive area IR2dw (for example, so as in At elementary boundary CB crossover position).Wide double diffusion interruptive area IR2dw the 3rd width W3 can be with gate pattern GP's Twice of pitch be substantially the same or twice of pitch less than gate pattern GP (i.e. so that wide double diffusion interruptive area IR2dw is still overlapped by three dummy gate electrode pattern GP_DM).Depending on overlapping the illusory of wide double diffusion interruptive area IR2dw Gate pattern GP_DM quantity, wide double diffusion interruptive area IR2dw the 3rd width W3 can increase.
It is as discussed above, the shape of the active patterns AP end adjacent with wide double diffusion interruptive area IR2dw and Configuration can be differently configured from shape and the configuration of the active patterns AP end adjacent with narrow double diffusion interruptive area IR2dn.This Difference can be due to the difference of its manufacture method, and this will be discussed in further detail later.
Fig. 4 is to show that the double diffusion in the semiconductor devices according to some exemplary embodiments of present inventive concept is interrupted The top view of one example of the arrangement in region.
As needed, what various sizes and width can be between logic units adjacent to each other in the first direction dl is double Realized on diffusion interruptive area IR2d.For example, narrow double diffusion interruptive area IR2dn may be provided in along a first direction There is the second width W2, and wide double diffusion interruptive area IR2dw can be by between a pair of logic units adjacent to each other D1 It is provided as wide be more than the second width W2 the 3rd between another pair logic units adjacent to each other of D1 along a first direction Spend W3.Reference picture 4 is hereinafter discussed in more detail to double diffusion interruptive area IR2d arrangement.
Reference picture 4, it can include carrying respectively according to the semiconductor devices of some exemplary embodiments of present inventive concept For the first logic unit C1 on substrate, the second logic unit C2 and the 5th logic unit C5.First logic unit C1, second Logic unit C2 and the 5th logic unit C5 can be set with D1 along a first direction.For example, the first logic unit C1 and the 5th is patrolled Collecting unit C5 can be spaced apart from each other with D1 along a first direction, and the second logic unit C2 is planted therebetween.First logic list First C1 and the second logic unit C2 can share first module border CB1, and the second logic unit C2 and the 5th logic unit C5 can To share second unit border CB2.
In one embodiment and as shown in exemplary, narrow double diffusion interruptive area IR2dn can be provided in Between first logic unit C1 and the second logic unit C2, and wide double diffusion interruptive area IR2dw can be provided in second Between logic unit C2 and the 5th logic unit C5.However, in other embodiment, narrow double diffusion interruptive area IR2dn can be provided between the first logic unit C1 and the second logic unit C2 and be patrolled in the second logic unit C2 and the 5th Between collecting unit C5, or wide double diffusion interruptive area IR2dw can be provided in the first logic unit C1 and the second logic list Between first C2 and between the second logic unit C2 and the 5th logic unit C5.In another embodiment, wide double diffusion Interruptive area IR2dw be can be provided between the first logic unit C1 and the second logic unit C2, and narrow double diffusion is interrupted Region IR2dn can be provided between the second logic unit C2 and the 5th logic unit C5.
Fig. 5 A to Figure 15 A be show according to some exemplary embodiments of present inventive concept be used to manufacture include it is active The top view of the method for the semiconductor devices of pattern.Fig. 5 B to Figure 15 B are the line I-I' and II- respectively along Fig. 5 A to Figure 15 A The sectional view of II' interceptions.Fig. 5 C to Figure 15 C are cutd open respectively along what Fig. 5 A to Figure 15 A line III-III' and IV-IV' was intercepted View.
Reference picture 5A, Fig. 5 B and Fig. 5 C, substrate 100 may be provided in includes the first logic cells area CR1, the respectively Two logic cells area CR2, the 3rd logic cells area CR3 and the 4th logic cells area CR4.For example, the first logic unit Region CR1 and the second logic cells area CR2 can be wherein a pair of logic unit quilts adjacent to each other in the first direction dl The region of formation, the 3rd logic cells area CR3 and the 4th logic cells area CR4 can be wherein in the first direction dl that The region that this adjacent another pair logic unit is formed.First logic cells area CR1 and the second logic cells area CR2 can The second list can be shared to share first module border CB1, the 3rd logic cells area CR3 and the 4th logic cells area CR4 First border CB2.Or first logic cells area CR1 can be wherein Fig. 4 the regions that are formed of the first logic unit C1, The second logic unit C2 that second logic cells area CR2 and the 3rd logic cells area CR3 can be wherein Fig. 4 is formed Region, the 4th logic cells area CR4 can be the regions that wherein Fig. 4 the 5th logic unit C5 is formed.In such case Under, Fig. 5 A first module border CB1 can correspond to Fig. 4 first module border CB1, Fig. 5 A second unit border CB2 It can correspond to Fig. 4 second unit border CB2.Substrate 100 can be Semiconductor substrate or compound semiconductor substrate (such as Including silicon, germanium, silicon-germanium etc. or its any combinations).
By subsequent technique, the narrow double diffusion interruptive area IR2dn that reference picture 2A and Fig. 2 B are discussed can be formed on the In substrate 100 between one logic cells area CR1 and the second logic cells area CR2, and reference picture 3A and Fig. 3 B are discussed Wide double diffusion interruptive area IR2dw can be formed on the 3rd logic cells area CR3 and the 4th logic cells area CR4 it Between substrate 100 in.Discuss further below based on different logic unit formed first to fourth logic cells area CR1, The embodiment of situation in CR2, CR3 and CR4.
Reference picture 5A, line mask pattern 110a and 110b can form on the substrate 100 and along a first direction that D1 is each other Extend parallel to.For example, line mask pattern 110a and 110b can with D1 along a first direction extend and along second direction D2 that This is spaced apart.Line mask pattern 110a and 110b can be spaced apart from each other along second direction D2 with substantially the same interval. Line mask pattern 110a and 110b can include being formed on the first logic cells area CR1 and the second logic cells area CR2 First Line mask pattern 110a and formed on the 3rd logic cells area CR3 and the 4th logic cells area CR4 the Two wires mask pattern 110b.First Line mask pattern 110a can be with D1 along a first direction across the first logic cells area CR1 Can be with D1 along a first direction across the 3rd logic unit area with the second logic cells area CR2, the second line mask pattern 110b Domain CR3 and the 4th logic cells area CR4.
In one embodiment and reference picture 5B and Fig. 5 C, First Line mask pattern 110a and the second line mask pattern 110b's can each be included with different etching selectivity from each other and the offline mask pattern of order stacking on the substrate 100 112 and reach the standard grade mask pattern 114.Offline mask pattern 112 can be by having the material shape of etching selectivity relative to substrate 100 Into.For example, offline mask pattern 112 can include at least one of Si oxide, silicon nitride and silicon nitrogen oxides.Reach the standard grade Mask pattern 114 can be by having the material (such as polysilicon) of etching selectivity to be formed relative to offline mask pattern 112. In present embodiment, each of line mask pattern 110a and 110b is shown as with double stacked structure, but structure of the present invention Think not limited to this.In some embodiments, line mask pattern 110a and 110b each can include single layer structure, three layers of heap Stack structure etc..Line mask pattern 110a and 110b can be formed using such as double patterning technology or quadruple patterning techniques.
Reference picture 6A, Fig. 6 B and Fig. 6 C, lower separating mask pattern 122,124 and 126 can be formed on the substrate 100. In one embodiment, lower separating mask pattern 122,124 and 126 can be covered by being formed in the whole surface of substrate 100 Line mask pattern 110a and 110b lower separating mask layer and then patterning descend separating mask layer and formed.Lower separating mask layer Separating mask pattern 122,124 and under being limited for example, by forming photoresist pattern on lower separating mask layer 126 and then etch lower separating mask layer using photoresist pattern as etching mask and pattern.Lower separating mask layer can To be formed by such as SOH (spin-coating hardmask) layer, but it would be recognized that lower separating mask layer can be by any other suitable Material is formed.
In some embodiments, lower separating mask pattern 122,124 and 126 can include：Along a first direction D1 across Cross the first logic cells area CR1 and the second logic cells area CR2 first time separating mask pattern 122；Formed the 3rd Second time separating mask pattern 124 on logic cells area CR3；And the three times separating mask patterns 126, it is formed on On 4th logic cells area CR4 and along a first direction D1 and be spaced apart with second time separating mask pattern 124.Second lower point The 3rd logic cells area CR3 and the 4th can be respectively formed at every mask pattern 124 and the three times separating mask patterns 126 to patrol Collect on the CR4 of unit area, while be spaced apart from each other and second unit border CB2 is planted therebetween.However, first time separation is covered Mould pattern 122 can be formed as single integral main body and (e.g., including be formed and patrolled in the first logic cells area CR1 and second The lower separating mask pattern on the CR2 of unit area is collected, they are combined integrally with each other).
First time separating mask pattern 122 can cover along second direction D2 and be arranged in the first logic cells area CR1 With on the second logic cells area CR2 multiple First Line mask pattern 110a (for example, four First Line mask pattern 110a, As shown in Fig. 6 A exemplarily).Second time separating mask pattern 124, which can be covered along second direction D2, is arranged in the 3rd Multiple second line mask pattern 110b on logic cells area CR3 are (for example, four the second line mask pattern 110b, such as Fig. 6 A In exemplarily show) part.The three times separating mask patterns 126, which can be covered along second direction D2, is arranged in the 4th Multiple second line mask pattern 110b on logic cells area CR4 are (for example, four the second line mask pattern 110b, such as Fig. 6 A In exemplarily show) part.Therefore, multiple second line mask pattern 110b different piece can be by second time separation Mask pattern 124 and the three times separating mask patterns 126 cover.Second time separating mask pattern 124 and the three times separating masks Pattern 126 can be spaced apart from each other (example with may correspond to wide double diffusion interruptive area IR2dw the 3rd width W3 interval Such as, illustrate as described above with Fig. 3 A and Fig. 3 B).In some embodiments, under second time separating mask pattern 124 and the 3rd Separating mask pattern 126 can have end facing with each other second unit border CB2 is planted therebetween, and second time separation is covered The end of mould pattern 124 and the three times separating mask patterns 126 can have the turning 124c and 126c of sphering respectively.When photic When Resist patterns is formed to define second time separating mask pattern 124 and the three times separating mask patterns 126, sphering turns Angle 124c and 126c is formed due to the characteristic of photoresist technique.
First time separating mask pattern 122 can be exposed positioned at first time separating mask pattern 122 along second direction First Line mask pattern 110a (referred to herein as illusory First Line mask pattern 110a_ on D2 reciprocal side DM).Similarly, second time separating mask pattern 124 and the three times separating mask patterns 126 can be exposed positioned at second time separation The second line on the reciprocal side along second direction D2 of mask pattern 124 and the three times separating mask patterns 126 is covered Mould pattern 110b (referred to herein as illusory second line mask pattern 110b_DM) and the second line mask pattern 110b the Part between two times separating mask patterns 124 and the three times separating mask patterns 126.
Reference picture 7A, Fig. 7 B and Fig. 7 C, the first etch process can be performed with using lower separating mask pattern 122,124 and 126 are used as etching mask to remove illusory First Line mask pattern 110a_DM and illusory second line mask pattern 110b_DM completely. First etch process can also remove second between second time separating mask pattern 124 and the three times separating mask patterns 126 Line mask pattern 110b expose portion, so as to form initial second hard mask pattern 110bp.Therefore, the first etch process can So that each second line mask pattern 110b is divided into initial second hard mask pattern 110bp, initial second hard mask pattern 110bp is spaced apart from each other (for example, so that D1 is adjacent to each other along a first direction) and second unit border CB2 is plugged on it Between.First etch process can be for example including anisotropic dry etch technique.First etch process can also partly remove lining The top at bottom 100.
In some embodiments, interval can be provided between adjacent initial second hard mask pattern 110bp, and The interval can change along second direction D2.For example, interval d1 can be provided in it is initial second hard positioned at outermost a pair Between mask pattern 110bp, less than interval d1 interval d2 can be provided in the initial second hard mask pattern 110bp of another pair it Between.Initial second hard mask pattern 110bp can have the respective end adjacent with second unit border CB2, and initial second is hard Mask pattern 110bp end can have the end with second time separating mask pattern 124 and the three times separating mask patterns 126 The shape that the shape in portion is consistent.For example, initial second hard mask pattern 110bp can have and second time separating mask pattern 124 and the three times separating mask patterns 126 the adjacent sphering of turning 124c and 126c end.
Reference picture 8A, Fig. 8 B and Fig. 8 C, upper separating mask layer 130 can be formed in the whole surface of substrate 100.Upper point First time separating mask pattern 122, second time separating mask pattern 124 and three times separations can be covered every mask layer 130 to cover Mould pattern 126, and also fill up the space between them.Upper separating mask layer 130 can be by the material with lower separating mask layer Identical material (such as SOH layers) formation.
Reference picture 9A, Fig. 9 B and Fig. 9 C, upper separating mask layer 130 can be patterned to form separating mask pattern 132.Upper separating mask pattern 132 can include multiple openings of the lower separating mask pattern 122,124 and 126 of exposure.It is real one Apply in mode, upper separating mask layer 130 can form exposure wherein by formation opening by being included on upper separating mask layer 130 The photoresist pattern in OP1 and OP2 region and then separate and cover in etching using photoresist pattern as etching mask The technique of mold layer 130 and be patterned.
In some embodiments, opening can patrol including jointly exposing first time separating mask pattern 122 first Collect first to fourth logic of the first opening OP1 and exposure of unit area CR1 and the part on the second logic cells area CR2 First to the three times separating mask patterns 122,124 and 126 on respective logic unit in unit CR1, CR2, CR3 and CR4 It is multiple second opening OP2.First opening OP1 can be located on the CB1 of first module border, and the second opening OP2 can be positioned as It is spaced apart with first module border CB1 and second unit border CB2.
First opening OP1 can have the rectangular shape along second direction D2 across first time separating mask pattern 122. For example, the first opening OP1 can overlap four in the First Line mask pattern 110a set along second direction D2.Planar shaped Shape can be formed on the overlapping region between the first opening OP1 and each First Line mask pattern 110a.When in a top view When observed, due to the characteristic of photoetching process, the first opening OP1 can have the turning of sphering.In some embodiments, The sphering that one opening OP1 length (for example, along second direction D2 measurement) can be adjusted to ensure the first opening OP1 turns The not overlapping First Line mask pattern 110a in angle.As a result, the first opening OP1 overlaps each First Line mask pattern 110a region Border can extend to straight line.First opening OP1 can have that its size and narrow double diffusion interruptive area IR2dn's is second wide Spend width corresponding to W2 size.
Although the second opening OP2 each two or initial second be shown as in overlapping First Line mask pattern 110a Two in hard mask pattern 110bp, but it would be recognized that any second opening OP2 can overlap any amount of the One second hard mask patterns of line mask pattern 110a or initial 110bp.Second opening OP2 can have various length.For example, the Two opening OP2's can each have the rectangular shape with rounded corners, and with the major axis extended along second direction D2. The wherein First Line mask that flat shape can be formed in the first logic cells area CR1 and the second logic cells area CR2 Pattern 110a is by place overlapping the second opening OP2.Similarly, flat shape can be formed in the 3rd logic cells area CR3 With the wherein initial second hard mask pattern 110bp in the 4th logic cells area CR4 by place overlapping the second opening OP2. Second opening OP2's can each have the width smaller than the first opening OP1 width.For example, the second opening OP2 can have Its size width (example corresponding with reference picture 2A and Fig. 2 the B single diffusion interruptive area IR2s discussed the first width W1 size Such as, along a first direction D1 measurement).Or second opening OP2 in one or all can not provide in logic unit area On domain CR1, CR2, CR3 and CR4.
Reference picture 10A, Figure 10 B and Figure 10 C, the second etch process can be performed so as to be made with separating mask pattern 132 The part exposed by opening OP1 and OP2 of lower separating mask pattern 122,124 and 126 is removed for etching mask.Second etching Technique can be such as anisotropic dry etch technique.Second etch process can be performed until substrate 100 is by opening OP1 It is exposed with the top surface of the OP2 parts overlapped.Second etch process can also be removed by the first opening OP1 and the second opening OP2 overlapping First Line mask pattern 110a and initial second hard mask pattern 110bp.
First time separating mask pattern 122 can be divided into D1 along a first direction and be spaced apart from each other by the second etch process The first sub- sub- separating mask pattern 122b of separating mask pattern 122a and second.In addition, First Line mask pattern 110a's is every It is individual to be separated with D1 along a first direction so that the first hard mask pattern 110h1 is formed in the first logic cells area CR1 and the On two logic cells area CR2.As illustrated, the first hard mask pattern 110h1 can have various length.In addition, initial One or more in two hard mask pattern 110bp can be separated with D1 along a first direction so that the second hard mask pattern 110h2 is formed as having various length on the 3rd logic cells area CR3 and the 4th logic cells area CR4.
In some embodiments, when being observed in a top view, the first logic cells area CR1 the first hard mask Pattern 110h1 can have with first module border CB1 adjacent and along respective end aligned with each other second direction D2.Equally Ground, when being observed in a top view, the second logic cells area CR2 the first hard mask pattern 110h1 can have and the One elementary boundary CB1 is adjacent and along respective end aligned with each other second direction D2.Therefore, identical interval can be provided in D1 is adjacent to each other and with the first hard mask pattern 110h1 for planting first module border CB1 therebetween along a first direction Between.When being observed in a top view, the 3rd logic cells area CR3 the second hard mask pattern 110h2 can have with Respective end adjacent second unit border CB2, and one or more in the end can be with D1 along a first direction Skew.In other words, the 3rd logic cells area CR3 can include being located at outermost and having being relatively distant from second unit border Second hard mask pattern 110h2 of CB2 end, and can also include setting and having relatively close along second direction D2 The second adjacent hard mask pattern 110h2 of second unit border CB2 end.Similarly, when being observed in a top view, 4th logic cells area CR4 the second hard mask pattern 110h2 can have the respective end adjacent with second unit border CB2 Portion, and one or more in the end can be offset with D1 along a first direction.In other words, the 4th logic unit area Domain CR4 can be included positioned at outermost and with the second hard mask pattern of the end for being relatively distant from second unit border CB2 110h2, and can also include setting along second direction D2 and there is the phase of relatively close second unit border CB2 end The second adjacent hard mask pattern 110h2.Therefore, it is adjacent to each other and with being plugged on to can be provided in D1 along a first direction for interval Between the second hard mask pattern 110h2 of second unit border CB2 therebetween, and such interval can according to they along Second direction D2 position and change.
After the second etch process, upper separating mask pattern 132 can be retained in separating mask pattern 122a, 122b, In space between 124 and 126.Opening OP1 and OP2 each depth can extend (for example, along third direction D3) simultaneously It is the basal surface for including the top surface corresponding to substrate 100 to be re-defined.
Reference picture 11A, Figure 11 B and Figure 11 C, separating mask pattern 122a, 122b, 124 and 126 can be removed.For example, can Separating mask pattern 122a, 122b, 124 and 126 is removed to perform cineration technics.
By using the first hard mask pattern 110h1 and the second hard mask pattern 110h2 the 3rd is performed as etching mask Etch process, groove T1, T2, T3 and T4 can be formed to limit active patterns AP.3rd etch process can be for example respectively to Different in nature dry etching process.Groove T1, T2, T3 and T4 can include the first groove for limiting active patterns AP relatively long side wall The 3rd groove T3 and the 4th groove T4 of T1 and second groove T2 and restriction active patterns AP relatively short side wall.
As best seen from, when being measured along second direction D2, first groove T1 can be with Figure 11 B and Figure 11 C With the width substantially the same with second groove T2 width or the width smaller than second groove T2 width.Second groove T2 There can be various width along second direction D2.When D1 along a first direction is measured, the 3rd groove T3 can have with The 4th groove T4 roughly the same width of width or the width smaller than the 4th groove T4 width.4th groove T4 can have D1 various width along a first direction.For example, between the first logic cells area CR1 and the second logic cells area CR2 4th groove T4 can have than the 4th groove T4 between the 3rd logic cells area CR3 and the 4th logic cells area CR4 The small width of width.In some embodiments, groove T1, T2, T3 and T4 can each be formed as having with from lining The width that the top surface at bottom 100 plays the downward distance gradually increased and reduced.Active patterns AP's can each be formed as having The shape that its width reduces with the distance that the top surface towards substrate 100 is gradually reduced.Groove T1, T2 discussed above, Each Breadth Maximum for being considered groove T1, T2, T3 and T4 of T3 and T4 width.
Groove T1, T2, T3 and T4 bottom can be filled with to form device isolation layer, and active patterns AP top passes through Device isolation layer exposes.Device isolation layer can be including the first narrow separated region IR1n in first groove T1, second groove In single diffusion interruptive area IR2s and the 4th groove T4 in wide the first separated region IR1w, the 3rd groove T3 in T2 Double diffusion interruptive area IR2dn and IR2dw.The description that reference picture 2A, Fig. 2 B, Fig. 3 A and Fig. 3 B are discussed can with same or like It is applicable to separated region IR1n and IR1w (i.e. the first separated region) and diffusion interruptive area IR2s, IR2dn and IR2dw (i.e. Second separated region) width, and be equally applicable to the shape and arrangement of active patterns AP adjacent thereto end, therefore Repetitive description will be omitted for simplicity.
In one embodiment, device isolation layer can by including form insulating barrier with fill groove T1, T2, T3 and T4 and then planarization and etching isolation layer is to expose the technique on active patterns AP top to be formed.Active patterns AP exposure Top can also be defined as active fin AF below.Device isolation layer can include such as silicon oxide layer, silicon nitride It is at least one in layer, silicon oxynitride layer, low-k dielectric layer etc..
As discussed above, according to the exemplary embodiment of present inventive concept, active patterns can be by including pattern Change line mask pattern and limit the plan-position of active patterns and the hard mask pattern of shape and using hard mask pattern to be formed Top as etching mask etching substrate is formed with forming the technique for the groove for limiting active patterns.The figure of line mask pattern Caseization can include being used to remove the Patternized technique of line mask pattern (below from by the region for forming double diffusion interruptive area Referred to as the first Patternized technique) and for another pattern from the region removal line mask pattern that will form list diffusion interruptive area Chemical industry skill (hereinafter referred to as the second Patternized technique).
Second Patternized technique can be performed using upper separating mask pattern, and separating mask pattern has overlapping incite somebody to action on this The opening of the line mask pattern formed on the region of single diffusion interruptive area.In this case, the length of opening can be adjusted Section overlaps the flat shape of line mask pattern to be formed to be open.As a result, active patterns can be formed as having and be interrupted with single diffusion Region is adjacent and along the width of active patterns end aligned with each other.
The lower separating mask pattern that first Patternized technique can use adjacent to each other and elementary boundary to plant therebetween is made Performed for etching mask.In this case, lower separating mask pattern can be formed as with facing with each other and with sphering The respective end at turning (such as characteristic of the photoetching process due to being related to).As a result, it is adjacent with double diffusion interruptive area active Pattern can be formed as with the respective end offset with double diffusion interruptive area adjacent and along the length direction of active patterns. For these reasons, can be difficult to subsequently form jointly overlap active patterns it is adjacent with the side of double diffusion interruptive area The gate pattern (i.e. dummy gate electrode pattern) of end.Specifically, the feelings with minimum widith are formed as in double diffusion interruptive area Under condition, due to the deficiency of process allowance, above mentioned problem can be more serious.In subsequent technique, regions and source/drain can be formed For with the end adjacent with the side of double diffusion interruptive area depending on the whether overlapping active patterns of dummy gate electrode pattern Shape.Therefore, if dummy gate electrode pattern does not overlap the adjacent with the side of double diffusion interruptive area of active patterns jointly End, then the reliability of semiconductor devices can reduce.
According to the exemplary embodiment of present inventive concept, in the feelings that double diffusion interruptive area is formed as having minimum widith Under condition (i.e. in the case where forming narrow double diffusion interruptive area), the second Patternized technique can be performed such that line mask artwork Case removes from by the region for forming double diffusion interruptive area.In other words, upper separating mask pattern can have overlapping formed Wherein by the opening of the line mask pattern on the region for forming double diffusion interruptive area.Therefore, with narrow double diffusion interruptive area Adjacent active patterns can be formed as the respective end being aligned with the width along active patterns.Then can be easily Form the dummy gate electrode pattern for the end adjacent with the side of double diffusion interruptive area for jointly overlapping active patterns.As a result, Semiconductor devices can have the reliability by being improved caused by the improved distribution of its electrical characteristics.
Including for manufacture according to some exemplary embodiments of present inventive concept is provided further below The method of the semiconductor devices of source pattern.
Reference picture 12A, Figure 12 B and Figure 12 C, sacrificing structure 140 can be formed as across active patterns AP.Sacrifice structure 140 can in a second direction d 2 extend and comparably be spaced apart each other in the first direction dl.Sacrificing each of structure 140 can With including sequentially stacking sacrificial pattern 142 and gate mask pattern 144 on the substrate 100.
In some embodiments, sacrifice structure 140 in it is one or more can overlap the second separated region IR2s, IR2dn and IR2dw.For example, single diffusion interruptive area IR2s can be spaced apart by the adjacent end portion with active patterns AP it is single It is overlapping to sacrifice structure 140.Narrow double diffusion interruptive area IR2dn can sacrifice structure 140 by two and overlap.The two sacrifice knot An active patterns AP's that can jointly overlap the first logic cells area CR1 in structure 140 interrupts with narrow double diffusion End adjacent region IR2dn.Another in the two sacrifice structures 140 can jointly overlap the second logic cells area The CR2 active patterns AP end adjacent with the narrow double diffusion interruptive area IR2dn.
Wide double diffusion interruptive area IR2dw can sacrifice structure 140 by three and overlap.These three are sacrificed in structure 140 An active patterns AP that can jointly overlap the 3rd logic cells area CR3 with wide double diffusion interruptive area End adjacent IR2dw.Another in these three sacrifice structures 140 can jointly overlap the 4th logic cells area CR4 Active patterns AP the end adjacent with the wide double diffusion interruptive area IR2dw.These three sacrifice another again in structure 140 One can be arranged on the wide double diffusion interruptive area IR2dw in overlapping second unit border CB2 opening position.
Structure 140 is sacrificed to pass through including forming sacrifice layer (not shown) to cover the whole surface of substrate 100, in sacrifice layer Upper formation gate mask pattern 144 and using gate mask pattern 144 as etching mask patterns sacrifice layer so as to being formed The technique of sacrificial pattern 142 is formed.Sacrifice layer can include such as polysilicon.Gate mask pattern 144 can be included for example Silicon nitride or silicon nitrogen oxides.
Grid spacer SP can be formed in the side wall for sacrificing structure 140.Grid spacer SP can be by conformally Form spacer layer and formed with covering sacrifice structure 140 and performing whole anisotropic etching process on the substrate 100.Interval Nitride layer can use such as SiO2, at least one of SiCN, SiCON, SiN etc. formed.Or spacer layer can be formed as Including such as SiO2, at least one of SiCN, SiCON, SiN etc. sandwich construction.
Reference picture 13A, Figure 13 B and Figure 13 C, sunk area RS1 and RS2, which can be formed, is sacrificing the phase each other of structure 140 On anti-side.In one embodiment, sunk area RS1 and RS2 can be come by using structure 140 is sacrificed as etching mask Perform isotropism and/or anisotropic etching process is formed with etching active fin AF top.For example, sunk area RS1 And RS2 can be included in the first sunk area RS1 with U-shaped section shape between adjacent sacrifice structure 140 and with The second adjacent single diffusion interruptive area IR2s sunk area RS2.During sunk area RS1 and RS2 formation, active fin AF Its end adjacent with single diffusion interruptive area IR2s can be etched to remove.Therefore, the second sunk area RS2 can be formed For without U-shaped section shape.
Reference picture 14A, Figure 14 B and Figure 14 C, regions and source/drain SD1 and SD2 can be formed active patterns AP that On this opposite side.In one embodiment, regions and source/drain SD1 and SD2 can be by performing selective epitaxial growth work Skill is formed, wherein limit sunk area RS1 and RS2 active fin AF and active patterns AP by sunk area RS1 and Any part of RS2 exposures is used as inculating crystal layer.It is, regions and source/drain SD1 and SD2 can include epitaxial layer.Example Such as, regions and source/drain SD1 and SD2 each can include from active fin AF and/or pass through sunk area RS1 and RS2 exposure Active patterns AP epitaxial growths at least one material, SiGe (SiGe), silicon (Si), carborundum (SiC) etc..Therefore, Regions and source/drain SD1 and SD2 can sacrificing the part below structure 140, (such part be also at this to active fin AF In be referred to as channel region) apply compression strain or elongation strain (be also generally referred to as " extension strain " or " misfit strain " here, As known in the art).With epitaxial growth technology simultaneously or after epitaxial growth technology, regions and source/drain SD1 and SD2 can be doped with impurity.For example, regions and source/drain SD1 and SD2 can be doped with p-type or p-type impurities.
Regions and source/drain SD1 and SD2 can include the first source/drain regions inside the first sunk area RS1 Domain SD1 and the second regions and source/drain SD2 inside the second sunk area RS2.In some embodiments, the first source Pole/drain region SD1 can have the uppermost surface higher than active fin AF uppermost surface, the second source/drain Polar region domain SD2 can have the uppermost surface lower than active fin AF uppermost surface.Second regions and source/drain SD2's can each have the inclined surface SD2_S tilted down towards single diffusion interruptive area IR2s adjacent thereto.Example Such as, inclined surface SD2_S can have (111) crystal face.
It is adjacent with narrow double diffusion interruptive area IR2dn in active patterns AP end but not to be sacrificed structure 140 overlapping In the case of, the first sunk area RS1 adjacent with such end (also referred to as the 3rd sunk area) can be formed as With with the second sunk area RS2 identical shapes.Regions and source/drain (hereinafter referred to as the 3rd regions and source/drain) can To be then formed on inside the sunk area of shape identical the 3rd of its shape and regions and source/drain SD2.In present embodiment In, the 3rd regions and source/drain can have the shape with adjacent regions and source/drain (i.e. the first regions and source/drain SD1) The different shape of shape, as a result, the characteristic distribution of semiconductor devices can deteriorate.For example, the electrical characteristics of semiconductor devices can due to from 3rd regions and source/drain be applied to the reduction on channel region strain and/or the regions and source/drain with subsequent work Formed in skill source/drain contact between contact fault and deteriorate.However, these problems can be by ensuring active patterns AP The end adjacent with narrow double diffusion interruptive area IR2dn be sacrificed structure 140 overlapping (example discussed in embodiment as described above The mode stated) and avoid, the unfailing performance of semiconductor devices is enhanced.
First interlevel dielectric layer 150 can be formed as covering and sacrifice structure 140 and regions and source/drain SD1 and SD2. For example, the first interlevel dielectric layer 150 can include silicon oxide layer, and flowable chemical vapor deposition can be passed through (FCVD) technique is formed.
First interlevel dielectric layer 150 can be flattened, until the top surface of sacrificial pattern 142 is exposed.First layer Between the planarization of dielectric layer 150 can be performed using etch back process or CMP process.Pass through flat chemical industry Skill, gate mask pattern 144 can be removed to expose the top surface of sacrificial pattern 142.Flatening process can also remove grid Sept SP top.
Once being exposed, sacrificial pattern 142 can use each grid including gate-dielectric pattern GD and gate electrode GE Pattern GP is replaced.Sacrificial pattern 142 is replaced to include optionally removing sacrificial pattern 142 to be formed cruelly with gate pattern GP Reveal the area of grid of the active patterns AP between grid spacer SP and then gate dielectric layer is sequentially formed in area of grid And grid electrode layer.For example, gate dielectric layer can include in hafnium oxide, hafnium silicate, Zirconium oxide, zirconium silicate etc. At least one or its any combinations.Grid electrode layer can include (such as titanium nitride, the tantalum nitridation of conductive metal nitride Thing, tungsten nitride etc.), metal (such as aluminium, tungsten etc.) etc. or its any combinations.Overlapping second separated region IR2s, IR2dn and IR2dw gate pattern GP can be referred to herein as dummy gate electrode pattern GP_DM.
Or gate electrode GE can be recessed at an upper portion thereof, and lid pattern (not shown) can be further formed at depression Gate electrode GE on.It is, gate pattern GP's can each include gate-dielectric pattern GD, gate electrode GE and lid pattern (not shown).For example, lid pattern (not shown) can include Si oxide, silicon nitride, silicon nitrogen oxides, silicon-carbon nitride (SiCN), at least one of silicon-carbon nitrogen oxides (SiCON) etc. or its any combinations.
Reference picture 15A, Figure 15 B and Figure 15 C, the second interlevel dielectric layer 160 can be formed and be situated between with covering the first interlayer electricity Matter layer 150 and gate pattern GP.Second interlevel dielectric layer 160 can include such as silicon oxide layer, silicon-nitride layer, silicon nitrogen It is at least one in oxide skin(coating), low dielectric layer etc..
Source/drain contact 170a and 170b can be formed through the first interlevel dielectric layer 150 and the second interlayer electricity Dielectric layer 160, and it is connected to regions and source/drain SD1 and SD2.Source/drain contact 170a's and 170b each can be Extend on second direction D2 with across at least two active patterns AP.Source/drain contact 170a and 170b can include common Ground is connected to the first source/drain contact for the multiple first regions and source/drain SD1 being arranged on gate pattern GP side 170a and it is commonly connected to be arranged on of multiple second regions and source/drain SD2 on gate pattern GP opposite side Two source/drains contact 170b.Be commonly connected to single source electrode/drain contact regions and source/drain may be constructed it is single More fin transistors.For the connection with the second regions and source/drain SD2, the second source/drain contact 170b can have it high Spend the low basal surface of the height of the basal surface than the first source/drain contact 170a.Source/drain contact 170a and 170b can be with Polysilicon layer, metal level (such as tungsten, titanium, tantalum etc.) including impurity doping, metal silicide layer (such as Titanium silicide, tantalum silicon Compound, tungsten silicide etc.) etc. at least one or its any combinations.
Although not shown in the drawings, still interconnection line can form on the second interlevel dielectric layer 160 and be electrically connected to source Pole/drain contact 170a and 170b.
According to the exemplary embodiment of present inventive concept, active patterns can be formed as with minimum widith Narrow double diffusion interruptive area is adjacent and width in active patterns on the respective end that is aligned.Dummy gate electrode pattern can be with Jointly overlap the end adjacent with narrow double diffusion interruptive area of active patterns.As a result, can formed in dummy gate electrode Substantially the same shape is realized in regions and source/drain between pattern and its adjacent gate pattern.Therefore, can improve The distribution of electrical characteristics is to improve the reliability of semiconductor devices.
Although the embodiment shown in combined accompanying drawing describes the disclosure, disclosure not limited to this.For Those skilled in the art will be apparent, and can carry out various replacements, modifications and changes to it, without departing from such as claim The scope and spirit of the present invention that secretary carries.
This application claims on May 17th, 2016 korean patent application submitted the 10-2016-0060334th it is preferential Power, entire contents are incorporated herein by reference.

Claims (20)

1. a kind of semiconductor devices, including：
Substrate, it includes the multiple logic units set along a first direction；
Active patterns, it is protruded from the substrate；And
Device isolation layer over the substrate, the device isolation layer include the first double diffusion interruptive area and the second double diffusion Interruptive area, the first double diffusion interruptive area have the first width along first direction measurement and are arranged on a pair Between adjacent logic unit, the second double diffusion interruptive area, which has along first direction measurement, is more than described the Second width of one width is simultaneously arranged between the adjacent logic unit of another pair,
Wherein described active patterns include：
Multipair first active patterns, the first active patterns per centering are spaced apart from each other along the first direction and make described the One double diffusion interruptive area is planted therebetween；And
Multipair second active patterns, the second active patterns per centering are spaced apart from each other along the first direction and make described the Two double diffusion interruptive areas are planted therebetween,
Wherein described first active patterns are included with the side of the first double diffusion interruptive area adjacent and along described in intersecting The first end of the second direction alignment of first direction, and
Wherein described second active patterns include the second end adjacent with the side of the second double diffusion interruptive area, and One in wherein described the second end along the first direction from another skew in the second end.
2. semiconductor devices according to claim 1, wherein second active patterns include being located at outermost outermost The active patterns in face and at least one internal active patterns between the outmost active patterns,
The second end of wherein described at least one internal active patterns from the outmost active patterns described the Two ends laterally protrude along the first direction.
3. semiconductor devices according to claim 2, wherein at least one in the outmost active patterns has The length bigger along the length of at least one internal active patterns described in the ratio of first direction measurement.
4. semiconductor devices according to claim 3,
Wherein described device isolation layer also includes being arranged on single diffusion in a logic unit in the multiple logic unit Interruptive area,
Wherein described at least one internal active patterns include adjacent with single diffusion interruptive area along the first direction The 3rd end, and
Wherein described single diffusion interruptive area along the second direction with it is at least one in the outmost active patterns It is adjacent.
5. semiconductor devices according to claim 1, in addition to the gate pattern extended along the second direction,
Two in wherein described gate pattern overlap the first double diffusion interruptive area, and three in the gate pattern Individual or more overlaps the second double diffusion interruptive area.
6. semiconductor devices according to claim 5, wherein some in the gate pattern are across the active patterns.
7. semiconductor devices according to claim 1, wherein the device isolation layer is also included at least one single diffusion Disconnected region, at least one single diffusion interruptive area have second width that is less than along first direction measurement 3rd width is simultaneously arranged in logic unit.
8. semiconductor devices according to claim 7, wherein the 3rd width is less than first width.
9. semiconductor devices according to claim 7, wherein at least one single diffusion interruptive area along described The length of second direction measurement is less than the length of the first double diffusion interruptive area or the second double diffusion interruptive area Length.
10. a kind of semiconductor devices, including：
Substrate, it includes first module region and second unit region adjacent to each other along a first direction, first module border Plant therebetween and extend along the second direction for intersecting the first direction；
First active patterns, it is arranged in the first module region and the second unit region along the second direction On, each of first active patterns extends along the first direction but does not intersect the first module border；
Device isolation layer, its over the substrate and exposure first active patterns top, the device isolation layer includes：
First double diffusion interruptive area, its be arranged on the first module border and on different unit areas and Between the first paired active patterns adjacent to each other along the first direction, first active patterns are at least two pairs； And
The first single diffusion interruptive area, it is arranged on from being made up of the first module region and the second unit region Selected in group it is at least one on, and on same unit region and along adjacent to each other paired of the first direction Between first active patterns；And
First grid pattern, it intersects first active patterns.
11. semiconductor devices according to claim 10, wherein the first double diffusion interruptive area is along described second Direction extends, and wherein described first double diffusion interruptive area the width along first direction measurement along described the Two directions are constant.
12. semiconductor devices according to claim 10, wherein two in the first grid pattern overlapping described the The end of one double diffusion interruptive area and at least two pair first active patterns described on different unit areas.
13. semiconductor devices according to claim 10, wherein one in the first grid pattern overlapping described the One single diffusion interruptive area is simultaneously spaced apart with the end of the first paired active patterns on same unit region.
14. semiconductor devices according to claim 10, wherein the substrate is also included along the first direction each other It is adjacent and second unit border is planted third unit region and the 4th unit area therebetween；
Second active patterns, it is arranged in the third unit region and the 4th unit area along the second direction On, each of second active patterns extends along the first direction but does not intersect the second unit border；And
Second grid pattern, it intersects second active patterns.
15. semiconductor devices according to claim 14, wherein the device isolation layer also includes：
Second double diffusion interruptive area, its be arranged on the second unit border and on different unit areas and Between the second paired active patterns adjacent to each other along the first direction, second active patterns are at least two pairs,
Wherein described second double diffusion interruptive area extends along the second direction, and wherein described second double diffusion is interrupted The width along first direction measurement in region changes along the second direction.
16. semiconductor devices according to claim 15, wherein the Breadth Maximum of the second double diffusion interruptive area is big In the width of the first double diffusion interruptive area.
17. semiconductor devices according to claim 16, wherein the minimum widith of the second double diffusion interruptive area is big In the width of the first double diffusion interruptive area.
18. semiconductor devices according to claim 15, wherein second active patterns include outmost active figure Case and along the second direction be plugged on the outmost active patterns between at least one internal active patterns,
The end of wherein described at least one internal active patterns than the outmost active patterns end closer to described Second unit border.
19. a kind of semiconductor devices, including：
Substrate, it includes first module region and second unit region adjacent to each other along a first direction, and elementary boundary is planted Extend between the first module region and the second unit region and along the second direction for intersecting the first direction；
Active patterns, it is arranged on the first module region and the second unit region along the second direction, institute The each of active patterns is stated along the first direction to extend but do not intersect the elementary boundary；
Device isolation layer, its over the substrate and the exposure active patterns part, wherein the active patterns is sudden and violent The part of dew includes active fin, and wherein described device isolation layer includes double diffusion interruptive area, the double diffusion discontinuity area Domain is arranged on the elementary boundary and on the first module region and the second unit region and along described Between first direction paired active patterns adjacent to each other, the active patterns are at least two pairs；
Gate pattern, it is arranged along the first direction and intersects the active fin along the second direction；And
First regions and source/drain, it is disposed in described active between the adjacent gate pattern in the gate pattern In the top of pattern, wherein in first regions and source/drain it is at least one including epitaxial layer and with it is described active The parallel top surface of at least one top surface in pattern.
20. semiconductor devices according to claim 19, wherein the device isolation layer also includes single diffusion interruptive area, Single diffusion interruptive area is arranged on to be selected from the group being made up of the first module region and the second unit region It is at least one upper and on identical unit area and along the first direction paired active figure adjacent to each other Between case：
Second regions and source/drain, it is disposed in the top of the active patterns, each second regions and source/drain cloth Put between gate pattern and single diffusion interruptive area and spread with the list is extended downwardly into from the gate pattern The inclined surface of interruptive area.
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US10636790B2 (en) 2020-04-28
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CN107393921B (en) 2023-04-18

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