CN104425380B - The forming method of CMOS inverter grid - Google Patents
The forming method of CMOS inverter grid Download PDFInfo
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- CN104425380B CN104425380B CN201310401303.XA CN201310401303A CN104425380B CN 104425380 B CN104425380 B CN 104425380B CN 201310401303 A CN201310401303 A CN 201310401303A CN 104425380 B CN104425380 B CN 104425380B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Abstract
A kind of forming method of grid, including：Substrate is provided, gate material layers is formed, the first list structure and the second list structure is formed in the gate material layers；The first sacrifice layer and patterned first mask layer are formed, patterned first mask layer exposes the first sacrifice layer on the first list structure；The second sacrifice layer is formed afterwards, the first photoresist with first window is formed on the second sacrifice layer, and the length of first window is equal to length of first photoresist on grid width direction；The first list structure is etched along the first window；Etch the position that the second list structure after second list structure, etching defines second grid；Using the second list structure after the first list structure after etching and etching as mask, the gate material layers are etched, grid is formed.It will not be connected with each other between adjacent two first grid in the grid formed by the technical program, grid length direction same row.
Description
Technical field
The present invention relates to semiconductor applications, a kind of forming method of CMOS inverter grid is related specifically to.
Background technology
With the development of semiconductor technology, prepare high density integrated circuit and become possible to.In order to improve the integrated level of circuit, a side
Face is to try to reduce the critical size of semiconductor devices, to reduce the area occupied by single semiconductor devices；On the other hand it is
Reduce the spacing between adjacent two device as much as possible.
Illustrated by taking the formation of grid in CMOS inverter as an example.
With reference to Fig. 1, there is provided substrate 1.
With reference to Fig. 2, gate material layers 2 are formed in the substrate 1.
With reference to Fig. 3, hard mask layer 3 is formed in the gate material layers 2.
With reference to Fig. 4 A and Fig. 4 B, the first patterned photoresist 4 is formed on the hard mask layer 3.
Fig. 4 B are the top views that the first patterned photoresist 4 is formed in the gate material layers 2, and Fig. 4 A are Fig. 4 B edges
The schematic diagram in tangent line AA ' institutes section.
It is mask with the described first patterned photoresist 4 with reference to Fig. 5 A and Fig. 5 B, etches the hard mask layer 3, is formed
The hard mask 31 of strip, and remove the described first patterned photoresist 4.
Fig. 5 B are the top views to form the hard mask 31 of strip, and Fig. 5 A are the schematic diagrames in Fig. 5 B tangentially BB ' institutes sections.
With reference to Fig. 6 A and 6B, sacrifice layer 5 is formed in the gate material layers 2 and the hard mask 31 of the strip, it is described sacrificial
The upper surface of domestic animal layer 5 is flat, and upper surface of the upper surface higher than the hard mask 31 of the strip of the sacrifice layer 5.
Fig. 6 B are the top views for foring sacrifice layer 5, and Fig. 6 A are the schematic diagrames in Fig. 6 B tangentially CC ' institutes sections.
With reference to Fig. 7 A and Fig. 7 B, the photoresist 6 with window 61 is formed on the sacrifice layer 5.
Fig. 7 B are the top views for foring photoresist 6, and Fig. 7 A are the schematic diagrames in Fig. 7 B tangentially DD ' institutes sections.
With reference to Fig. 8 A and Fig. 8 B, the sacrifice layer 5 and the hard mask 31 of the strip are etched by the window 61, figure is formed
The sacrifice layer of shape and patterned hard mask layer 32, and remove the photoresist 6 and patterned sacrifice layer.
Fig. 8 B are the top views for foring patterned hard mask layer 32, and Fig. 8 A are Fig. 8 B tangentially EE ' institutes sections
Schematic diagram.
It is mask with the patterned hard mask layer 32 with reference to Fig. 9 A and Fig. 9 B, etches the gate material layers 2, shape
Into grid 21.
Fig. 9 B are the top views for foring grid 21, and Fig. 9 A are the schematic diagrames in Fig. 9 B tangentially FF ' institutes sections.
The grid 21 prepared by the above method, even if grid 21 arranges very close, forms CMOS anti-in being staggered
After phase device, the electric signal being also possible to prevent between adjacent two phase inverter is interfered, it is thereby possible to reduce between adjacent two device
Spacing, increase integrated circuit integrated level.
With reference to Fig. 7 B, still, because the area of window 61 is too small, in photoresist 6 of the exposure imaging formation with window 61,
Easily the pattern of window 61 is set to deform, and the residue produced when easily attachment is developed in window 61.Pass through the window 61
When etching the hard mask 31 of strip, etching is easily caused incomplete.It is again mask with the patterned hard mask layer 32, etches institute
When stating gate material layers 2, the grid 22 of formation may be connected with each other, the CMOS inverter failure resulted in.
The content of the invention
The problem of present invention is solved is that in the prior art, grid may be connected with each other.
To solve the above problems, the present invention provides a kind of forming method of CMOS inverter grid, grid is divided into the first grid
Pole and second grid, first grid and second grid are in have two adjacent row in periodic arrangement, each cycle in grid width direction
First grid and two adjacent row second grids, and first grid and second grid are in grid width direction Heterogeneous Permutation；Methods described
Including：
Substrate is provided, gate material layers is formed on the substrate, multiple parallels is formed in the gate material layers
The first list structure and the second list structure of row, the first list structure define position of the first grid in grid width direction, second
List structure defines position of the second grid in grid width direction；
The first sacrifice layer is formed in first list structure, the second list structure and gate material layers, described
Patterned first mask layer is formed on one sacrifice layer, the first sacrifice layer upper surface is flat, described patterned first covers
Film layer exposes the first sacrifice layer on the first list structure；
The second sacrifice layer is formed on first sacrifice layer and patterned first mask layer, the shape on the second sacrifice layer
Into the first photoresist with first window, the second sacrifice layer upper surface is flat, and the first window defines grid length direction
The distance between upper adjacent two first grid, the length of first window is equal to length of first photoresist on grid width direction；
Second sacrifice layer, the first sacrifice layer and the first list structure are etched along the first window, then is removed described
First photoresist, the second sacrifice layer, the first sacrifice layer and patterned first mask layer；
Etch the position that the second list structure after second list structure, etching defines second grid；
Using the second list structure after the first list structure after etching and etching as mask, the grid material is etched
Layer, forms first grid and second grid.
Optionally, etching the method for second list structure includes：
3rd sacrifice layer is formed on the first list structure after the gate material layers, the second list structure and etching,
Patterned second mask layer is formed in the 3rd sacrifice layer upper surface, patterned second mask layer exposes the second strip knot
3rd sacrifice layer on structure, the 3rd sacrifice layer upper surface is flat；
The 4th sacrifice layer is formed in the 3rd sacrifice layer and patterned second mask layer, in the 4th sacrifice layer
Upper to form the second photoresist with the second window, the 4th sacrifice layer upper surface is flat, and the second window definition grid are long
The distance between adjacent two second grid on direction, the length of the second window is equal to length of second photoresist on grid width direction
Degree；
Along the 4th sacrifice layer, 3rd sacrifice layer and the second list structure described in second opening etch, then remove described
Second photoresist, 3rd sacrifice layer, the 4th sacrifice layer and patterned second mask layer.
Optionally, formed after first grid and second grid, in addition to：
Remove the first list structure after etching and the second list structure after etching.
Optionally, projection and first window projection section on substrate of second window in substrate is overlapping；Or,
Projection and first window projection on substrate of second window in substrate is spaced from each other.
Optionally, the first sacrifice layer, the second sacrifice layer, 3rd sacrifice layer and the 4th sacrifice layer are silicon oxide layer, silicon nitride
Layer or silicon carbide layer.
Optionally, patterned first mask layer and patterned second mask layer are titanium nitride layer or silicon nitride layer.
Optionally, the material of first list structure and the second list structure is titanium nitride or silicon nitride.
Optionally, formed before the first photoresist, sequentially form the first hard mask from the bottom to top on second sacrifice layer
Layer and the first bottom anti-reflection layer, the first photoresist formation is in first bottom anti-reflection layer.
Optionally, formed before the second photoresist, the second hard mask is sequentially formed from the bottom to top on the 4th sacrifice layer
Layer and the second bottom anti-reflection layer, the second photoresist formation is in second bottom anti-reflection layer.
Optionally, the first hard mask layer and the second hard mask layer are titanium nitride layer or silicon nitride layer.
Optionally, the first bottom anti-reflection layer and the second bottom anti-reflection layer are organic bottom antireflective layer or Inorganic bottom
Anti-reflecting layer.
Optionally, the gate material layers are polysilicon layer.
Optionally, formed on the substrate before gate material layers, form gate dielectric layer, the grid on the substrate
Material layer formation is on the gate dielectric layer.
Optionally, multiple first list structures and the second list structure arranged in parallel are formed in the gate material layers
Method include：
List structure material layer is formed in the gate material layers；
Patterned photoresist is formed in the list structure material layer；
Using the patterned photoresist as mask, the list structure material layer is etched, is formed multiple arranged in parallel
First list structure and the second list structure.
Optionally, before forming patterned photoresist in the list structure material layer, in the list structure material
The 3rd hard mask layer and the 3rd bottom anti-reflection layer are sequentially formed on layer from the bottom to top, the patterned photoresist formation is in institute
State in the 3rd bottom anti-reflection layer.
Compared with prior art, technical scheme has advantages below：
The technical program first exposes the first sacrifice layer on the first list structure using patterned first mask layer, to have
The first photoresist for having first window is mask, etches the first list structure；The length of first window exists equal to the first photoresist
Length on grid width direction, so the area of first window is very big, can prevent during exposure imaging first window deform or
Adhere to residue.And then, the first list structure in grid length direction same row after adjacent two etching can be prevented to be connected with each other.To carve
The first list structure after erosion is mask, etches the gate material layers, is formed after first grid, phase in grid length direction same row
Adjacent two first grids are spaced from each other, it is therefore prevented that adjacent two first grid is connected with each other in grid length direction same row.
Further, the 3rd sacrifice layer on the second list structure is exposed using patterned second mask layer, with the
Second photoresist of two windows is mask, etches the second list structure.The length of second window is equal to the second photoresist in grid width
Length on direction, so the area of the second window is very big, can prevent that the second window deforms or adhered to during exposure imaging
Residue.And then, the second list structure in grid length direction same row after adjacent two etching can be prevented to be connected with each other.After etching
The second list structure be mask, etch the gate material layers, formed after second grid, adjacent two in grid length direction same row
Second grid is spaced from each other, it is therefore prevented that adjacent two second grid is connected with each other in grid length direction same row.
Brief description of the drawings
Fig. 1 to Fig. 9 B is the schematic diagram for forming grid each production phase in the prior art；
Figure 10 to Figure 25 B is the schematic diagram of formation grid each production phase in the specific embodiment of the invention.
Embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The present embodiment provides a kind of forming method of CMOS inverter grid, and grid is divided into first grid and second grid,
First grid and second grid are in periodic arrangement in grid width direction, and each cycle is interior with two adjacent row first grids and adjacent
Two row second grids, and first grid and second grid are in grid width direction Heterogeneous Permutation；The shape of the CMOS inverter grid
Include into method：
With reference to Figure 10, there is provided substrate 110.
In a particular embodiment, the material of the substrate 110 is monocrystalline silicon, polysilicon, non-crystalline silicon or silicon-on-insulator.Institute
State in substrate 110 and could be formed with source electrode and drain electrode.
With reference to Figure 11, gate material layers 120 are formed in the substrate 110.
The method for forming the gate material layers 120 can be chemical vapor deposition, physical vapour deposition (PVD), ald
Or epitaxial growth method.The gate material layers 120 can be polysilicon layer.
In other embodiments, formed in the substrate 110 before gate material layers 120, can be in the substrate 110
Gate dielectric layer is initially formed, gate material layers 120 are then formed on the gate dielectric layer.
Then multiple first list structures arranged in parallel and the second strip knot are formed in the gate material layers 120
Structure, the first list structure defines position of the first grid in grid width direction, and the second list structure defines second grid in grid width side
To position, i.e., the length direction of described grid width direction vertical first list structure and the second list structure.
Forming the method for multiple first list structures arranged in parallel and the second list structure includes：
With reference to Figure 12, list structure material layer 130 is formed in the gate material layers 120.
The method for forming list structure material layer 130 can be chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition
The other methods known in the art such as product.For example physical vapour deposition (PVD) can for use Ar and N2 plasmas as sputter from
Son, Ar the and N2 plasma strikes and the material identical target of list structure material layer 130, by the molecules strike in target
Depart from target, deposit in the gate material layers 120, form list structure material layer 130.
In a particular embodiment, the list structure material layer 130 is titanium nitride layer or silicon nitride layer.
With reference to Figure 13 A and Figure 13 B, patterned photoresist 103 is formed in the list structure material layer 130.
Figure 13 B are the top view for foring patterned photoresist 103, and Figure 13 A are Figure 13 B tangentially AA ' institutes sections
Schematic diagram.
In other embodiments, formed in the list structure material layer 130 before patterned photoresist 103, in institute
State and sequentially form the 3rd hard mask layer and the 3rd bottom anti-reflection layer in list structure material layer 130 from the bottom to top, the figure
The photoresist 103 of change is formed in the 3rd bottom anti-reflection layer.
The mask for functioning as etching list structure material layer 130 of 3rd hard mask layer, the 3rd bottom
The effect of anti-reflecting layer is to reduce reflection effect when forming patterned photoresist 103, is turned with improving the accurate of fine pattern
Move.
When the list structure material layer 130 is titanium nitride layer, the 3rd hard mask layer can be silicon nitride layer or cryogenic oxygen
SiClx layer；When the list structure material layer 130 is silicon nitride, the 3rd hard mask layer can be titanium nitride layer or cryogenic oxidation silicon
Layer.To ensure that the 3rd hard mask layer can be as the mask for etching list structure material layer 130.The 3rd bottom anti-reflective
It can be organic bottom antireflective layer or Inorganic bottom antireflective layer to penetrate layer.
It is mask with the patterned photoresist 103 with reference to Figure 14 A and Figure 14 B, etches the list structure material layer
130, form multiple first list structure 131A and the second list structure 131B arranged in parallel.Then, remove described graphical
Photoresist 103.
First list structure 131A and the second list structure 131B are in periodic arrangement on grid width direction, are had in each cycle
There are two first adjacent list structure 131A and two second adjacent list structure 131B.
It is adjacent to refer to middle no other structures in this specific embodiment.Two first i.e. adjacent list structure 131A are
Refer to no formation the second list structure 131B or other first list structures 131A between the two first list structure 131A.Together
Reason, two second adjacent list structure 131B refer to the first list structure of no formation between the two second list structure 131B
131A or other second list structures 131B.
Figure 14 B are the top view for foring the first list structure 131A and the second list structure 131B, and Figure 14 A are Figure 14 B
The tangentially schematic diagram in BB ' institutes section.In order to distinguish, in Figure 14 A and Figure 14 B, the first list structure 131A and the second strip
Structure 131B has used different fillings.
The method for etching the list structure material layer 130 can be plasma etching method.
With reference to Figure 15 A and Figure 15 B, in the first list structure 131A and the second list structure 131B and gate material layers
The first sacrifice layer 141 is formed on 120, the upper surface of the first sacrifice layer 141 is flat.The upper surface of first sacrifice layer 141 is high
In the first list structure 131A and the second list structure 131B upper surface.
Figure 15 B are the top view for foring the first sacrifice layer 141, and for Figure 15 B, tangentially CC ' institute sections show Figure 15 A
It is intended to.
The method for forming the first sacrifice layer 141 is spin-coating method or sedimentation.
In a particular embodiment, the first sacrifice layer 141 be silicon oxide layer, silicon nitride layer or silicon carbide layer, and first sacrifice
The material of layer 141 must be different from the material of list structure material layer 130, and when etching the first sacrifice layer 141, first sacrifices
The list structure 131A and the second list structure 131B of layer 141 and first has higher etching selection ratio.Such as list structure material
The material of layer 130 is silicon nitride, and the material of the first sacrifice layer 141 can be titanium nitride.
The effect of first sacrifice layer 141 is to provide flat upper surface to be subsequently formed patterned first mask layer.
With reference to Figure 16 A and Figure 16 B, patterned first mask layer 151 is formed on first sacrifice layer 141, it is described
Patterned first mask layer 151 exposes the first sacrifice layer 141 on the first list structure 131A.
Figure 16 B are the top view for foring patterned first mask layer 151, and by Figure 16 B, tangentially DD ' is cut Figure 16 A
The schematic diagram of plane.
The material of patterned first mask layer 151 should be with the first sacrifice layer 141 and the material of list structure material layer 130
It is all different.And when the first sacrifice layer 141 of etching, the first list structure 131A and the second list structure 131B, the first sacrifice layer 141
There is higher etching selection ratio, the first list structure 131A and the second list structure with patterned first mask layer 151
131B also has higher etching selection ratio with patterned first mask layer 151.As the material of list structure material layer 130 is
Silicon nitride, the material of the first sacrifice layer 141 is titanium nitride, and the material of patterned first mask layer 151 can be low-temperature oxidation
Silicon.
In a particular embodiment, forming the method for patterned first mask layer 151 includes：
The first mask layer is formed on the first sacrifice layer 141；
Patterned photoresist is formed on first mask layer；
Using the patterned photoresist as mask, first mask layer is etched, patterned first is formed and covers
Film layer 151；
Remove the patterned photoresist.
Forming the effect of patterned first mask layer 151 is, when etching the first list structure 131A, protects Article 2
Shape structure 131B, is not etched the second list structure 131B.
With reference to Figure 17 A and Figure 17 B, second is formed on first sacrifice layer 141 and patterned first mask layer 151
Sacrifice layer 142, the upper surface of the second sacrifice layer 142 is flat.The upper surface of second sacrifice layer 142 is higher than described patterned
The upper surface of first mask layer 151.
Figure 17 B are the top view for foring the second sacrifice layer 142, and for Figure 17 B, tangentially EE ' institute sections show Figure 17 A
It is intended to.
The material and forming method of second sacrifice layer 142 may be referred to the material and forming method of the first sacrifice layer 141.
With reference to Figure 18 A and Figure 18 B, the first photoresist with first window 161 is formed on second sacrifice layer 142
101, the vertical first list structure 131A of length direction of the first window 161 length direction.First window 161 is determined
The distance between adjacent two first grid of adopted grid length direction.
Wherein grid length direction is parallel with the first list structure 131A and the second list structure 131B length direction.
Figure 18 B are the top view for foring the first photoresist 101, and for Figure 18 B, tangentially FF ' institute sections show Figure 18 A
It is intended to.
The length of first window 161 is equal to size of first photoresist 101 on grid width direction, i.e. first window 161 exists
Grid width side extends upward through whole first photoresist 101.So the area of first window 161 is very big, when can prevent exposure imaging
First window 161 deforms, and prevents in the side wall of first window 161 and bottom attachment residue.
Wherein grid width direction is perpendicular to grid length direction.
In other embodiments, formed the first photoresist 101 before, can first on second sacrifice layer 142 by it is lower extremely
On sequentially form the first hard mask layer and the first bottom anti-reflection layer, first photoresist 101 is formed in first bottom
On anti-reflecting layer.
Wherein, first hard mask layer functions as the second sacrifice layer 142 of etching, the first sacrifice layer 141 and the
One list structure 131A mask, the effect of the first bottom anti-reflection layer is to reduce reflection effect when forming the first photoresist 101
Should, to improve the accurate transfer of fine pattern.
When etching the second sacrifice layer 142, the first sacrifice layer 141 and the first list structure 131A, the second sacrifice layer is etched
142nd, the first sacrifice layer 141 and the first list structure 131A and the second hard mask layer have higher etching selection ratio.Specific
In embodiment, the first hard mask layer is titanium nitride layer or silicon nitride layer；First bottom anti-reflection layer can be organic bottom
Anti-reflecting layer or Inorganic bottom antireflective layer.
With reference to Figure 19 A and Figure 19 B, second sacrifice layer 142, the first sacrifice layer 141 are etched along the first window 161
With the first list structure 131A；Then first photoresist 101, the second sacrifice layer 142, the first sacrifice layer 141 and figure are removed
First mask layer 151 of shape.
Figure 19 B is remove first photoresist 101, the second sacrifice layer 142, the first sacrifice layer 141 and patterned the
Top view after one mask layer 151, Figure 19 A for Figure 19 B tangentially GG ' institutes sections schematic diagram.
Because the second list structure 131B the first mask layers 151 being patterned are covered, so the second list structure 131B
It will not be etched.
The first list structure 131A by patterned first mask layer 151 due to not covered, so every 1
One list structure 131A is etched to some segments.Every one first list structure 131A is etched to segment 132 and small in Figure 19 B
Section 133.
Because first window 161 will not deform, and residue is not adhered in the side wall of first window 161 and bottom, so
When etching the first list structure 131A by first window 161, the first list structure 131A of exposure can be etched completely, can
To prevent the first list structure in grid length direction same row after adjacent two etching to be connected with each other.Between adjacent segment completely every
Open, will not be connected with each other.It is i.e. completely separated between segment 132 and segment 133.
Moreover, first window 161 is big due to area, pattern preferably, can reduce shape after the first list structure 131A of etching
Into segment 132 and segment 133 line edge roughness.
Then, the position that the second list structure after the second list structure 131B, etching defines second grid is etched.
Etching the method for the second list structure 131B includes：
With reference to Figure 20 A and Figure 20 B, the first list structure 131A and Article 2 after the gate material layers 120, etching
3rd sacrifice layer 143 is formed on shape structure 131B, the upper surface of 3rd sacrifice layer 143 is flat.
Figure 20 B are the top view for foring 3rd sacrifice layer 143, and for Figure 20 B, tangentially HH ' institute sections show Figure 20 A
It is intended to.
The forming method and material of 3rd sacrifice layer 143 may be referred to the forming method and material of the first sacrifice layer 141.
The effect of the 3rd sacrifice layer 143 is to provide flat surface to be subsequently formed patterned second mask layer.
With reference to Figure 21 A and Figure 21 B, patterned second mask layer 152, figure are formed in the 3rd sacrifice layer upper surface
The second mask layer 152 changed exposes the 3rd sacrifice layer 143 on the second list structure 131B, patterned second mask layer 152
The first list structure 131A after covering etching.
Figure 21 B are the top view for foring patterned second mask layer 152, and by Figure 21 B, tangentially II ' is cut Figure 21 A
The schematic diagram of plane.
In a particular embodiment, forming the method for patterned second mask layer 152 includes：
The second mask layer is formed in 3rd sacrifice layer 143；
Patterned photoresist is formed on second mask layer；
Using the patterned photoresist as mask, second mask layer is etched, patterned second is formed and covers
Film layer 152；
Remove the patterned photoresist.
The material of patterned second mask layer 152 may be referred to the material of patterned first mask layer 151.
With reference to Figure 22 A and Figure 22 B, the 4th is formed in the 3rd sacrifice layer 143 and patterned second mask layer 152
Sacrifice layer 144, the upper surface of the 4th sacrifice layer 144 is flat.
Figure 22 B are the top view for foring the 4th sacrifice layer 144, and for Figure 22 B, tangentially JJ ' institute sections show Figure 22 A
It is intended to.
The forming method and material of 4th sacrifice layer 144 may be referred to the forming method and material of the first sacrifice layer 141.
The effect of 4th sacrifice layer 144 is to provide flat surface to be subsequently formed the second photoresist.
With reference to Figure 23 A and Figure 23 B, the second photoresist with the second window 162 is formed on the 4th sacrifice layer 144
102, the length direction of the length direction of second window 162 parallel to first window 161.Second window 162 is defined
The distance between adjacent two second grid on grid length direction.
Figure 23 B are the top view for foring the second photoresist 102, and for Figure 23 B, tangentially KK ' institute sections show Figure 23 A
It is intended to.
The length of second window 162 is equal to the length of first window 161, i.e., the second window 162 is in the length of the second window 162
Side extends upward through whole second photoresist 102.So the area of the second window 162 is very big, second when can prevent exposure imaging
Window 162 deforms, and prevents in the side wall of the second window 162 and bottom attachment residue.
In other embodiments, formed the second photoresist 102 before, can first on the 4th sacrifice layer 144 by it is lower extremely
On sequentially form the second hard mask layer and the second bottom anti-reflection layer, second photoresist 102 is formed in second bottom
On anti-reflecting layer.
Wherein, the mask for functioning as the second list structure 131B of etching of second hard mask layer, the second bottom
The effect of anti-reflecting layer is to reduce reflection effect when forming the second photoresist 102, to improve the accurate transfer of fine pattern.
The material of second hard mask layer may be referred to the material of the first hard mask layer.Second bottom anti-reflection layer can be with
For organic bottom antireflective layer or Inorganic bottom antireflective layer.
In the present embodiment, projection and first window 161 throwing on substrate 110 of second window 162 in substrate 110
Shadow is spaced from each other, non-overlapping.So that first grid and second grid are in grid width direction Heterogeneous Permutation.
In other embodiments, projection and first window 161 of second window 162 in substrate 110 are in substrate 110
Projection can also partly overlap.
With reference to Figure 24 A and Figure 24 B, the 4th sacrifice layer 144,3rd sacrifice layer 143 are etched along second window 162
With the second list structure 131B.Then, second photoresist 102,3rd sacrifice layer 143, the 4th sacrifice layer 144 and figure are removed
Second mask layer 152 of shape.
Figure 24 B is eliminate second photoresist 102,3rd sacrifice layer 143, the 4th sacrifice layer 144 and patterned
The top view of second mask layer 152, Figure 24 A for Figure 24 B tangentially LL ' institutes sections schematic diagram.
Because the second mask layers 152 being patterned of the first list structure 131A after etching are covered, so after etching
First list structure 131A will not be etched.
The second list structure 131B by patterned second mask layer 152 due to not covered, so every 1
Two list structure 131B are etched to some segments.With reference to Figure 24 B, every one second list structure 131B be etched to segment 134,
Segment 135 and segment 136.
Because the second window 162 will not deform, and residue is not adhered in the side wall of the second window 162 and bottom, so
When etching the second list structure 131B by the second window 162, the second list structure 131B of exposure can be etched completely, can
To prevent the second list structure in grid length direction same row after adjacent two etching to be connected with each other.That is segment 134, the and of segment 135
It is completely separated between segment 136.
Moreover, the second window 162 is big due to area, pattern preferably, can reduce shape after the second list structure 131B of etching
Into segment 134, segment 135 and segment 136 line edge roughness.
With reference to Figure 25 A and Figure 25 B, with the second list structure 131B after the first list structure 131A after etching and etching
For mask, the gate material layers 120 are etched, first grid 121A and second grid 121B is formed.And remove after etching the
One list structure 131A and the second list structure 131B after etching.
Figure 25 B are the top view for foring first grid 121A and second grid 121B, and Figure 25 A are Figure 25 B tangentially MM '
The schematic diagram in institute section.
Because the segment in the second list structure 131B after the first list structure 131A after etching and etching is all mutual
Separate, and line edge roughness is small；With the second list structure 131B after the first list structure 131A after etching and etching
For mask, it is therefore prevented that adjacent two first grids 121A is connected with each other in grid length direction same row, is also possible to prevent grid length direction same
The one upper adjacent two second grids 121B of row.And first grid 121A and second grid 121B line edge roughness are small.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
1. a kind of forming method of CMOS inverter grid, grid is divided into first grid and second grid, first grid and second
Grid is in have two adjacent row first grids and two adjacent row second gates in periodic arrangement, each cycle in grid width direction
Pole, and first grid and second grid are in grid width direction Heterogeneous Permutation；Characterized in that, methods described includes：
Substrate is provided, gate material layers is formed on the substrate, forms multiple arranged in parallel in the gate material layers
First list structure and the second list structure, the first list structure define position of the first grid in grid width direction, the second strip
Structure defines position of the second grid in grid width direction；
The first sacrifice layer is formed in first list structure, the second list structure and gate material layers, it is sacrificial described first
Patterned first mask layer is formed on domestic animal layer, the first sacrifice layer upper surface is flat, patterned first mask layer
Cover the first sacrifice layer on the first sacrifice layer and the first list structure of exposure on the second list structure；
The second sacrifice layer is formed on first sacrifice layer and patterned first mask layer, tool is formed on the second sacrifice layer
There is the first photoresist of first window, the second sacrifice layer upper surface is flat, and the first window defines phase on grid length direction
The distance between adjacent two first grids, the length of first window is equal to length of first photoresist on grid width direction；
Second sacrifice layer, the first sacrifice layer and the first list structure are etched along the first window, then removes described first
Photoresist, the second sacrifice layer, the first sacrifice layer and patterned first mask layer；
Etch the position that the second list structure after second list structure, etching defines second grid, etching described second
The method of list structure includes：Formed on the first list structure after the gate material layers, the second list structure and etching
3rd sacrifice layer, forms patterned second mask layer in the 3rd sacrifice layer upper surface, and patterned second mask layer covers
In the 3rd sacrifice layer in 3rd sacrifice layer and the second list structure of exposure on the list structure of lid first, the 3rd sacrifice layer
Surface is flat；The 4th sacrifice layer is formed in the 3rd sacrifice layer and patterned second mask layer, is sacrificed the described 4th
The second photoresist with the second window is formed on layer, the 4th sacrifice layer upper surface is flat, the second window definition grid
The distance between adjacent two second grid on length direction, the length of the second window is equal to length of second photoresist on grid width direction
Degree；Along the 4th sacrifice layer, 3rd sacrifice layer and the second list structure described in second opening etch, then remove second light
Photoresist, 3rd sacrifice layer, the 4th sacrifice layer and patterned second mask layer；
Using the second list structure after the first list structure after etching and etching as mask, the gate material layers, shape are etched
Into first grid and second grid.
2. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that form first grid and second
After grid, in addition to：
Remove the first list structure after etching and the second list structure after etching.
3. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that the second window is in substrate
The projection section projected with first window in substrate is overlapping；Or,
Projection and first window projection on substrate of second window in substrate is spaced from each other.
4. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that the first sacrifice layer, second sacrificial
Domestic animal layer, 3rd sacrifice layer and the 4th sacrifice layer are silicon oxide layer, silicon nitride layer or silicon carbide layer.
5. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that patterned first mask layer
It is titanium nitride layer or silicon nitride layer with patterned second mask layer.
6. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that first list structure and
The material of second list structure is titanium nitride or silicon nitride.
7. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that formed before the first photoresist,
Sequentially form the first hard mask layer and the first bottom anti-reflection layer, first photoetching from the bottom to top on second sacrifice layer
Glue formation is in first bottom anti-reflection layer.
8. the forming method of the CMOS inverter grid as described in claim 1 or 7, it is characterised in that form the second photoresist
Before, sequentially form the second hard mask layer and the second bottom anti-reflection layer, described second from the bottom to top on the 4th sacrifice layer
Photoresist formation is in second bottom anti-reflection layer.
9. the forming method of CMOS inverter grid as claimed in claim 8, it is characterised in that the first hard mask layer and second
Hard mask layer is titanium nitride layer or silicon nitride layer.
10. the forming method of CMOS inverter grid as claimed in claim 8, it is characterised in that the first bottom anti-reflection layer
It is organic bottom antireflective layer or Inorganic bottom antireflective layer with the second bottom anti-reflection layer.
11. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that the gate material layers are
Polysilicon layer.
12. the forming method of the CMOS inverter grid as described in claim 1 or 11, it is characterised in that
Formed on the substrate before gate material layers, form gate dielectric layer on the substrate, the gate material layers are formed
On the gate dielectric layer.
13. the forming method of CMOS inverter grid as claimed in claim 1, it is characterised in that in the gate material layers
Upper multiple first list structures arranged in parallel and the method for the second list structure of being formed include：
List structure material layer is formed in the gate material layers；
Patterned photoresist is formed in the list structure material layer；
Using the patterned photoresist as mask, the list structure material layer is etched, multiple arranged in parallel first are formed
List structure and the second list structure.
14. the forming method of CMOS inverter grid as claimed in claim 13, it is characterised in that in the list structure material
Formed on the bed of material before patterned photoresist, the 3rd hard mask layer is sequentially formed from the bottom to top in the list structure material layer
With the 3rd bottom anti-reflection layer, the patterned photoresist formation is in the 3rd bottom anti-reflection layer.
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| CN102623457A (en) * | 2011-01-26 | 2012-08-01 | 旺宏电子股份有限公司 | Semiconductor structure, manufacturing method thereof and operating method |
| CN102683191A (en) * | 2011-03-17 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method forming gate pattern and semiconductor device |
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| CN102683191A (en) * | 2011-03-17 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method forming gate pattern and semiconductor device |
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