CN104425376A - Manufacture method of CMOS tube, and CMOS tube - Google Patents

Manufacture method of CMOS tube, and CMOS tube Download PDF

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Publication number
CN104425376A
CN104425376A CN201310381820.5A CN201310381820A CN104425376A CN 104425376 A CN104425376 A CN 104425376A CN 201310381820 A CN201310381820 A CN 201310381820A CN 104425376 A CN104425376 A CN 104425376A
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Prior art keywords
trap
dark
cmos
tube
ion
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王晓芸
陈建国
贺冠中
张枫
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Priority to CN201310381820.5A priority Critical patent/CN104425376A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a manufacture method of a CMOS tube, and a CMOS tube. The method comprises manufacturing a PMOS tube on the surface of an N trap and manufacturing an NMOS tube on the surface of a P trap. Before the PMOS tube is manufactured on the surface of the N trap and the NMOS tube is manufactured on the surface of the P trap, the method also comprises injecting N-type ions in the surface of a substrate to form a deep N trap and manufacturing the N trap and the P trap on the surface of the deep N trap. The manufacture method of the CMOS tube can enable the NMOS tube in the manufactured CMOS tube to be connected with different biases so as to improve the circuit flexibility.

Description

The manufacture method of CMOS tube and CMOS tube
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of manufacture method and CMOS tube of CMOS tube.
Background technology
Complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor is called for short CMOS) is in integrated circuit design, adopts NMOS tube and PMOS two kinds of devices simultaneously, and a kind of circuit structure of pairing appearance usually.Because the quiescent dissipation of cmos circuit is very little, circuit structure is simple, makes it may be used for large scale integrated circuit, very lagre scale integrated circuit (VLSIC).
Fig. 1 is the structural representation of cmos device in prior art.As shown in Figure 1, prior art by forming P trap 102 and N trap 103 by ion implantation on the substrate 101, and makes NMOS tube on P trap 102 surface respectively, makes PMOS on N trap surface.This NMOS tube comprises source electrode 104, drain electrode 105 and grid 106, and this PMOS comprises drain electrode 107, source electrode 108 and grid 109.If substrate 101 is P type substrate, the substrate bias due to NMOS tube is specific voltage, and threshold voltage during this NMOS tube conducting is also specific voltage, makes the very flexible of circuit.
Summary of the invention
The invention provides a kind of manufacture method and CMOS tube of CMOS tube, to solve the problem of the traditional cmos pipe very flexible in circuit application adopting prior art to make.
First aspect, the invention provides a kind of manufacture method of CMOS tube, is included in N trap surperficial making PMOS, in P trap surperficial making NMOS tube, described in N trap surface making PMOS, before P trap surperficial making NMOS tube, also comprises:
Inject N-type ion at substrate surface, form dark N trap;
Described N trap and described P trap is made on described dark N trap surface.
Second aspect, the present invention also provides a kind of CMOS tube to comprise: the PMOS made on N trap surface and the NMOS tube made on P trap surface, and described P trap is the P trap made on dark N trap surface; Described dark N trap is the N trap made at substrate surface;
Described N trap is the N trap made on described dark N trap surface.
The manufacture method of the CMOS tube that the present embodiment provides, by before the P trap needed for this NMOS, make dark N trap, in the CMOS tube that final making obtains, NMOS tube becomes suspension NMOS tube, the underlayer voltage of this suspension NMOS tube can access different voltage respectively by P trap and substrate, therefore threshold voltage during this NMOS tube conducting is just different bias voltage, improves the flexibility of circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of cmos device in prior art;
The flow chart of the manufacture method of the CMOS tube that Fig. 2 provides for the embodiment of the present invention one;
The flow chart of the manufacture method of the CMOS tube that Fig. 3 provides for the embodiment of the present invention three;
Fig. 4 is the structural representation growing the first pad oxide in the embodiment of the present invention three;
Fig. 5 is the structural representation forming dark N trap in the embodiment of the present invention three;
Fig. 6 is the structural representation after carrying out the propelling of dark N trap in the embodiment of the present invention three;
Fig. 7 is the structural representation being formed with source region figure in the embodiment of the present invention three;
Fig. 8 is the structural representation forming N trap in the embodiment of the present invention three;
Fig. 9 is the structural representation forming P trap in the embodiment of the present invention three;
Figure 10 is the structural representation forming field oxide in the embodiment of the present invention three;
Figure 11 is the structural representation of the formation grid in the embodiment of the present invention three;
Figure 12 is the structural representation forming source-drain electrode in the embodiment of the present invention three;
Figure 13 is the structural representation forming fairlead graph layer in the embodiment of the present invention three;
Figure 14 is the structural representation forming metal wiring layer in the embodiment of the present invention three;
Figure 15 is the structural representation of CMOS tube made in the embodiment of the present invention three;
The structural representation of the CMOS tube that Figure 16 provides for the embodiment of the present invention four.
Description of reference numerals:
101,401,601,1601: substrate;
102,902,1002,1604:P trap;
103,802,901,1001,1603:N trap;
104,1201, the source electrode of 1607:NMOS pipe;
105,1202, the drain electrode of 1608:NMOS pipe;
106,1104, the grid of 1609:NMOS pipe;
107,1203, the drain electrode of 1610:PMOS pipe;
108,1204, the source electrode of 1612:PMOS pipe;
109,1105, the grid of 1611:PMOS pipe;
402: the first pad oxides;
501,602,801,1602: dark N trap;
701: the second oxide layers;
702: silicon nitride layer;
703: the first active area figures;
704: the second active area figures;
1003: field oxide;
1101: grid oxic horizon;
1102: grid polycrystalline silicon;
1103: gate metal articulamentum;
1301: fairlead graph layer;
1401: metal wiring layer;
1501: passivation layer;
1605:NMOS manages;
1606:PMOS manages.
Embodiment
Embodiment one
The embodiment of the present invention one provides a kind of manufacture method of CMOS tube.The flow chart of the manufacture method of the CMOS tube that Fig. 2 provides for the embodiment of the present invention one.The method, is included in N trap surface and makes PMOS, make NMOS tube on P trap surface.As shown in Figure 2, make PMOS on N trap surface, before P trap surface makes NMOS tube, also comprise:
Step 201, inject N-type ion at substrate surface, form dark N trap.
Particularly, evenly inject N-type ion at whole substrate surface, form the dark N trap with N-type sheath.N-type ion can be V race's ion, as phosphorus, antimony, arsenic etc. any one, also can be the compound ions with V valence charge.
Step 202, make described N trap and described P trap on described dark N trap surface.
Mostly existing CMOS manufacture method is to make N trap and P trap at substrate surface, then makes PMOS at the upper surface of N trap, makes NMOS at the upper surface of P trap.The present embodiment injects N ion by the surface uniform at whole dark N trap, forms initial stage N trap, then hides the part of this N trap and implanting p-type ion by light shield mask, forms P trap.The N trap of follow-up making PMOS is by the region that light shield mask hides.Because the region of implanting p-type ion is also filled with N-type ion at first, therefore, the dosage forming the P type ion that P trap injects should be greater than the dosage of the initial N-type ion injected.
Making N trap and P trap on dark N trap surface can also be that N-type ion is injected in a part of region hiding dark N trap surface by light shield mask, forms N trap, then is hidden the region implanting p-type ion of another part on dark N trap surface by light shield mask, forms P trap.
But due to the requirement of light shield masking process to equipment and process parameter higher, therefore form N trap and P trap in the present embodiment and can adopt and first inject N trap ion, then by light shield mask implanting p-type ion, by means of only a light shield mask, form N trap and P trap.
The scheme that the present embodiment provides, when making CMOS tube, by before the P trap needed for this NMOS, make dark N trap, in the CMOS tube that final making obtains, NMOS tube becomes suspension NMOS tube, the underlayer voltage of this suspension NMOS tube can access different voltage respectively by P trap and substrate, and the threshold voltage therefore during this NMOS tube conducting is just different bias voltage, improves the flexibility of circuit.
Embodiment two
On the basis of above-described embodiment, the embodiment of the present invention two also provides a kind of manufacture method of CMOS tube.
In technique scheme, described substrate is P type substrate; The crystal orientation of described substrate is 100, and resistivity is 15-25 Ω .cm.
Specifically, P type substrate, refers to the P type ion of the trace that to adulterate in the growth course of monocrystalline substrate.P type ion is III race's element ion, as boron.Due to N-type raceway groove participation conduction is electronics, and P type raceway groove parameter conduction is hole, and the mobility of electronics is far longer than the mobility in hole, i.e. electric conductivity the conducting electricity very well than P type raceway groove of N-type raceway groove.For ensureing the performance of N-type raceway groove in CMOS tube, namely the performance of NMOS tube, preferentially selects P type substrate.
The present embodiment specifically selects crystal orientation to be 100, and resistivity is the P type substrate of 15-25 Ω .cm.
In such scheme, form the N trap ion that dark N trap injects and be specially phosphonium ion; The energy of described injection N-type ion is 100kev, and dosage is 5E12/cm 2.
The energy injecting ion determines that the injection degree of depth of ion, dosage determine to inject the concentration of ion.
Further, in such scheme, inject N-type ion at substrate surface in step 201, before forming dark N trap, also comprise:
At described substrate surface growth pad oxide, the thickness of described pad oxide is
Particularly, for avoiding the crystal circle structure of substrate surface in the process injecting N-type ion, may outer damage be subject to, therefore before injection N trap ion, can pad oxide be grown.This pad oxide is preferably silicon dioxide layer, and its thickness is preferably the method of growth silicon dioxide layer can be adopt thermal oxidation method.Adopting thermal oxidation method to grow the first pad oxide can be inserted in oxidation furnace by this substrate to heat certain hour, forms the oxide layer of specific thicknesses.Thermal oxidation process is divided into dry oxidation and wet oxidation.If be full of oxygen in oxidation furnace, being then dry method thermal oxidation, if be full of steam and oxygen in oxidation furnace, is then wet oxidation.Grow the time of the first pad oxide by controlled oxidization, carry out the thickness of controlled oxidization layer.
Further, in such scheme, inject N-type ion at substrate surface in step 201, after forming dark N trap, also comprise:
With the temperature of 1200 DEG C, 120 minutes are advanced to described dark N trap, reach the degree of depth of described dark N trap, and remove described pad oxide.
Because the N trap ion distribution directly injected is more concentrated, and be mostly positioned at the surface of substrate, can advance this dark N trap.When advancing dark N trap with the temperature of 1200 DEG C, the N-type ion injecting dark N trap adds fast diffusion due to the rising of temperature, when propelling 120 minutes, can reach its predetermined depth.The predetermined depth of dark N trap, for before starting to make, according to the depth value that the electrical parameter etc. of the CMOS that will make calculates.
The formation of dark N trap by first injecting N-type ion, then by advancing, can make N trap uniform ion diffuse to the predetermined degree of depth, thus the device parameters making the CMOS tube obtained can be made more stable.Because substrate surface is when injecting N-type ion and forming dark N trap, sustain damage formation defect, for ensureing the performance making the CMOS tube obtained, therefore needs pad oxide to remove.It should be noted that, the method for removal pad oxide layer can be wet etching.
The manufacture method that the present embodiment provides, ensureing that in the CMOS tube that making obtains, NMOS tube can connect on the basis of different bias voltage, making the performance of CMOS tube better by selecting specific substrate, the specifically method etc. of the dark N trap of formation.
Embodiment three
On the basis of above-described embodiment, the embodiment of the present invention three also provides a kind of manufacture method of CMOS tube.The present embodiment is specifically described by example.The flow chart of the manufacture method of the CMOS tube that Fig. 3 provides for the embodiment of the present invention three.The method, concrete steps are as follows:
Step 301, at substrate surface growth thickness be silicon dioxide, as the first pad oxide.
The substrate adopted in the present embodiment is the P type substrate of crystal orientation 100, resistivity 15-25 Ω .cm.Fig. 4 is the structural representation growing the first pad oxide in the embodiment of the present invention three.As shown in Figure 4, at the superficial growth thickness of substrate 401 be the first pad oxide 402.
Step 302, with the energy injection dosage of 100kev for 5E12/cm 2n-type ion, form dark N trap.
Fig. 5 is the structural representation forming dark N trap in the embodiment of the present invention three.At the upper surface of the first pad oxide 402 as shown in Figure 4 with the energy injection dosage of 100kev for 5E12/cm 2n-type ion, as phosphonium ion, form dark N trap 501 as shown in Figure 5 at the lower surface of the first pad oxide 402.
Step 303, with the temperature of 1200 DEG C, 120 minutes are advanced to dark N trap, reach predetermined depth, and remove the first pad oxide.
Fig. 6 is the structural representation after carrying out the propelling of dark N trap in the embodiment of the present invention three.Advance the dark N trap 501 shown in above-mentioned Fig. 5, to reach position as shown in Figure 6, make substrate 401 become substrate 601, dark N trap 501 becomes dark N trap 602.Outside the substrate 601 formed as shown in Figure 6 and dark N trap 602, also to remove the first pad oxide 402.
Step 304, growth thickness are silicon dioxide, as the second pad oxide, at the surface deposition thickness of the second pad oxide be silicon nitride, and light shield etching is carried out to active area, is formed with source region figure.
Wherein, active area refers to the region that can make active device, and the region that active area figure covers is the region that will make NMOS tube and PMOS.
Fig. 7 is the structural representation being formed with source region figure in the embodiment of the present invention three.At the superficial growth thickness of the device of making be as shown in Figure 6 silicon dioxide, at the surface deposition thickness of the first pad oxide be silicon nitride.The silicon dioxide layer of growth and silicon nitride layer are cover whole surface at first, by etching formation first source region figure 703 and the second active area figure 704 to the light shield of active area.When first active area 703 is the active area figure of NMOS tube, the second active area figure 704 is the active area figure of PMOS.Corresponding, when the first active area figure 703 is the active area figure of PMOS, the second active area figure 704 is the active area figure of NMOS tube.As shown in Figure 7, the first active area figure 703 comprises the structure of the second pad oxide 701 and silicon nitride layer 702, second active area figure 704 and the similar of the first active area figure 703, does not repeat them here.
Step 305, with the energy injection dosage of 330kev for 4.5E12/cm 2n-type ion, form N trap.
Fig. 8 is the structural representation forming N trap in the embodiment of the present invention three.As shown in Figure 8, at the upper surface of the device made as shown in Figure 7 with the energy injection dosage of 330kev for 4.5E12/cm 2n-type ion, as phosphonium ion, form N trap 802 as shown in Figure 8, dark N trap 602 becomes dark N trap 801.
Step 306, adopt light shield implantation dosage for 1.5E13/cm with the energy of 160kev 2p type ion, form P trap.
Fig. 9 is the structural representation forming P trap in the embodiment of the present invention three.Adopt light shield mask plate to hide the side of device as shown in Figure 8, in other side with the energy injection dosage of 110kev for 1.5E13/cm 2p type ion, as boron ion, form P trap 902, N trap N trap 802 as shown in Figure 8 as shown in Figure 9 and become N trap 901.
Step 307, the N trap of above-mentioned formation and P trap to be carried out to knot dark, and growth thickness is silicon dioxide, as field oxide, be formed with source region, and remove silicon nitride layer and the second pad oxide.
Figure 10 is the structural representation forming field oxide in the embodiment of the present invention three.Knot carries out to the N trap 901 shown in above-mentioned Fig. 9 and P trap 902 dark, to form N trap 1001 as shown in Figure 10 and P trap 1002.At outside and the interstitial growth silicon dioxide of the first active area figure 703 as shown in Figure 9 and the second active area figure 704, as field oxide 1003, and remove silicon nitride layer 702 and the second pad oxide 701.
Removing silicon nitride layer 702, such as, can be carry out wet etching removal by hot phosphoric acid, also can be that in the gases such as employing fluoroform, carbon tetrafluoride, sulphur hexafluoride, Nitrogen trifluoride, any one carries out dry etching.
Step 308, with the energy injection dosage of 60kev for 2.3E12/cm 2boron difluoride ion as the ion implantation of adjustment threshold voltage, and carry out P district light shield and to inject and P district compensates injection.
Because the molecular structure of boron difluoride ion is comparatively large, this ion of injection mainly concentrates on the top layer of N trap 1001 as shown in Figure 10 and P trap 1002.The injection of boron difluoride ion can make the conducting voltage of the PMOS made at N trap 1001 diminish; Corresponding, the injection of boron difluoride ion can make the conducting voltage of the NMOS tube made at P trap 1002 increase.Boron difluoride ion by injecting various dose makes the NMOS tube of the CMOS tube made and PMOS can have different threshold voltages.
Due to field oxide also adsorbable boron ion, also need to carry out light shield injection to P district, to supplement the P type ion of a part to P trap.P district carries out light shield injection, such as, can be that P trap 1002 as shown in Figure 10 above adopts light shield mask, and with energy 70kev implantation dosage for 3E12/cm 2inject boron ion.
For NMOS tube being the current lead-through realizing between source and drain by the migration of electronics.Because the migration velocity of electronics is very fast, for avoiding source-and-drain junction generation break-through, also need to compensate injection to P district.It can be such as after above-mentioned P district light shield injects that P district light shield injects, and continues with energy 180kev implantation dosage as 7E12/cm 2inject boron ion.
In order to remove damage and some particulates of surface of bottom material, and there is certain scattering process to the ion implantation of next step, namely reducing the impact of channelling effect.Before step 308, at least also comprise: growth thickness is silicon dioxide as sacrificial oxide layer.It should be noted that, owing to injecting the injection of boron difluoride ion and boron ion, make this sacrificial oxide layer there is doping, poor quality, therefore, after step 308, also needs to remove this sacrificial oxide layer.
Step 309, at the superficial growth thickness of active area be silicon dioxide, as grid oxic horizon, deposit thickness is polysilicon as grid polycrystalline silicon, deposition tungsten silicide, by photo etched mask etching technics, formed grid.
Figure 11 is the structural representation of the formation grid in the embodiment of the present invention three.Successively grow silicon dioxide layer, silicon nitride layer and tungsten silicide layer on the surface of P trap 1002 as shown in Figure 10 and N trap 1001, then by chemical wet etching, form the grid 1104 of NMOS tube as shown in figure 11 and the grid 1105 of PMOS.The grid 1104 of this NMOS tube and the grid 1105 of PMOS all have grid oxic horizon 1101, grid polycrystalline silicon 1102 and gate metal articulamentum 1103 as shown in figure 11.For ensureing that the metal connecting layer of grid better contacts with grid oxic horizon 1101, deposit spathic silicon 1102 between grid oxic horizon 1101 and gate metal articulamentum.This gate metal articulamentum 1103 is specially tungsten silicide, and tungsten silicide, as gate metal articulamentum, can reduce the resistance of the polysilicon of deposition.
It should be noted that, the deposition of polysilicon and tungsten silicide can be grown by the method for vapour deposition, and can be chemical vapour deposition (CVD), also start to be physical vapour deposition (PVD), the present invention be as limit.
Step 310, the N-type ion implantation of source-drain area of carrying out, adopt light shield to after source-drain area implanting p-type ion, also need the annealing carrying out source-drain area, form source-drain electrode.
Figure 12 is the structural representation forming source-drain electrode in the embodiment of the present invention.For avoiding hot carrier's effect, adopt the doping of gradual change type source and drain.The N-type ion implantation of source-drain area and the injection of P type ion can be that the light dope first carrying out N-type ion and P type ion injects, and under gate lateral wall deposition forms the protection of side wall, then the heavy doping carrying out N-type ion and P type ion is respectively injected.
Wherein, lightly doped N-type ion can be phosphonium ion, and its energy injected can be 60kev, and dosage is 2E13/cm 2; Lightly doped P type ion can be boron difluoride ion, and its energy injected is 55kev, and dosage is 3E13/cm 2.It is arsenic ion that source and drain injects heavily doped N-type ion, and its Implantation Energy can be 80kev, and dosage is 4E15/cm 2.It can be boron difluoride ion that source and drain injects heavily doped P type ion, and its energy injected is 55kev, and dosage is 2.5E15/cm 2.
Because the spreadability of silicon dioxide is better, it can be the side wall forming earth silicon material at gate lateral wall.
N-type ion and the P type ion of source-drain area have all injected complete, at least also need the annealing carrying out source-drain electrode.Can be heat 30 minutes at 800 DEG C to the annealing of source-drain electrode, to repair the lattice damage caused in ion implantation process, the source-drain electrode of ion implantation is electrically activated and spread simultaneously.
This step, on the basis of the device shown in above-mentioned Figure 11, forms the source electrode 1201 of NMOS tube as shown in figure 12, the drain electrode 1202 of NMOS tube, and the source electrode 1204 of PMOS, the drain electrode 1203 of PMOS.
Step 311, after the unadulterated silicon dioxide of the surface deposition of above-mentioned device, the silicon dioxide of dopant deposition, and adopt photo etched mask etching technics, forms fairlead graph layer.
Figure 13 is the structural representation forming fairlead graph layer in the embodiment of the present invention three.Unadulterated at the surface deposition of the device of above-mentioned steps making silicon dioxide, on this basis, the silicon dioxide of dopant deposition boron phosphorus adopt photo etched mask etching technics, source-drain layer is formed fairlead figure.The reduced reflux temperature of silicon dioxide layer doped with boron ion, Doping Phosphorus ion can reduce the membrane stress that follow-up making metal level and passivation layer etc. cause source and drain grid.
This step, on the basis of the device shown in above-mentioned Figure 12, forms fairlead graph layer 1301 as shown in fig. 13 that.
Step 312, carry out the sputtering of metal level on the surface of the device of above-mentioned making, adopt photo etched mask etching technics, form metal carbonyl conducting layer.
Figure 14 is the structural representation forming metal wiring layer in the embodiment of the present invention three.Carry out the sputtering of metal level on the surface of the device of above-mentioned steps making, this metal level comprises copper doped element silicon aluminium lamination and titanium nitride layer, form metal wiring layer 1401 as shown in figure 14.Dissolve each other for preventing sial and aluminium ELECTROMIGRATION PHENOMENON, doped silicon and copper in aluminium lamination, in the metal level of sputtering, included titanium nitride layer is antireflecting coating.
It should be noted that, splash-proofing sputtering metal layer at least also comprises before forming metal wiring layer in this step: the sputtering carrying out titanium and titanium nitride on the surface of the fairlead figure of above-mentioned steps making, and heat-treats.
In the sputtering of the surfaces nitrided titanium of the fairlead figure of above-mentioned steps making, for titanium nitride is because the contact of titanium nitride and silicon dioxide layer is bad, therefore before sputtering titanium nitride, also need sputtered titanium, the thickness of the titanium of sputtering can be for the titanium obtained for making sputtering better contacts with silicon with titanium nitride, and at temperature is 800 DEG C, the time of carrying out is the rapid thermal treatment of 20 seconds.
Step 313, the deposition of passivation layer of carrying out on the surface of the device of above-mentioned making, adopt photo etched mask etching technics, forms passivation layer figure, complete the making of CMOS tube.
Figure 15 is the structural representation of CMOS tube made in the embodiment of the present invention three.Carry out the deposition of passivation layer on the surface of the device of above-mentioned steps making, chemical wet etching forms deposit passivation layer 1501 as shown in figure 15.This passivation layer comprises silicon dioxide layer and silicon nitride.
For repairing the damage of the device inside that above-mentioned each manufacturing process causes, also need to carry out alloy technique to manufacturing the cmos device obtained, as heated 60 minutes at 425 DEG C.
Finally, also need to test the parameters of the CMOS tube made, when parameters all meets the requirements, completed the whole Making programme of CMOS tube.
Embodiment four
The embodiment of the present invention four also provides a kind of complementary metal oxide semiconductors (CMOS) CMOS tube, comprising: the PMOS made on N trap surface and the NMOS tube made on P trap surface, and described P trap is the P trap made on dark N trap surface; Described dark N trap is the N trap made at substrate surface;
Described N trap is the N trap made on described dark N trap surface.
The structural representation of the CMOS tube that Figure 16 provides for the embodiment of the present invention four.As shown in figure 16, this CMOS tube comprises substrate 1601, dark N trap 1602, N trap 1603, P trap 1604 and the NMOS tube 1605 made on P trap 1604, the PMOS 1606 made on N trap 1603, this NMOS tube 1605 comprise the source electrode 1607 of NMOS tube, the grid 1609 of the drain electrode 1608 of NMOS tube and NMOS tube.This PMOS 1606 comprises the grid 1611 of the source electrode 1612 of PMOS, the drain electrode 1610 of PMOS and PMOS.
The manufacture method of the CMOS tube that the CMOS tube of the embodiment of the present invention can adopt the embodiment of the present invention to provide is to make formation.Owing to having dark N trap between the P trap of NMOS tube in this CMOS tube and substrate, and become the NMOS tube of suspension, the underlayer voltage of this suspension NMOS tube can access different voltage respectively by P trap and substrate, and the threshold voltage therefore during this NMOS tube conducting is just different bias voltage, improves the flexibility of circuit.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (6)

1. a manufacture method for complementary metal oxide semiconductors (CMOS) CMOS tube, is included in N trap surperficial making PMOS, in P trap surperficial making NMOS tube, it is characterized in that, described in N trap surface making PMOS, before P trap surperficial making NMOS tube, also comprises:
Inject N-type ion at substrate surface, form dark N trap;
Described N trap and described P trap is made on described dark N trap surface.
2. method according to claim 1, is characterized in that, described substrate is P type substrate; The crystal orientation of described substrate is 100, and resistivity is 15-25 Ω .cm.
3. method according to claim 1, is characterized in that, described N-type ion is phosphonium ion; The energy of described injection N-type ion is 100kev, and dosage is 5E12/cm 2.
4. method according to claim 1, is characterized in that, described at substrate surface injection N-type ion, before forming dark N trap, also comprises:
At described substrate surface growth pad oxide, the thickness of described pad oxide is
5. method according to claim 4, is characterized in that, described at substrate surface injection N-type ion, after forming dark N trap, also comprises:
With the temperature of 1200 DEG C, 120 minutes are advanced to described dark N trap, reach predetermined depth, and remove described pad oxide.
6. a complementary metal oxide semiconductors (CMOS) CMOS tube, comprising: the PMOS made on N trap surface and the NMOS tube made on P trap surface, is characterized in that,
Described P trap is the P trap made on dark N trap surface; Described dark N trap is the N trap made at substrate surface;
Described N trap is the N trap made on described dark N trap surface.
CN201310381820.5A 2013-08-28 2013-08-28 Manufacture method of CMOS tube, and CMOS tube Pending CN104425376A (en)

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CN113380787A (en) * 2021-08-13 2021-09-10 上海维安半导体有限公司 Bidirectional transient voltage suppression device and preparation method thereof

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CN1617353A (en) * 2003-11-14 2005-05-18 株式会社瑞萨科技 Method of manufacturing a semiconductor device
CN101258603A (en) * 2005-05-25 2008-09-03 梅尔斯科技公司 Semiconductor device including a superlattice having at least one group of substantially undoped layer
CN104051343A (en) * 2013-03-14 2014-09-17 德克萨斯仪器股份有限公司 Transistor with deep N-well implanted through the gate

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Publication number Priority date Publication date Assignee Title
US5929493A (en) * 1998-03-31 1999-07-27 Texas Instruments--Acer Incorporated CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
CN1617353A (en) * 2003-11-14 2005-05-18 株式会社瑞萨科技 Method of manufacturing a semiconductor device
CN101258603A (en) * 2005-05-25 2008-09-03 梅尔斯科技公司 Semiconductor device including a superlattice having at least one group of substantially undoped layer
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380787A (en) * 2021-08-13 2021-09-10 上海维安半导体有限公司 Bidirectional transient voltage suppression device and preparation method thereof
CN113380787B (en) * 2021-08-13 2022-02-25 上海维安半导体有限公司 Bidirectional transient voltage suppression device and preparation method thereof

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Application publication date: 20150318