CN104425370B - A kind of semiconductor devices and its manufacture method - Google Patents
A kind of semiconductor devices and its manufacture method Download PDFInfo
- Publication number
- CN104425370B CN104425370B CN201310379938.4A CN201310379938A CN104425370B CN 104425370 B CN104425370 B CN 104425370B CN 201310379938 A CN201310379938 A CN 201310379938A CN 104425370 B CN104425370 B CN 104425370B
- Authority
- CN
- China
- Prior art keywords
- threshold voltage
- type
- layer
- dielectric layer
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 97
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 17
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical group [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 10
- 229910021324 titanium aluminide Inorganic materials 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000006902 nitrogenation reaction Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 171
- 239000000463 material Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910010038 TiAl Inorganic materials 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, is related to technical field of semiconductors.This method includes：S101：Being formed on a semiconductor substrate includes the front-end devices of dummy grid oxide layer, dummy grid and gate lateral wall, removes dummy grid oxide layer and dummy grid；S102：Boundary layer and high k dielectric layer are formed between gate lateral wall；S103：The high k dielectric layer in the region for being pointed to intend to form p-type high threshold voltage transistors and N-type low threshold voltage transistor carries out nitrogen treatment；S104：Post-nitridation anneal technique is carried out to front-end devices；S105：Metal gates are formed in high k dielectric layer.This method introduces nitrogen by nitrogenation treatment technology in the high k dielectric layer of N-type low threshold voltage transistor and p-type high threshold voltage transistors, can effectively realize the regulation to transistor threshold voltage.The semiconductor devices of the present invention is because the high k dielectric layer of N-type low threshold voltage transistor and p-type high threshold voltage transistors is doped with nitrogen, with good threshold voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method.
Background technology
In technical field of semiconductors, how reduction power consumption has become people while the performance of semiconductor devices is ensured
A significant challenge facing.Power consumption/performance optimization（Power-performance optimization）Usually require that half
Conductor device has multiple threshold voltages（Vt）With low cut-off current（Ioff）.In plane body silicon semiconductor device, pass through
Use two work-function layers（N type field effect transistor NFET and p type field effect transistor PFET is corresponded to respectively）And using not
With grid length and doping concentration realize multi-Vt.Fin FET（FinFET）It is small due to that can realize
Device size, there is outstanding static control ability using small operating voltage, however, device size and operating voltage
Reduce, the especially reduction of operating voltage causes the control to threshold voltage changeability to become very difficult.In large-scale application fin
Type field-effect transistor（FinFET）Semiconductor devices in, as process node constantly reduces, it is necessary to the number of the ion injected
Amount is constantly reduced（Need the amount of ions injected considerably less for example with the device of 10nm process nodes）, ion implantation technology change
Control must be very difficult to.
Pass through block technique（capping）The method of adjusting threshold voltage can effectively adjust fin FET
Threshold voltage, but this method needs complicated integrated technique and will not bring otherwise lifting.And it is traditional from
Sub- injection technology can reduce the ionic mobility of device, and may result in influences very bad dopant random device
Fluctuation.Also, for the manufacture method using the semiconductor devices of metal gate technique, ion implantation technology is also faced with control
Ion implantation dosage processed is to prevent ion from infiltrating through the challenge of the channel region of high k dielectric layer or device.
It can be seen that, good threshold voltage how is obtained, is the manufacturer of the semiconductor devices of high k dielectric layer process after applying
The problem of method has to solve.To solve the above problems, being necessary to propose a kind of new semiconductor devices and its manufacture method.
The content of the invention
The embodiment of the present invention one provides a kind of manufacture method of semiconductor devices, and this method includes：
Step S101：Being formed on a semiconductor substrate includes gate lateral wall and the pseudo- grid between the gate lateral wall
Pole oxide layer and dummy grid, remove the dummy grid oxide layer and the dummy grid；
Step S102：Boundary layer and the high k dielectric layer on the boundary layer are formed between the gate lateral wall；
Step S103：The high k dielectric layer in the region for being pointed to intend to form N-type low threshold voltage transistor and positioned at intending being formed
The high k dielectric layer in the region of p-type high threshold voltage transistors carries out nitrogen treatment；
Step S104：Post-nitridation anneal technique is carried out to the front-end devices；
Step S105：Metal gates are formed in the high k dielectric layer.
Wherein, wherein, in the step S101, before the front-end devices are formed, have in the Semiconductor substrate
There is fin structure.The fin structure is distributed in the plan and forms the region of N-type low threshold voltage transistor, intends forming the high threshold of N-type
The region of threshold voltage transistor, the region for intending being formed p-type low threshold voltage transistor and plan form p-type high threshold voltage transistors
Region so that transistor in the semiconductor devices ultimately formed is fin FET.
Wherein, the step S103 includes：
Step S1031：Region and plan that covering intends being formed N-type high threshold voltage transistors are formed on the front-end devices
Form the shielding layer in the region of p-type low threshold voltage transistor；
Step S1032：The high k dielectric layer in the region for being pointed to intend to form N-type low threshold voltage transistor and positioned at intending shape
High k dielectric layer into the region of p-type high threshold voltage transistors carries out nitrogen treatment.
Wherein, in the step S103, the method that the nitrogen treatment is used is decoupled plasma nitridation.
Wherein, it is described to form N-type low-threshold power piezocrystal positioned at plan by the nitrogen treatment in the step S103
The high k dielectric layer in the region of body pipe and the high k dielectric layer for being located at the region for intending forming p-type high threshold voltage transistors are incorporated
It is miscellaneous enter positivity nitrogen.
Wherein, step S1045 is also included between the step S104 and the step S105：
The work content of cap, barrier layer and work-function layer, wherein N-type transistor is sequentially formed in the high k dielectric layer
Several layers different from the work-function layer of P-type transistor.
Wherein, the cap is titanium nitride, and the barrier layer is tantalum nitride, and the work-function layer of the N-type transistor is
Titanium aluminide, the work-function layer of the P-type transistor is titanium nitride and the double-decker of titanium aluminide composition.
The embodiment of the present invention two provides a kind of semiconductor devices, and it includes：Semiconductor substrate and positioned at the semiconductor
N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor and the high threshold of p-type on substrate
Threshold voltage transistor, also, the N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low-threshold power piezocrystal
Body pipe and p-type high threshold voltage transistors include：Gate lateral wall and the stacking from bottom to top between the gate lateral wall
Boundary layer, high k dielectric layer and metal gates；
Wherein, the high k of the high k dielectric layer of the N-type low threshold voltage transistor and the p-type high threshold voltage transistors
Dielectric layer is the high k dielectric layer doped with nitrogen.
Wherein, it is fin effect to have the transistor in fin structure, the semiconductor devices in the Semiconductor substrate
Answer transistor.
Wherein, in the N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage crystal
Also include the block being laminated from bottom to top in pipe and p-type high threshold voltage transistors, between the high k dielectric layer and metal gates
Layer, barrier layer and work-function layer, also, the work-function layer of N-type transistor and the work-function layer of P-type transistor are different.
The manufacture method of the semiconductor devices of the present invention, the manufacture method of the semiconductor devices of the present embodiment, by using
Nitrogenation treatment technology introduces nitrogen member in the high k dielectric layer of N-type low threshold voltage transistor and p-type high threshold voltage transistors
Element, effectively the threshold voltage of transistor can be adjusted, obtained semiconductor devices has good threshold voltage.Phase
For threshold voltage adjustment method of the prior art, this method has the advantages that technique is simple, is easily achieved.The half of the present invention
Conductor device, because the high k dielectric layer of N-type low threshold voltage transistor and p-type high threshold voltage transistors is doped with nitrogen member
The high k dielectric layer of element, thus the threshold voltage adjustments to transistor can be effectively realized, it is special with good threshold voltage
Property.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A to Fig. 1 E is a kind of correlation step formation of the manufacture method of semiconductor devices of the embodiment of the present invention one
The schematic cross sectional views of structure；
Fig. 2 is a kind of a kind of typicalness flow chart of the manufacture method of semiconductor devices of the embodiment of the present invention one；
Fig. 3 is a kind of a kind of schematic cross sectional views of the structure of semiconductor devices of the embodiment of the present invention two.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Although it should be understood that can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., can describe for convenience herein and by using so as to the element or feature shown in description figure with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.If for example, the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or it
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, " one " and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determine the feature, it is whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Hair is described herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to the change caused by such as manufacturing technology and/or tolerance from shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain semiconductor devices proposed by the present invention and its manufacture method.Presently preferred embodiments of the present invention is described in detail as follows, but is removed
These are described in detail outer, and the present invention can also have other embodiment.
Embodiment one
The embodiment of the present invention provides a kind of manufacture method of semiconductor devices, and this method is by using nitrogen treatment（Typically
For DPN）Technique introduces nitrogen in the high k dielectric layer of N-type low threshold voltage transistor and p-type high threshold voltage transistors,
The regulation to the threshold voltage of transistor is realized, the semiconductor devices with multi-Vt can be better achieved.
Below, reference picture 1A to Fig. 1 E and Fig. 2 describes a kind of semiconductor devices of the proposition of the embodiment of the present invention one
Manufacture method.Wherein, Figure 1A to Fig. 1 E is a kind of correlation step shape of the manufacture method of semiconductor devices of the embodiment of the present invention
Into structure schematic cross sectional views；Fig. 2 is typical for a kind of one kind of the manufacture method of semiconductor devices of the embodiment of the present invention
Property flow chart.
The manufacture method of the semiconductor devices of the embodiment of the present invention, comprises the following steps：
Step A1：Being formed on a semiconductor substrate includes gate lateral wall and the dummy grid between the gate lateral wall
The front-end devices of oxide layer and dummy grid, remove the dummy grid and the dummy grid oxide layer.
Specifically there is provided Semiconductor substrate 100, plan on a semiconductor substrate 100 forms N-type low threshold voltage transistor
（NLVT）Region, intend form N-type high threshold voltage transistors（NHVT）Region, intend form p-type low threshold voltage transistor
（PLVT）Region and plan form p-type high threshold voltage transistors（PHVT）Region form gate lateral wall respectively and positioned at grid
The components such as dummy grid oxide layer and dummy grid between the wall of pole side（That is, front-end devices are formd on a semiconductor substrate 100）, so
The dummy grid and the dummy grid oxide layer positioned at above-mentioned regional are removed afterwards, are only retained and are formed the low threshold of N-type positioned at plan
The gate lateral wall 1011 in the region of threshold voltage transistor, the gate electrode side positioned at the region for intending being formed N-type high threshold voltage transistors
Wall 1021, positioned at intend formed p-type low threshold voltage transistor region gate lateral wall 1031 and positioned at intend form p-type high threshold
The gate lateral wall 1041 in the region of voltage transistor, as shown in Figure 1A.Certainly, the front-end devices can also include well region, shallow ridges
Groove isolation, lightly doped district（LDD）, source electrode and drain electrode, interlayer dielectric layer, the component such as skew side wall, this is not limited herein
It is fixed.
In this embodiment, it is preferred that, before the front-end devices are formed, it is formed with the Semiconductor substrate 100
Fin structure（Not shown in Figure 1A）.The fin structure is distributed in the plan and forms the region of N-type low threshold voltage transistor, intends
The region of formation N-type high threshold voltage transistors, the region for intending being formed p-type low threshold voltage transistor and plan form the high threshold of p-type
The region of threshold voltage transistor.Due to having fin structure in Semiconductor substrate 100, it is ensured that the semiconductor device finally manufactured
Transistor in part（Including N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor
With p-type high threshold voltage transistors）For fin FET.In fact, because Figure 1A is cuing open along grid width direction
Face figure, and fin structure can just be seen typically in the sectional view along grid length direction, therefore do not shown in Figure 1A
Fin structure.In the present embodiment, each transistor is preferably fin FET（Fin FET）.
Wherein, the material of the dummy grid oxide layer of formation is generally silica, and the material of the dummy grid of formation is generally many
Crystal silicon.Regional（That is, intend forming the region of N-type low threshold voltage transistor, intend forming N-type high threshold voltage transistors
Region, plan form the region of p-type low threshold voltage transistor and plan forms the region of p-type high threshold voltage transistors）Pseudo- grid
Pole oxide layer is general to be formed in same technique, and the dummy grid of regional is general also to be formed in same technique.
In step A1, it can also typically include：The step of forming well region, the step of forming skew side wall layer is carried out light
Doping（LDD）The step of, the step of source electrode and drain electrode is formed, the step of forming interlayer dielectric layer carries out stress and close on technology
Step etc..Above steps, can be realized, here is omitted using existing various techniques.
Step A2：Boundary layer is formed between the gate lateral wall（ILD）With the high k dielectric layer on boundary layer.
Specifically, boundary is formed between the gate lateral wall 1011 positioned at the region for intending forming N-type low threshold voltage transistor
Surface layer 1012 and high k dielectric layer 1013 disposed thereon, in the grid positioned at the region for intending being formed N-type high threshold voltage transistors
Boundary layer 1022 and high k dielectric layer 1023 disposed thereon are formed between side wall 1021, p-type low threshold voltage is being formed positioned at plan
Boundary layer 1032 and high k dielectric layer 1033 disposed thereon are formed between the gate lateral wall 1031 in the region of transistor, positioned at
Boundary layer 1042 and height disposed thereon are formed between the gate lateral wall 1041 in the region that plan forms p-type high threshold voltage transistors
K dielectric layer 1043, as shown in Figure 1B.Obviously, high k dielectric layer is less than gate lateral wall.It will be understood to those skilled in the art that
In the present embodiment, boundary layer and the high k dielectric layer on boundary layer are formed between gate lateral wall, wherein, " gate lateral wall
Between " refer between two gate lateral walls of a corresponding transistor.
In the present embodiment, boundary layer 1012,1022,1032 and 1042 is general forms in same technique, high k dielectric layer
1013rd, 1023, the 1033 and 1043 general formation in same technique.Wherein, high k dielectric layer 1013,1023,1033 and 1043
Section is preferably U-shaped, as shown in Figure 1B.The section of high k dielectric layer is U-shaped, can increase it with being positioned above and lower section
The contact area of film layer, improves the performance of transistor.
Step A3：It is pointed to plan and forms p-type high threshold voltage transistors（PHVT）Region and plan form N-type low-threshold power
Piezoelectric crystal（NLVT）Region high k dielectric layer carry out nitrogen treatment.
Wherein, exemplarily, the region and plan for being pointed to intend to form p-type high threshold voltage transistors form N-type Low threshold
The high k dielectric layer in the region of voltage transistor（I.e. high k dielectric layer 1013 and 1043）The method for carrying out nitrogen treatment, specifically can be with
Comprise the following steps：
Step A31：Covering plan is formed on front-end devices and forms p-type low threshold voltage transistor（PLVT）Region and plan
Form N-type high threshold voltage transistors（NHVT）Region shielding layer 200；
Step A32：The region and plan for being pointed to intend to form p-type high threshold voltage transistors form N-type low-threshold power piezocrystal
The high k dielectric layer in the region of body pipe（I.e. high k dielectric layer 1013 and 1043）Carry out nitrogen treatment.By nitrogen treatment, high k dielectric
Layer 1013 and 1043 has been injected into nitrogen, and high k dielectric is denoted as respectively by the high k dielectric layer 1013 and 1043 of nitrogen treatment
Layer 1013 ' and 1043 ', as shown in Figure 1 C.
Wherein, step A31 purpose is：Protection intends being formed the region of p-type low threshold voltage transistor and plan forms N-type
The region of high threshold voltage transistors is from the influence of nitrogen treatment, and especially, protection forms p-type low-threshold power piezocrystal positioned at plan
The region of body pipe and plan form the high k dielectric layer in the region of N-type high threshold voltage transistors（I.e. high k dielectric layer 1023 and 1033）
From the influence of nitrogen treatment.Exemplarily, photoresist layer can be used as shielding layer and form p-type low-threshold power to block plan
The region of piezoelectric crystal and plan form the region of N-type high threshold voltage transistors, as shown in Figure 1 C.
In the present embodiment, the region and plan for being pointed to intend to form p-type high threshold voltage transistors form N-type low-threshold power
The high k dielectric layer in the region of piezoelectric crystal（I.e. high k dielectric layer 1013 and 1043）The method for carrying out nitrogen treatment, can use and go
Coupling pecvd nitride (decoupled plasma nitration；DPN) method or other suitable methods.Enter when using DPN
During row nitrogen treatment, processing time is preferably -180 seconds 10 seconds, to obtain more preferable nitriding result.
, can be nitrogen by nitrogen treatment（Abbreviation nitrogen）It is incorporated into and forms p-type high threshold voltage transistors positioned at plan
Region high k dielectric layer（I.e. high k dielectric layer 1043）With the high k dielectric in the region for intending being formed N-type low threshold voltage transistor
Layer（I.e. high k dielectric layer 1013）Among, i.e. in the high k dielectric layer positioned at the region for intending being formed p-type high threshold voltage transistors
（I.e. high k dielectric layer 1043）With the high k dielectric layer in the region for intending being formed N-type low threshold voltage transistor（I.e. high k dielectric layer
1013）Middle formation N doping, the N doping can realize the p-type high threshold voltage transistors and N-type Low threshold to ultimately forming
The regulation of the threshold voltage of voltage transistor.In general, the nitrogen injected by nitrogen treatment carries positive charge（What is adulterated is
The nitrogen of positivity）.The nitrogen of positively charged is injected into p-type high threshold voltage transistors and the high k of N-type low threshold voltage transistor is situated between
After in electric layer, the effect for the threshold voltage for adjusting corresponding transistor can be reached.This method is by nitrogenation treatment technology in N
Nitrogen is introduced in the high k dielectric layer of type low threshold voltage transistor and p-type high threshold voltage transistors, can be effectively to transistor
Threshold voltage be adjusted, relative to threshold voltage adjustment method of the prior art, with technique it is simple, be easily achieved
Advantage.
Step A4：Post-nitridation anneal is carried out to the front-end devices.
By post-nitridation anneal, N-type low-threshold power is formed positioned at the region and plan for intending being formed p-type high threshold voltage transistors
The high k dielectric layer of the process nitrogen treatment in the region of piezoelectric crystal（I.e. high k dielectric layer 1013 ' and 1043 '）High k is respectively become
Dielectric layer 1013 " and 1043 ", as shown in figure iD.
Wherein, the main function of post-nitridation anneal technique is to repair nitrogen treatment（Such as DPN）Caused to front-end devices
Infringement.In addition, post-nitridation anneal technique can also improve high k dielectric layer and the quality of boundary layer to a certain extent, especially
Can be by improving the high k dielectric layer by nitrogen treatment（I.e. high k dielectric layer 1013 ' and 1043 '）In nitrogen residing for
Position（Nitrogen is set further to be deep among high k dielectric layer）Improve the conductive characteristic of the high k dielectric layer by nitrogen treatment.
In the present embodiment, the method for post-nitridation anneal, can use various method for annealing of the prior art, such as swash
Photo-thermal annealing etc., is not defined herein.
Step A5：Metal gates are formed on high k dielectric layer.
Specifically, gold is formed in the high k dielectric layer 1013 " positioned at the region for intending forming N-type low threshold voltage transistor
Belong to grid 1014, metal gates are formed in the high k dielectric layer 1023 positioned at the region for intending forming N-type high threshold voltage transistors
1024, metal gates 1034 are formed in the high k dielectric layer 1033 positioned at the region for intending forming p-type low threshold voltage transistor,
Metal gates 1044 are formed in the high k dielectric layer 1043 " positioned at the region for intending forming p-type high threshold voltage transistors, are such as schemed
Shown in 1E.
In the present embodiment, step A45 can also be included between step A4 and step A5：On high k dielectric layer according to
Secondary formation cap（cap layer）, barrier layer（barrier layer）, and NMOS and PMOS work-function layer is formed respectively.
Wherein, each transistor of formation（Including N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type
Low threshold voltage transistor and p-type high threshold voltage transistors）Cap（cap layer）Identical material can be used,
Barrier layer（barrier layer）Identical material can also be used；But, NMOS work-function layer and PMOS work-function layer
Typically use different materials.Exemplary, cap（cap layer）Using titanium nitride（TiN）Or other have similitude
The material of matter, barrier layer（barrier layer）Using tantalum nitride（TaN）Or other have the material of similar quality, N-type crystal
Pipe（Including N-type low threshold voltage transistor and N-type high threshold voltage transistors）Work-function layer use titanium aluminide（TiAl）'s
Single layer structure；P-type transistor（Including p-type low threshold voltage transistor and p-type high threshold voltage transistors）Work-function layer adopt
Use titanium nitride（TiN）And titanium aluminide（TiAl）Double-decker, wherein titanium nitride（TiN）Positioned at titanium aluminide（TiAl）Lower section.
Further, the cap of each transistor, barrier layer, the section of work-function layer are preferably U-shape structure, to increase and its top
With the contact area of the film layer of lower section, the performance of transistor is improved.
So far, a kind of introduction of the committed step of the manufacture method of semiconductor devices of the embodiment of the present invention is completed.Connect
Get off to be referred to technological process of the prior art to complete the manufacture of whole semiconductor devices, on subsequent step, herein
Repeat no more.
The manufacture method of the semiconductor devices of the present embodiment, by using nitrogenation treatment technology in N-type low-threshold power piezocrystal
Nitrogen is introduced in the high k dielectric layer of body pipe and p-type high threshold voltage transistors, threshold voltage that can effectively to transistor
It is adjusted.Relative to threshold voltage adjustment method of the prior art（For example pass through the side of ion implanting adjusting threshold voltage
Method）, the step of method of the present embodiment does not need ion implanting have the advantages that technique is simple, be easily achieved.
Fig. 2 shows a kind of a kind of typical flowchart of the manufacture method of semiconductor devices proposed by the present invention, specific bag
Include：
Step S101：Being formed on a semiconductor substrate includes gate lateral wall and the pseudo- grid between the gate lateral wall
The front-end devices of pole oxide layer and dummy grid, remove the dummy grid and the dummy grid oxide layer；
Step S102：Boundary layer and the high k dielectric layer on the boundary layer are formed between the gate lateral wall；
Step S103：The high k dielectric layer in the region for being pointed to intend to form N-type low threshold voltage transistor and positioned at intending being formed
The high k dielectric layer in the region of p-type high threshold voltage transistors carries out nitrogen treatment；
Step S104：Post-nitridation anneal technique is carried out to the front-end devices；
Step S105：Metal gates are formed in the high k dielectric layer.
Embodiment two
The embodiment of the present invention provides a kind of semiconductor devices, can use the manufacture of the semiconductor devices of above-described embodiment one
It is prepared by method.
The semiconductor devices of the present embodiment, its included N-type low threshold voltage transistor and p-type high threshold voltage transistors
High k dielectric layer be high k dielectric layer doped with nitrogen, thus can effectively realize to the threshold voltage of transistor tune
Section, with good threshold voltage characteristic.
Below, reference picture 3 come describe the embodiment of the present invention two proposition a kind of semiconductor devices structure.Wherein, Fig. 3 is
A kind of a kind of schematic cross sectional views of the structure of semiconductor devices of the embodiment of the present invention.
As shown in figure 3, the semiconductor devices of the present embodiment includes：Semiconductor substrate 100 and positioned at Semiconductor substrate 100
On N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor and p-type high threshold electricity
Piezoelectric crystal.Wherein, N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor and P
Type high threshold voltage transistors include：Gate lateral wall and the boundary stacked gradually from bottom to top between the gate lateral wall
Surface layer, high k dielectric layer and metal gates.Specifically, N-type low threshold voltage transistor includes being located in Semiconductor substrate 100
Gate lateral wall 1011 and the boundary layer 1012 stacked gradually from bottom to top between gate lateral wall 1011, high k dielectric layer
1013 " and metal gates 1014；N-type high threshold voltage transistors include the gate lateral wall 1021 being located in Semiconductor substrate 100
And the boundary layer 1022 stacked gradually from bottom to top, high k dielectric layer 1023 and metal gate between gate lateral wall 1021
Pole 1024；P-type low threshold voltage transistor includes the gate lateral wall 1031 being located in Semiconductor substrate 100 and positioned at gate electrode side
The boundary layer 1032 stacked gradually from bottom to top, high k dielectric layer 1033 and metal gates 1034 between wall 1031；The high threshold of p-type
Threshold voltage transistor include be located at Semiconductor substrate 100 on gate lateral wall 1041 and between gate lateral wall 1041 from
Boundary layer 1042, high k dielectric layer 1043 " and the metal gates 1044 stacked gradually on down.Wherein, N-type low-threshold power piezocrystal
The high k dielectric layer 1013 " of body pipe and the high k dielectric layer 1043 " of p-type high threshold voltage transistors are the high k doped with nitrogen
Dielectric layer.
Wherein it is preferred to, it is formed with fin structure in Semiconductor substrate 100（Not shown in Fig. 3）.The fin structure is distributed
It is described intend formed N-type low threshold voltage transistor region, intend formed N-type high threshold voltage transistors region, intend form P
The region of type low threshold voltage transistor and plan form the region of p-type high threshold voltage transistors.Due in Semiconductor substrate 100
With fin structure, it is ensured that the transistor in the semiconductor devices finally manufactured（Including N-type low threshold voltage transistor, N
Type high threshold voltage transistors, p-type low threshold voltage transistor and p-type high threshold voltage transistors）For fin field effect crystal
Pipe.In fact, because Fig. 3 is the profile along grid width direction, and fin structure is general in cuing open along grid length direction
It can just be seen in view, therefore not show fin structure in Fig. 3.
Further, in the present embodiment, it is low in N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type
Among threshold voltage transistors and p-type high threshold voltage transistors, it can also include between high k dielectric layer and metal gates under
And on the cap, barrier layer and the work-function layer that stack gradually（Not shown in Fig. 3）.Exemplary, cap（cap layer）
Using titanium nitride（TiN）Or other have the material of similar quality, barrier layer（barrier layer）Using tantalum nitride（TaN）
Or other have the material of similar quality.Wherein it is preferred to, N-type transistor（It is high including N-type low threshold voltage transistor and N-type
Threshold voltage transistors）Work-function layer and P-type transistor（It is brilliant including p-type low threshold voltage transistor and p-type high threshold voltage
Body pipe）Work-function layer it is different.Exemplary, N-type transistor（Including N-type low threshold voltage transistor and N-type high threshold voltage
Transistor）Work-function layer use titanium aluminide（TiAl）Single layer structure；P-type transistor（Including p-type low threshold voltage transistor
With p-type high threshold voltage transistors）Work-function layer use titanium nitride（TiN）And titanium aluminide（TiAl）Double-decker, wherein
Titanium nitride（TiN）Positioned at titanium aluminide（TiAl）Lower section.
Further, more than one of the high k dielectric layer of each transistor, cap, barrier layer, work-function layer cutting
Face is U-shaped, to increase the contact area with the film layer above and below it, improves the performance of transistor.
The semiconductor devices of the embodiment of the present invention, can also include well region, skew side wall, be lightly doped（LDD）Area, source electrode and
The components such as drain electrode, interlayer dielectric layer, these components can be realized using various methods of the prior art, no longer be gone to live in the household of one's in-laws on getting married herein
State.
The semiconductor devices of the present invention, due to the high k of N-type low threshold voltage transistor and p-type high threshold voltage transistors
Dielectric layer is the high k dielectric layer doped with nitrogen, thus can effectively realize the threshold voltage adjustments to transistor, is had
Good threshold voltage characteristic.Also, when transistor is fin FET, the semiconductor devices is relative to existing skill
Art, with more preferable threshold voltage characteristic.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Step S101：Being formed on a semiconductor substrate includes gate lateral wall and the dummy grid oxygen between the gate lateral wall
Change the front-end devices of layer and dummy grid, remove the dummy grid and the dummy grid oxide layer；
Step S102：Boundary layer and the high k dielectric layer on the boundary layer are formed between the gate lateral wall, it is described
High k dielectric layer is U-shaped；
Step S103：The high k dielectric layer in the region for being pointed to intend to form N-type low threshold voltage transistor and positioned at intending forming p-type
The high k dielectric layer in the region of high threshold voltage transistors carries out nitrogen treatment；
Step S104：Post-nitridation anneal technique is carried out to the front-end devices；
Step S105：Metal gates are formed in the high k dielectric layer.
2. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that in the step S101, in shape
Into before the front-end devices, fin structure is formed with the Semiconductor substrate.
3. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the step S103 includes：
Step S1031：Covering is formed on the front-end devices to intend being formed the region of N-type high threshold voltage transistors and intend being formed
The shielding layer in the region of p-type low threshold voltage transistor；
Step S1032：The high k dielectric layer in the region for being pointed to intend to form N-type low threshold voltage transistor and positioned at intending forming p-type
The high k dielectric layer in the region of high threshold voltage transistors carries out nitrogen treatment.
4. the manufacture method of the semiconductor devices as described in any one of claims 1 to 3, it is characterised in that in the step
In S103, the method that the nitrogen treatment is used is decoupled plasma nitridation.
5. the manufacture method of the semiconductor devices as described in any one of claims 1 to 3, it is characterised in that in the step
In S103, by the nitrogen treatment, it is described be located at intend formed N-type low threshold voltage transistor region high k dielectric layer and
The high k dielectric layer for being located at the region for intending forming p-type high threshold voltage transistors is doped into the nitrogen of positivity.
6. the manufacture method of the semiconductor devices as described in any one of claims 1 to 3, it is characterised in that in the step
Also include step S1045 between S104 and the step S105：
The work-function layer of cap, barrier layer and work-function layer, wherein N-type transistor is sequentially formed in the high k dielectric layer
It is different from the work-function layer of P-type transistor.
7. the manufacture method of semiconductor devices as claimed in claim 6, it is characterised in that the cap is titanium nitride, institute
Barrier layer is stated for tantalum nitride, the work-function layer of the N-type transistor is titanium aluminide, and the work-function layer of the P-type transistor is nitrogen
Change the double-decker that titanium and titanium aluminide are constituted.
8. a kind of semiconductor devices, it is characterised in that including：Semiconductor substrate and the N-type in the Semiconductor substrate
Low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor and p-type high threshold voltage crystal
Pipe, the N-type low threshold voltage transistor, N-type high threshold voltage transistors, p-type low threshold voltage transistor and p-type high threshold
Voltage transistor includes：Gate lateral wall and the boundary layer being laminated from bottom to top, high k between the gate lateral wall are situated between
Electric layer and metal gates；
Wherein, the high k dielectric of the high k dielectric layer of the N-type low threshold voltage transistor and the p-type high threshold voltage transistors
Layer is the high k dielectric layer doped with nitrogen, and the high k dielectric layer is U-shaped.
9. semiconductor devices as claimed in claim 8, it is characterised in that there is fin structure, institute in the Semiconductor substrate
It is fin FET to state the transistor in semiconductor devices.
10. semiconductor devices as claimed in claim 8 or 9, it is characterised in that in the N-type low threshold voltage transistor, N
In type high threshold voltage transistors, p-type low threshold voltage transistor and p-type high threshold voltage transistors, the high k dielectric layer and
Also include the work function of cap, barrier layer and work-function layer, wherein N-type transistor being laminated from bottom to top between metal gates
Layer is different from the work-function layer of P-type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310379938.4A CN104425370B (en) | 2013-08-27 | 2013-08-27 | A kind of semiconductor devices and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310379938.4A CN104425370B (en) | 2013-08-27 | 2013-08-27 | A kind of semiconductor devices and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104425370A CN104425370A (en) | 2015-03-18 |
| CN104425370B true CN104425370B (en) | 2017-10-20 |
Family
ID=52974008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310379938.4A Active CN104425370B (en) | 2013-08-27 | 2013-08-27 | A kind of semiconductor devices and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104425370B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298506A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and forming method |
| CN108346577B (en) * | 2017-01-22 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
| CN107464783B (en) * | 2017-08-22 | 2020-01-31 | 中国科学院微电子研究所 | CMOS devices and manufacturing method thereof |
| CN107564864B (en) * | 2017-08-22 | 2020-03-31 | 中国科学院微电子研究所 | CMOS device and manufacturing method thereof |
| CN110164878B (en) * | 2019-06-10 | 2022-05-03 | 惠科股份有限公司 | Array substrate and preparation method thereof |
| CN113468845A (en) * | 2020-03-31 | 2021-10-01 | 中芯国际集成电路制造(上海)有限公司 | Process manufacturing method, threshold voltage adjusting method, device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747850A (en) * | 1994-04-08 | 1998-05-05 | Texas Instruments Incorporated | Extended drain resurf lateral DMOS devices |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN102800631A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming complementary metal oxide semiconductor (CMOS) transistor |
| CN103094214A (en) * | 2011-11-04 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103258823A (en) * | 2012-02-16 | 2013-08-21 | 国际商业机器公司 | Semiconductor structure and formation method thereof |
-
2013
- 2013-08-27 CN CN201310379938.4A patent/CN104425370B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747850A (en) * | 1994-04-08 | 1998-05-05 | Texas Instruments Incorporated | Extended drain resurf lateral DMOS devices |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN102800631A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming complementary metal oxide semiconductor (CMOS) transistor |
| CN103094214A (en) * | 2011-11-04 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103258823A (en) * | 2012-02-16 | 2013-08-21 | 国际商业机器公司 | Semiconductor structure and formation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104425370A (en) | 2015-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104425370B (en) | A kind of semiconductor devices and its manufacture method | |
| US7208397B2 (en) | Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same | |
| US8815668B2 (en) | Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask | |
| US8148217B2 (en) | Semiconductor manufacturing method and semiconductor device | |
| US9263587B1 (en) | Fin device with blocking layer in channel region | |
| US10573645B2 (en) | Integrated semiconductor device and method for manufacturing the same | |
| US9142651B1 (en) | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device | |
| CN104425384B (en) | A kind of semiconductor devices and its manufacture method | |
| CN103928327B (en) | Fin formula field effect transistor and forming method thereof | |
| JP2002198529A (en) | Semiconductor device and its manufacturing method | |
| WO2010032174A1 (en) | Fin field effect transistor (finfet) | |
| US7994009B2 (en) | Low cost transistors using gate orientation and optimized implants | |
| US8093665B2 (en) | Semiconductor device and method for fabricating the same | |
| US10483172B2 (en) | Transistor device structures with retrograde wells in CMOS applications | |
| US20150270399A1 (en) | Semiconductor structure and method for manufacturing the same | |
| TWI633670B (en) | Power mosfets and methods for manufacturing the same | |
| US20090170269A1 (en) | High voltage mosfet devices containing tip compensation implant | |
| CN104425283B (en) | A kind of semiconductor devices and its manufacture method | |
| CN108109908B (en) | Semiconductor device and manufacturing method thereof | |
| US11398555B2 (en) | Transistor device with a plurality of active gates that can be individually modulated to change performance characteristics of the transistor | |
| CN103021827A (en) | Method for forming finned field effect transistor and complementary metal oxide semiconductor (CMOS) finned field effect transistor | |
| US20060177985A1 (en) | Source/drain extension implant process for use with short time anneals | |
| US20120309182A1 (en) | Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process | |
| US20220085155A1 (en) | Transistor device, ternary inverter device including same, and manufacturing method therefor | |
| Rao et al. | High-k metal-gate PMOS FinFET threshold voltage tuning with aluminum implantation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |