CN107464783B - CMOS devices and manufacturing method thereof - Google Patents

CMOS devices and manufacturing method thereof Download PDF

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CN107464783B
CN107464783B CN201710724977.1A CN201710724977A CN107464783B CN 107464783 B CN107464783 B CN 107464783B CN 201710724977 A CN201710724977 A CN 201710724977A CN 107464783 B CN107464783 B CN 107464783B
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channel region
work function
layer
barrier layer
function layer
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CN107464783A (en
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殷华湘
姚佳欣
赵超
叶甜春
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Institute of Microelectronics of CAS
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

The application provides CMOS devices and a manufacturing method thereof, which comprises the steps of providing a semiconductor substrate, forming a barrier layer on the surface of the semiconductor substrate, carrying out plasma nitridation treatment on a 0 th barrier layer of a second N-channel region and a second P-channel region, forming a th work function layer on a th barrier layer of a P-channel region and a th barrier layer of a second P-channel region, forming a second work function layer on a th barrier layer of an N-channel region and a th barrier layer of a second N-channel region and the th work function layer, and/or carrying out plasma nitridation treatment on an th barrier layer of the second N-channel region and a th work function layer of the second P-channel region.

Description

CMOS devices and manufacturing method thereof
Technical Field
The present invention relates to the field of Semiconductor device manufacturing technology, and more particularly, to types of CMOS (complementary metal Oxide Semiconductor) devices and a method for manufacturing the same.
Background
As the integration degree of integrated circuits is continuously improved and the size of devices is continuously reduced, it is difficult to continuously reduce the critical size of the conventional planar CMOS (complementary metal oxide semiconductor) devices, and three-dimensional devices such as FINFET (fin field effect transistor) and nanowire channel devices are gradually becoming the mainstream trend.
After entering a nano node, adjustment of the threshold voltage of a CMOS device is a key point and a difficulty in manufacturing a semiconductor device, and at present, the threshold voltage of the semiconductor device is adjusted mainly by adjusting ion implantation, Gate width (Gate Length), Gate dielectric layer thickness and work function layer thickness, and as the size of the semiconductor device is further reduced , especially when the size of the semiconductor device is below 10nm node, multiple threshold voltages need to be adjusted, but higher requirements are provided for the threshold adjustment of the CMOS device due to space limitation and parasitic effect influence caused by size reduction, and these traditional methods cannot well realize the adjustment of multiple thresholds.
Disclosure of Invention
In view of the above, the present invention provides CMOS devices and methods for fabricating the same, so as to adjust the multi-threshold voltage of the CMOS devices.
In order to achieve the purpose, the invention provides the following technical scheme:
A method for manufacturing a CMOS device, comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, and the channel region comprises an N channel region, a P channel region, a second N channel region and a second P channel region;
forming an th barrier layer on the surface of the semiconductor substrate;
performing a plasma nitridation process on the th barrier layer of the second N-channel region and the second P-channel region;
selectively forming a th work function layer on the th P channel region and the th barrier layer of the second P channel region;
forming a second work-function layer on the N-channel region, the barrier layer of the second N-channel region, and the work-function layer;
and/or after selectively forming a th work function layer on the th P channel region and the th barrier layer of the second P channel region, performing plasma nitridation treatment on the th barrier layer on the second N channel region and the th work function layer on the second P channel region.
CMOS devices, which are made by the above CMOS device making method, and the CMOS device comprises:
the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, wherein the channel region comprises an N channel region, a P channel region, a second N channel region and a second P channel region;
an th barrier layer, the th barrier layer covering the semiconductor substrate;
an th work function layer, the th work function layer being on the th barrier layer of the th P-channel region and the second P-channel region;
a second work function layer overlying the N-channel region, the th barrier layer of the second N-channel region, and the th work function layer;
the th barrier layer on the second N channel region and the second P channel region is a structural layer subjected to plasma nitridation treatment;
and/or the th barrier layer on the second N channel region and the th work function layer on the second P channel region are structural layers subjected to plasma nitridation treatment.
According to the technical scheme, the method for manufacturing the CMOS device further comprises plasma nitridation processing after the barrier layer is formed and/or after the th work function layer is selectively formed on the th barrier layer of the th P channel region and the th barrier layer of the second P channel region, plasma nitridation processing is simultaneously carried out on the th barrier layer and/or the th work function layer of the N channel region and the P channel region in a plasma nitridation processing mode, the work function of the NMOS region and the work function of the PMOS region are simultaneously adjusted times, and the work function of the CMOS device is not required to be adjusted by adjusting the thickness of the barrier layers, so that the integration process is simpler, the threshold value adjustment correlation between NMOS and PMOS is less in influence, and the control precision is higher.
The invention also provides CMOS devices which are formed by adopting the method, and the method has high control precision of threshold adjustment, high process flexibility, simplicity and feasibility, and is more suitable for the adjustment and control of multiple thresholds in small-size devices, so that the size of the CMOS devices can be continuously reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flow chart of a manufacturing method of CMOS devices according to an embodiment of the present invention;
fig. 2, 4-7 are schematic process steps of a manufacturing method of kinds of CMOS devices according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a channel region structure of CMOS devices according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of another CMOS device manufacturing methods according to an embodiment of the present invention;
fig. 9-11 are schematic diagrams illustrating processing steps of another methods for fabricating CMOS devices according to embodiments of the present invention;
fig. 12 is a flowchart illustrating a complete manufacturing method of CMOS devices according to an embodiment of the present invention.
Detailed Description
As described in the background section, the prior art has raised higher requirements for threshold adjustment of CMOS devices due to space limitations and parasitic effects caused by size reduction, and the conventional threshold adjustment method has not been able to achieve multi-threshold adjustment well.
Specifically, the method for adjusting the threshold of the CMOS device in the prior art is: depositing a barrier layer on the metal gates of the NMOS area and the PMOS area, then adjusting the thickness of the barrier layer, then depositing a PMOS work function layer (PMOS WFL), and then changing the thickness of the PMOS WFL to adjust the PMOS threshold; then, an NMOS work function layer (NMOS WFL) is deposited, and the NMOS WFL adjusts the NMOS threshold value together with the previous thickness variation of the barrier layer. In the prior art, the NMOS threshold value adjusting process needs to be divided into two sections, the threshold value adjusting process of the CMOS device is complex, the associated parasitic influence is easy to generate between the NMOS area and the PMOS area, and the accuracy of threshold value control is low.
Based on this, the invention provides methods for manufacturing CMOS devices, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, and the channel region comprises an N channel region, a P channel region, a second N channel region and a second P channel region;
forming an th barrier layer on the surface of the semiconductor substrate;
performing a plasma nitridation process on the th barrier layer of the second N-channel region and the second P-channel region;
selectively forming a th work function layer on the th P channel region and the th barrier layer of the second P channel region;
forming a second work-function layer on the N-channel region, the barrier layer of the second N-channel region, and the work-function layer;
and/or after selectively forming a th work function layer on the th P channel region and the th barrier layer of the second P channel region, performing plasma nitridation treatment on the th barrier layer on the second N channel region and the th work function layer on the second P channel region.
The method for manufacturing the CMOS device further comprises a plasma nitridation treatment step after the th barrier layer is formed and/or after the th work function layer is selectively formed on the th P channel region and the th barrier layer of the second P channel region, wherein the plasma nitridation treatment step is adopted to simultaneously perform plasma nitridation treatment on the th barrier layer and/or the th work function layer of the N channel region and the P channel region, times of simultaneous adjustment of the work function of the NMOS region and the work function of the PMOS region, and adjustment of the work function of the CMOS device through adjustment of the thickness of the barrier layers is not needed, so that the integration process is simpler, the threshold value adjustment correlation influence between the NMOS and the PMOS is smaller, and the control precision is higher.
The method is particularly suitable for adjusting the work function of a small-size CMOS device, for example, a CMOS device with the size of less than 10nm, the structure of the CMOS device can be a fin field effect transistor or a nanowire transistor, and the method can be applied to a front gate process or a back gate process.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only partial embodiments of of the present invention, rather than all embodiments.
The invention provides CMOS device manufacturing methods, please refer to FIG. 1, which comprises the following steps:
s101, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, and the channel region comprises an th N channel region, a th P channel region, a second N channel region and a second P channel region;
in the embodiment of the present invention, the semiconductor substrate may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator), or the like.
In this embodiment, as shown in fig. 2, the semiconductor substrate already has a channel region (110, 120, 130, 140) and a gate dielectric layer 150, the channel region (110, 120, 130, 140) is a region for forming a gate structure, as shown in fig. 2, the channel region may be a fin, in other embodiments of the present invention, the channel region may also be a nanowire 210, as shown in fig. 3, the channel region may also be any other structure, the channel region may be provided by using a suitable method, and the structure and the forming method of the channel region are not limited in the embodiments of the present invention.
The material of the gate dielectric layer may be determined according to the subsequently formed gate structure, in the embodiment of the present invention, the subsequently formed gate is a metal gate, and the gate dielectric layer may be made of a high-K dielectric material (for example, a material having a high dielectric constant compared to silicon oxide)Several materials), high-K dielectric materials such as hafnium-based oxide, HFO2HfSiO, HfSiON, HfTaO, HfTiO, etc., which are merely examples, the present invention is not limited thereto. An interface layer can be formed between the gate dielectric layer and the channel region, the interface layer is used for improving interface characteristics, and the interface layer can be made of silicon oxide or silicon oxynitride and the like.
, it can be applied to the front gate process, referring to fig. 2, first, the channel region of the fin 110 is formed by etching the substrate 100, then the gate dielectric layer 150 is deposited, then the metal gate formation is continued, in another , it can be applied to the back gate process, first, as shown in fig. 2, the substrate 100 is etched to form the channel region of the fin (110, 120, 130, 140), then, the gate dielectric layer, the dummy gate and the source drain region (not shown) are formed, after the dummy gate is removed, the metal gate formation is continued, in another , the channel region of the nanowire can be formed by a suitable method, in specific examples, as shown in fig. 3, the nanowire 210 can be formed by etching the substrate 200, both ends of the nanowire 210 are supported by the support structure 220, and the other regions are exposed for forming a fully-enclosed gate structure.
S102, forming an th barrier layer on the surface of the semiconductor substrate;
referring to fig. 4, the th barrier layer 160 is used to prevent diffusion of metal into the gate dielectric layer and the channel region, and the th barrier layer 160 may be or more selected from TiN, TaN, TiNx, TaNx, TiNSi, etc. as a composite material.
The th barrier layer can be formed by CVD (chemical vapor deposition), ALD (atomic layer deposition), or other suitable deposition methods in specific embodiments, a barrier layer of TiN can be formed using ALD methods.
S103, performing Plasma nitridation (Plasma nitridation) on the th barrier layers of the second N-channel region and the second P-channel region;
referring to fig. 5, in the present embodiment, a masking plate 170 may be formed on the N-channel region 110 and the P-channel region 120 to mask the N-channel region 110 and the P-channel region 120, so as to perform a plasma nitridation process on the second N-channel region 130 and the second P-channel region 140, wherein the masking plate 170 may be a PR (photoresist) material, or other polymers, organic oxides, doped oxides, amorphous carbon, carbides, etc. the masking plate 170 may be selectively removed after the plasma nitridation process without affecting the thickness and properties of other film layers, and the removal method may include any or more combinations of dry etching, wet etching, ashing, or stripping.
It should be noted that, in this embodiment, the specific process of the plasma nitridation is not limited, and the power, the ac/dc bias voltage, and the N of the plasma equipment may be adjusted2The gas flow rate and the gas pressure, etc., to adjust the degree of the plasma nitridation process, thereby changing the threshold of the second N-channel region and the second P-channel region. Optionally, the pressure range of the plasma nitridation process in this embodiment is 10Pa to 1300Pa, inclusive. The plasma nitridation treatment has a nitridation temperature of 150 ℃ to 650 ℃, inclusive. In this embodiment, the gas used in the plasma nitridation is not limited to nitrogen only, and may be a mixed gas of nitrogen and another gas. The ratio of nitrogen to other gases can be adjusted according to actual requirements, so that the threshold values of the second N-channel region and the second P-channel region are changed.
The specific principle of the method comprises the steps that plasma nitridation treatment is used for acting on TiNx base or TaNx base or composite material of the barrier layer to change the concentration of N vacancies in the material, for a PMOS region, the increase of N vacancies in TiN can weaken the binding energy of Ti-N bonds, so that the effective work function of a PMOS work function layer (TiN) moves towards a band, and thus the threshold value (absolute value) is increased, for an NMOS region, the increase of N vacancies can greatly increase the probability that Al in TiAlC of the work function layer is diffused by vacancies in a barrier layer, so that the integral effective work function of the NMOS region also moves towards the band, and thus the threshold value is also increased.
S104, selectively forming a th work function layer on the th P channel region and the th blocking layer of the second P channel region;
referring to fig. 6, the th work function layer 180 is a film layer for adjusting a work function of a device, that is, a PMOS work function layer, and in this embodiment, the specific material of the th work function layer 180 is not limited, and optionally, the th work function layer 180 in this embodiment may be selected from or more of TiN, TaN, TiNx, TaNx, TiNSi, and the like.
th work function layer 180 can be formed by CVD (chemical vapor deposition), ALD (atomic layer deposition), or other suitable deposition methods in specific embodiments, a th work function layer of TiN can be formed by CVD or ALD.
Specifically, the entire work function layer is formed on the th barrier layer 160, the 0 th work function layer covers the entire 1 th barrier layer, and the th work function layer is removed from the th N-channel region 110 and the th barrier layer 160 of the second N-channel region 130, so that the th work function layer 180 is formed on the th P-channel region 120 and the th barrier layer of the second P-channel region 140, that is, the th work function layer is formed only in the P-channel region, and the th work function layer is removed from the N-channel region.
The specific process method for removing the th work function layer on the th barrier layer of the th N-channel region and the second N-channel region is not limited in this embodiment, and optionally, any or more of dry etching, wet etching, ashing or stripping is included.
S105, forming a second work function layer on the th N-channel region, the th blocking layer of the second N-channel region and the th work function layer;
referring to fig. 7, the second work function layer 190 has the same function as the work function layer, and is a film layer for adjusting the work function of the device, that is, an NMOS work function layer.
The work function layer may be formed by CVD (chemical vapor deposition), ALD (atomic layer deposition), or other suitable deposition methods in specific embodiments, ALD methods may be used to form the second work function layer of TiAlC.
In this embodiment, the second work function layer 190 covers the th N-channel region 110, the second N-channel region 130, the th P-channel region 120, and the second P-channel region 140 at the same time.
It should be noted that, the embodiment of the present invention further provides an methods for manufacturing a CMOS device, as shown in fig. 8, including:
s201, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, and the channel region comprises an th N channel region, a th P channel region, a second N channel region and a second P channel region;
s202, forming an th barrier layer on the surface of the semiconductor substrate;
s203, selectively forming a th work function layer on the th P channel region and the th blocking layer of the second P channel region;
referring to fig. 9, in the present embodiment, the th work function layer 280 is formed only on the th P-channel region 120 and the th blocking layer 260 of the second P-channel region 140. the manufacturing method of the th work function 280 may refer to the manufacturing method in the above embodiment, which is not described in detail in this embodiment.
S204, performing plasma nitridation treatment on the th barrier layer on the second N channel region and the th work function layer on the second P channel region;
referring to fig. 10, in the present embodiment, a mask 170 is formed on the blocking layer 260 on the N-channel region 110 and on the work function 280 on the P-channel region 120 to shield the N-channel region 110 and the P-channel region 120, so that only the blocking layer 260 on the second N-channel region 130 and the work function layer 280 on the second P-channel region 140 are subjected to plasma nitridation.
And S205, forming a second work function layer on the th N-channel region, the th blocking layer of the second N-channel region and the th work function layer.
Referring to fig. 11, a second work function layer 290 is formed on the N-channel region 110, the blocking layer 260 of the second N-channel region 130, and the work function layer 280.
In this embodiment, the plasma nitridation step is performed after the th work function layer is formed, that is, after the PMOS work function layer (TiN, TiSiN, etc.) is deposited and selectively etched, the method and the principle are similar to those described above, which are not described in detail in this embodiment, and the specific steps may refer to the embodiment.
In devices below 10nm, there are typically four core devices for NMOS devices and PMOS devices, that is, there are four threshold voltages to be adjusted, which are HVT, RVT, LVT and SLVT respectively, if the respective adjustment is to be achieved, additional process steps are added and difficult to achieve, and after the th barrier layer and/or the PMOS work function layer is formed, plasma nitridation is performed to achieve adjustment of the work function, so that the process flexibility is high, the control precision is high, and the method is simple and easy to implement.
Referring to fig. 7 and 11, in the embodiment of the present invention, Plasma depletion is used to act on the TiNx-based or TaNx-based or composite material of the th barrier layer or on the material of the th work function layer to change the concentration of N vacancies in the material, in the case of the PMOS region, the effective work function of the work function layer (TiN) is shifted into the band due to the decrease of Ti-N bond binding energy due to the increase of N vacancies in TiN, thereby increasing the threshold (absolute value), and in the case of the NMOS region, the probability that Al diffusion in the TiAlC of the work function layer is trapped by vacancies in the th barrier layer is increased due to the increase of N vacancies, thereby causing the overall effective work function of the NMOS region to be shifted into the band, thereby also increasing the threshold, further making VTN-1< VTN-2, | VTP-1| < | VTP-2| in fig. 7 and 11 replace the prior art method of adjusting the threshold by adjusting the thickness of the present invention, which provides a threshold adjustment method of , which can more easily control the integration of the PMOS region and the PMOS region by nitriding process, thereby achieving a higher accuracy.
After understanding the main invention points of the present application, a complete process flow of a high-K metal gate CMOS device in the embodiment of the present invention is described below with reference to fig. 12, specifically, a process flow of a Fin Field Effect Transistor (FinFET):
s301: forming a fin FET on a silicon substrate;
s302: forming a device isolation region Fin STI;
S303-S309: forming a grid side wall and a source drain region at two sides of each dummy grid stacking structure, which specifically comprises the following steps: s303: doping to form a well region and a channel region of the NMOS and the PMOS; s304: forming a dummy gate; s305: forming a Spacer (Spacer); s306: source-drain doping of NMOS and PMOS; s307: respectively selecting epitaxial Si and SiGe from the source and drain of the NMOS and the PMOS; s308: doping the source and drain of the NMOS and the PMOS respectively; s309: and (5) doping and annealing.
Forming th interlayer electrolyte (ILD 0) S310, assembling th interlayer electrolyte stack (POP) S311;
s312: removing the dummy gate stack structures, and leaving a plurality of NMOS gate grooves and a plurality of PMOS gate grooves in the interlayer dielectric layer;
s313: depositing an isolation layer and a high-K dielectric layer;
completing the step S101, namely providing a semiconductor substrate having a channel region and a gate dielectric layer located on the channel region, wherein the channel region includes an th N channel region, a th P channel region, a second N channel region and a second P channel region;
next, step S314, namely step S102, is executed, wherein an th barrier layer barrier-I is formed on the surface of the semiconductor substrate;
next, step S315 of performing Plasma nitridation processing on the th barrier layers of the second N-channel region and the second P-channel region at the same time in the NMOS and PMOS partial regions, that is, step S103 of performing Plasma nitridation processing (Plasma nitridation) on the th barrier layers of the second N-channel region and the second P-channel region is performed;
next, steps S316-S317 are performed, in which a PMOS WFL (work function layer) is deposited and an NMOS region is selectively etched to remove the PMOS WFL, that is, step S104, a th work function layer is formed on the th P channel region and the th barrier layer of the second P channel region;
next, an NMOS WFL deposition is performed in step S318, i.e., in step S105, a second work function layer is formed on the N-channel region, the barrier layer of the second N-channel region, and the work function layer.
S319-S320, forming a second barrier layer and a filling layer in sequence in the NMOS gate trenches and the PMOS gate trenches, S320, Chemically Mechanically Polishing (CMP) the high-K metal gate stack, wherein the second barrier layer comprises at least or more of TiN, TaN, TiNx, TaNx and TiNSi, and the filling layer is preferably made of metal with low resistivity and high filling rate, such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or alloy of the metal and nitride of the metal.
S321-S325: and completing the interconnection of the devices. The method specifically comprises the following steps: s321: deposition to form a second interlayer electrolyte (ILD 1) S322: forming a metal layer (CT) and a Silicide layer (Silicide); s323: forming a tungsten plug (W plug) and chemically and mechanically polishing; s324: a multilayer interconnection; s325: and forming a passivation layer and a pin (Pad).
The embodiment of the present invention further provides kinds of CMOS devices, please refer to fig. 7 and fig. 11, including:
the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, wherein the channel region comprises an th N channel region 110, a th P channel region 120, a second N channel region 130 and a second P channel region 140;
an th barrier layer (160 or 260), a th barrier layer (160 or 260) covering the semiconductor substrate;
an th work function layer (180 or 280), a th work function layer (180 or 280) on the th barrier layer of the th P-channel region 120 and the second P-channel region 140;
a second work function layer (190 or 290), the second work function layer (190 or 290) overlying the th N-channel region 110, the th barrier layer (160 or 260) of the second N-channel region 130, and the th work function layer (180 or 280);
the th barrier layer (160 or 260) on the second N-channel region 130 and the second P-channel region 140 is a structural layer subjected to plasma nitridation;
and/or the th barrier layer (160 or 260) on the second N channel region 130 and the th work function layer (180 or 280) on the second P channel region 140 are structural layers subjected to plasma nitridation treatment.
In this embodiment, specific materials of the film layers are not limited, and optionally, the th barrier layer is made of or more composite materials of TiN, TaN, TiNx, TaNx, and TiNSi, the th work function layer is made of TiN, TaN, TiNx, TaNx, or TiNSi, and the second work function layer is made of Al, TiAl, TiAlx, tiaxcx, TiCx, or TaCx.
The channel region on the semiconductor substrate may be a fin or a nanowire, which is not limited in this embodiment.
The CMOS device provided by the embodiment of the invention is manufactured and formed by adopting the CMOS device manufacturing methods provided by the two embodiments. The work functions of an NMOS channel region and a PMOS channel region in the CMOS device are adjusted simultaneously through plasma nitridation treatment, the work function of the CMOS device is not required to be adjusted through adjusting the thickness of a blocking layer, and therefore the integration process is simpler, the threshold value adjusting correlation influence between the NMOS and the PMOS is smaller, and the control precision is higher.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.

Claims (10)

1, CMOS device manufacturing method, characterized by comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, and the channel region comprises an N channel region, a P channel region, a second N channel region and a second P channel region;
forming an th barrier layer on the surface of the semiconductor substrate;
performing a plasma nitridation process on the th barrier layer of the second N-channel region and the second P-channel region;
forming a th work function layer on the th and th barrier layers of the second P-channel region;
forming a second work-function layer on the N-channel region, the barrier layer of the second N-channel region, and the work-function layer;
or after the step of forming a th work function layer on the th P channel region and the th barrier layer of the second P channel region, performing plasma nitridation treatment on the th barrier layer on the second N channel region and the th work function layer on the second P channel region.
2. The CMOS device fabrication method of claim 1, wherein the plasma nitridation process is at a pressure in a range from 10Pa to 1300Pa, inclusive.
3. The method of claim 2 wherein the nitridation temperature of the plasma nitridation process is between 150 ℃ and 650 ℃, inclusive.
4. The method of any , wherein the barrier layer is chosen from one or more of TiNx, TaNx and TiNSi .
5. The method of any of , wherein the work function layer comprises TiNx, TaNx or TiNSi.
6. The method of any of claims 1-3 and , wherein the second work function layer comprises Al, TiAlx, TiAlCx, TiCx, or TaCx.
7. The CMOS device fabrication method of any one of claims 1-3 and , wherein the channel region is a fin or a nanowire.
8, CMOS devices, wherein the CMOS devices are formed by the method of any claims 1-7, the CMOS devices comprising:
the semiconductor substrate is provided with a channel region and a gate dielectric layer positioned on the channel region, wherein the channel region comprises an N channel region, a P channel region, a second N channel region and a second P channel region;
an th barrier layer, the th barrier layer covering the semiconductor substrate;
an th work function layer, the th work function layer being on the th barrier layer of the th P-channel region and the second P-channel region;
a second work function layer overlying the N-channel region, the th barrier layer of the second N-channel region, and the th work function layer;
the th barrier layer on the second N channel region and the second P channel region is a structural layer subjected to plasma nitridation treatment;
or, the th barrier layer on the second N channel region and the th work function layer on the second P channel region are structural layers subjected to plasma nitridation treatment.
9. The CMOS device of claim 8, wherein the channel region is a fin or a nanowire.
10. The CMOS device of claim 9, wherein said barrier layer is made of or more of TiNx, TaNx and TiNSi, said work function layer is made of TiNx, TaNx or TiNSi, and said second work function layer is made of Al, TiAlx, TiAlCx, TiCx or TaCx.
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