CN108109908B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area, and a gate structure is formed on the semiconductor substrate of the first device area and the second device area; performing doping ion implantation of a first doping type to form a lightly doped source drain region in the first device region, and simultaneously forming an ion implantation region in a gate oxide layer of the second device region, wherein the thickness of the gate oxide layer in the second device region is greater than the depth of the lightly doped source drain region in the first device region; and performing doping ion implantation of a second doping type to form a bag-shaped implantation area in the first device area and simultaneously form a light-doped source drain area in the semiconductor substrate below the gate oxide layer of the second device area. Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention saves a mask process.
Description
Technical Field
The present invention relates to a semiconductor manufacturing process, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
Along with the continuous improvement of semiconductor device integration, the characteristic dimension reduces gradually, and the length of the channel of MOS transistor also reduces gradually, and the thickness of gate dielectric layer also reduces continuously, because gate voltage can not reduce continuously (at least 1V at present), makes the electric field intensity that gate oxide received grow, and Time Dependent Dielectric Breakdown (TDDB) also takes place more easily, and forms Hot Carrier Injection effect (HCI) easily. In the prior art, a lightly doped source drain (LDD) process has become one of standard processes for effectively suppressing hot carrier effect of sub-micron and ultra-deep sub-micron MOS devices. After forming the LDD source/drain region, Pocket implantation (Pocket) may be performed on both sides of the LDD source/drain region near the channel region, where the type of impurity ions implanted in the Pocket implantation region is opposite to the type of impurity ions implanted in the LDD region, so that depletion regions on both sides of the LDD source/drain region near the channel region are narrowed, and a short channel effect can be alleviated.
Semiconductor devices typically include a plurality of transistors that are interconnected by an interconnect structure to perform a certain function. These transistors typically include low voltage NMOS transistors, low voltage PMOS transistors, high voltage NMOS transistors, high voltage PMOS transistors, and the like. Different masks are needed when forming the lightly doped source-drain regions of different MOS transistors, and the process is complex. For example, a 90nm MCU product comprises 1.2V/3.3V/5V MOS devices, and 7 different masks are needed in formation of lightly doped source and drain regions of the devices, so that the process is complex, the cost and the manufacturing period of the product are increased, and the yield of the product is reduced.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a semiconductor device comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area, and a gate structure is formed on the semiconductor substrate of the first device area and the second device area;
performing doping ion implantation of a first doping type on the semiconductor substrate on two sides of the gate structures of the first device region and the second device region to form a lightly doped source drain region in the first device region, and simultaneously forming an ion implantation region in a gate oxide layer of the second device region, wherein the thickness of the gate oxide layer in the second device region is greater than the depth of the lightly doped source drain region in the first device region;
and performing doping ion implantation of a second doping type on the semiconductor substrate at two sides of the gate structures of the first device area and the second device area to form a bag-shaped implantation area in the first device area and simultaneously form a lightly doped source drain area in the semiconductor substrate below the gate oxide layer of the second device area.
Illustratively, the first doping type is P-type, and the second doping type is N-type.
Illustratively, the semiconductor device formed by the first device region is a PMOS device, and the semiconductor device formed by the second device region is an NMOS device.
Illustratively, the threshold voltage of the NMOS device is higher than the threshold voltage of the PMOS device.
Illustratively, the first doping type is N-type, and the second doping type is P-type.
Illustratively, the semiconductor device formed by the first device region is an NMOS device, and the semiconductor device formed by the second device region is a PMOS device.
Illustratively, the threshold voltage of the PMOS device is higher than the threshold voltage of the NMOS device.
Illustratively, the first doping type dopant ion implantation and the second doping type dopant ion implantation use the same mask.
The invention also provides a semiconductor device manufactured by the method of any one of the above.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention saves a mask process, thereby simplifying the process and saving the cost.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1a-1b are cross-sectional views of a structure of a semiconductor device of the prior art;
fig. 2 is a flow chart of a method of manufacturing a semiconductor device in an embodiment of the invention;
fig. 3a-3b are cross-sectional views of structures of semiconductor devices fabricated by a method of fabricating a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Different masks are needed when forming the lightly doped source-drain regions of different MOS transistors, and the process is complex. For example, a 90nm MCU product comprises 1.2V/3.3V/5V MOS devices, and 7 different masks are needed in formation of lightly doped source and drain regions of the devices, so that the process is complex, the cost and the manufacturing period of the product are increased, and the yield of the product is reduced.
Taking the conventional 1.2V PMOS and 5.0V NMOS as examples, they are shown in FIGS. 1a and 1 b. Fig. 1a shows a 1.2V PMOS device, which includes a semiconductor substrate 101, a gate electrode 104, an LDD region 103 and a pocket implant region 102, wherein the LDD region 103 and the pocket implant region 102 are formed using the same mask, and the doping elements are B and P, respectively. The gate oxide layer 105a of the 1.2V PMOS device is thin. In fig. 1b is a 5.0V NMOS device, which includes a semiconductor substrate 101, a gate electrode 104, an LDD region 106, and a gate oxide layer 105 b. The pocket implant region is not required in the 5.0V NMOS device, where the LDD region 103 is doped with P. The thickness of the gate oxide layer 105 of the 5.0V NMOS device is greater than that of the gate oxide layer of the 1.2V PMOS device and greater than that of the LDD region of the 1.2V PMOS device. The case in 1.2V NMOS devices and 5.0V PMOS devices is similar to the above case.
Based on the above principle, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area, and a gate structure is formed on the semiconductor substrate of the first device area and the second device area;
performing doping ion implantation of a first doping type on the semiconductor substrate on two sides of the gate structures of the first device region and the second device region to form a lightly doped source drain region in the first device region, and simultaneously forming an ion implantation region in a gate oxide layer of the second device region, wherein the thickness of the gate oxide layer in the second device region is greater than the depth of the lightly doped source drain region in the first device region;
and performing doping ion implantation of a second doping type on the semiconductor substrate at two sides of the gate structures of the first device area and the second device area to form a bag-shaped implantation area in the first device area and simultaneously form a lightly doped source drain area in the semiconductor substrate below the gate oxide layer of the second device area.
The first doping type is P type, and the second doping type is N type. The semiconductor device formed in the first device region is a PMOS device, and the semiconductor device formed in the second device region is an NMOS device. The threshold voltage of the NMOS device is higher than the threshold voltage of the PMOS device.
The first doping type is N type, and the second doping type is P type. The semiconductor device formed in the first device region is an NMOS device, and the semiconductor device formed in the second device region is a PMOS device. The threshold voltage of the PMOS device is higher than the threshold voltage of the NMOS device.
The first doping type and the second doping type dopant ion implantation use the same mask.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention saves a mask process, thereby simplifying the process and saving the cost.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed. [ exemplary embodiment one ]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 2 and fig. 3a and 3 b.
First, step 201 is executed, and a semiconductor substrate 301 is provided, wherein the semiconductor substrate includes a first device region and a second device region, and a gate structure is formed on the semiconductor substrate of the first device region and the second device region. The first device region is shown in fig. 3a and the second device region is shown in fig. 3 b.
Specifically, a semiconductor substrate 301 is first provided, which is made of a semiconductor material such as silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-germanium-on-insulator (S-SiGeOI), silicon-on-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). An isolation structure (not shown), such as a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, is formed on the semiconductor substrate. The isolation structure is located between adjacent devices for electrically isolating the adjacent devices. The specific forming process of the isolation structure is well known to those skilled in the art, and will not be described herein. Various well regions (not shown) may also be formed on the semiconductor substrate.
Next, a gate structure is formed over the semiconductor substrate 301. In the first device region, the gate structure includes a gate electrode layer 304 and a gate oxide layer 305a, wherein the gate oxide layer 305a is very thin; in the second device region, the gate structure includes a gate electrode layer 304 and a gate oxide layer 305b, wherein the thickness of the gate oxide layer 305b is much greater than the thickness of the gate oxide layer 305a in the first device region. Illustratively, the gate oxide layer may be silicon oxide (SiO)2) Or silicon oxynitride (SiON), etc. The gate electrode layer is formed on the gate oxide layer. Gate electrode layerMay be one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer. In this embodiment, the gate electrode layer is preferably a polysilicon material. Methods for forming gate oxide and gate electrode layers include Chemical Vapor Deposition (CVD) such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and generally similar methods such as sputtering and Physical Vapor Deposition (PVD) may also be used.
Next, step 202 is performed to form a patterned mask layer on the semiconductor substrate. The mask layer exposes the first device region and the second device region. The patterned masking layer can be any suitable masking material known to those skilled in the art, including but not limited to a photoresist material or a hardmask material, among others.
Next, step 203 is executed, doping ions of a first doping type are implanted into the semiconductor substrate on two sides of the gate structures of the first device region and the second device region, so as to form a lightly doped source-drain region 302 in the first device region, and an ion implantation region 306 is formed in the gate oxide layer 305b of the second device region, where the thickness of the gate oxide layer 305b in the second device region is greater than the depth of the lightly doped source-drain region 302 in the first device region. In this embodiment, the first doping type is P-type, and the implanted ions may be boron or the like. The threshold voltage of the semiconductor device formed by the first device area is higher than that of the semiconductor device formed by the second device area. Illustratively, the semiconductor devices formed in the first device region are 1.2V PMOS devices and the semiconductor devices formed in the second device region are 5V NMOS devices. Because the injection depth of the PLDD in the 1.2V PMOS device is shallow, for example 100-200 angstroms, and is less than the thickness of the gate oxide layer of the 5V NMOS device, the ion injection region of the first doping type in the second device region is formed in the gate oxide layer 305b, so that the doped ions are prevented from diffusing into the silicon substrate, and the performance of the device is not influenced. In another embodiment, the first doping type is N type, the semiconductor device formed in the first device region is a 1.2V NMOS device, and the semiconductor device formed in the second device region is a 5V PMOS device. NLDD is formed in the 1.2V NMOS device at this time and an N-type ion implantation region is formed in the gate oxide of the 5V PMOS device.
Next, step 204 is performed, and doping ion implantation of the second doping type is performed on the semiconductor substrate at two sides of the gate structures of the first device region and the second device region, so as to form a pocket implantation region 303 in the first device region, and simultaneously form a lightly doped source/drain region 307 in the semiconductor substrate below the second device region gate oxide layer 305 b. The second doping type is opposite to the first doping type, namely when the first doping type is an N type, the second doping type is a P type; on the contrary, when the first doping type is P-type, the second doping type is N-type. In one embodiment, the second doping type is N-type, and the implanted ions may be phosphorus or the like. In the first device region, since the type of the implanted ions of the pocket-shaped implantation region 303 is the same as the type of the doped ions of the semiconductor substrate and is opposite to the type of the doped ions of the source/drain region formed later, and the concentration of the doped ions is greater than the concentration of the impurity ions of the semiconductor substrate of the channel region, the width of the depletion region in the outer region of the lightly doped source/drain region close to the gate structure is narrowed, so that the threshold voltage Vt is adjusted and the punch-through of the source/drain depletion layer is prevented. And in the second device region, dopant ions of the second doping type are implanted to a depth greater than the thickness of the gate oxide layer 305b, thereby forming lightly doped source-drain regions 307 below the gate oxide layer. In another embodiment, the second doping type is P-type.
After the above steps are performed, subsequent steps in the existing process may be continuously performed, for example, source and drain ion implantation and annealing treatment are performed to form a source and drain heavily doped region in the well region.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention saves a mask process, thereby simplifying the process and saving the cost.
[ second exemplary embodiment ]
A semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3a and 3 b. The semiconductor device is manufactured by a method as shown in fig. 2.
The semiconductor device comprises a semiconductor substrate 301, the semiconductor substrate comprising a first device region as shown in fig. 3a and a second device region as shown in fig. 3b, and a gate structure formed on the semiconductor substrate of the first device region and the second device region. In the first device region, the gate structure includes a gate electrode layer 304 and a gate oxide layer 305a, wherein the gate oxide layer 305a is very thin; in the second device region, the gate structure includes a gate electrode layer 304 and a gate oxide layer 305b, wherein the thickness of the gate oxide layer 305b is much greater than the thickness of the gate oxide layer 305a in the first device region.
The first device region is formed with a lightly doped source/drain region 302 of a first doping type, the gate oxide layer 305b of the second device region is formed with an ion implantation region 306 of the first doping type, and the lightly doped source/drain region 302 and the ion implantation region 306 are formed in the same step by using the same mask. The thickness of the gate oxide layer 305b in the second device region is greater than the depth of the lightly doped source/drain region 302 in the first device region. The gate oxide layer 305b prevents diffusion of dopant ions into the silicon substrate without affecting the performance of the device.
A pocket implantation region 303 of the second doping type is formed in the first device region, and a lightly doped source drain region 307 of the second doping type is formed in the semiconductor substrate below the gate oxide layer 305b of the second device region. The pocket implant region 303 and the lightly doped source drain region 307 are formed in the same step using the same mask. The depths of the pocket implantation region 303 and the lightly doped source drain region 307 are greater than the thickness of the gate oxide layer 305b of the second device region.
The first doping type is opposite to the second doping type, namely when the first doping type is an N type, the second doping type is a P type; on the contrary, when the first doping type is P-type, the second doping type is N-type. In one embodiment, the first doping type is P-type, the second doping type is N-type, the semiconductor device formed in the first device region is a 1.2V PMOS device, and the semiconductor device formed in the second device region is a 5V NMOS device. In another embodiment, the first doping type is N-type, the second doping type is P-type, the semiconductor device formed in the first device region is a 1.2V NMOS device, and the semiconductor device formed in the second device region is a 5V PMOS device.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention saves a mask process, thereby simplifying the process and saving the cost.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area, and a gate structure is formed on the semiconductor substrate of the first device area and the second device area;
performing doping ion implantation of a first doping type on the semiconductor substrate on two sides of the gate structures of the first device region and the second device region to form a lightly doped source drain region in the first device region, and simultaneously forming an ion implantation region in a gate oxide layer of the second device region, wherein the thickness of the gate oxide layer in the second device region is greater than the depth of the lightly doped source drain region in the first device region;
and performing doping ion implantation of a second doping type on the semiconductor substrate at two sides of the gate structures of the first device area and the second device area to form a bag-shaped implantation area in the first device area, and simultaneously forming a lightly doped source drain area in the semiconductor substrate below the gate oxide layer of the second device area, wherein the second doping type is opposite to the first doping type.
2. The method of claim 1, wherein the first doping type is P-type and the second doping type is N-type.
3. The method of claim 2, wherein the semiconductor devices formed in the first device region are PMOS devices and the semiconductor devices formed in the second device region are NMOS devices.
4. The method of claim 3, wherein the threshold voltage of the NMOS device is higher than the threshold voltage of the PMOS device.
5. The method of claim 1, wherein the first doping type is N-type and the second doping type is P-type.
6. The method of claim 5, wherein the semiconductor devices formed in the first device region are NMOS devices and the semiconductor devices formed in the second device region are PMOS devices.
7. The method of claim 6, wherein the threshold voltage of the PMOS device is higher than the threshold voltage of the NMOS device.
8. The method of claim 1, wherein the first doping type dopant ion implantation and the second doping type dopant ion implantation use the same mask.
9. A semiconductor device, characterized in that it is manufactured using the method of any of claims 1-8.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6387735B1 (en) * | 2000-01-12 | 2002-05-14 | Kmt Semiconductor, Ltd. | Method for manufacturing field effect transistor capable of successfully controlling transistor characteristics relating to the short-channel effect |
| US6667524B1 (en) * | 2002-09-13 | 2003-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a plurality of semiconductor elements |
| CN101452884A (en) * | 2007-12-05 | 2009-06-10 | 东部高科股份有限公司 | Multi device and method of manufacturing the same |
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| KR100624912B1 (en) * | 2005-03-22 | 2006-09-19 | 주식회사 하이닉스반도체 | Method for fabricating flash memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6387735B1 (en) * | 2000-01-12 | 2002-05-14 | Kmt Semiconductor, Ltd. | Method for manufacturing field effect transistor capable of successfully controlling transistor characteristics relating to the short-channel effect |
| US6667524B1 (en) * | 2002-09-13 | 2003-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a plurality of semiconductor elements |
| CN101452884A (en) * | 2007-12-05 | 2009-06-10 | 东部高科股份有限公司 | Multi device and method of manufacturing the same |
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