CN104425272A - Forming methods for offset side wall and transistor - Google Patents
Forming methods for offset side wall and transistor Download PDFInfo
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- CN104425272A CN104425272A CN201310382850.8A CN201310382850A CN104425272A CN 104425272 A CN104425272 A CN 104425272A CN 201310382850 A CN201310382850 A CN 201310382850A CN 104425272 A CN104425272 A CN 104425272A
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- layer
- offset side
- side wall
- formation method
- polysilicon gate
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 83
- 229920005591 polysilicon Polymers 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 125
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- 230000015572 biosynthetic process Effects 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
Abstract
Provided are forming methods for an offset side wall and a transistor. The forming method for an offset side wall comprises providing a substrate; forming a polysilicon gate on the substrate; and oxidizing the side wall of the polysilicon gate to form the offset side wall. The method can form the offset side walls with uniform thickness on the side walls of the gate side walls.
Description
Technical field
The present invention relates to semiconductor applications, the formation method of a kind of formation method being related specifically to offset side wall and the transistor comprising this offset side wall.
Background technology
In semiconductor process, normal employing ion implantation is to form source electrode and drain electrode, after execution ion implantation technology, need to anneal, the ion injected is spread to darker wider direction further in Semiconductor substrate, and distribution evenly, but also can to repair in ion implantation process the damage that Semiconductor substrate is brought.
But along with the decline of device size, the conducting channel between source area and drain region is very short, if will anneal after LDD so traditionally, source electrode and drain electrode break-through may be made, thus device performance will be caused defective.
In prior art, before carrying out LDD, form the offset side wall (spacer) of all around gate, to prevent the ion implantation of larger dose too close to raceway groove, source electrode and drain electrode break-through can be prevented.
In prior art, the method forming described offset side wall comprises:
With reference to figure 1, provide substrate 1, described substrate 1 forms grid 2.
With reference to figure 2, use chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald, at described substrate 1 and grid 2 upper surface, and the sidewall of described grid 2 forms offset side wall 3.
Along with the reduction of device critical dimensions, use chemical vapour deposition (CVD), offset side wall 3 that physical vapour deposition (PVD) or ald are formed in uneven thickness, this can affect follow-up ion implantation technology.
Summary of the invention
The problem that the present invention solves is in prior art, and the thickness of offset side wall is very uneven.
For solving the problem, the invention provides a kind of formation method of offset side wall, comprising: substrate is provided; Form polysilicon gate on the substrate; The sidewall being oxidized described polysilicon gate forms offset side wall.
Optionally, the method forming described polysilicon gate comprises: form polysilicon layer on the substrate; Described polysilicon layer forms patterned photoresist, the position of described patterned photoresist definition polysilicon gate; With described patterned photoresist for mask, etch described polysilicon layer, form polysilicon gate.
Optionally, after forming polysilicon gate, use free-radical oxidation or thermal oxidation method to be oxidized the sidewall of described polysilicon gate, then remove described patterned photoresist.
Optionally, the method using free-radical oxidation method to be oxidized the sidewall of described polysilicon gate comprises: reaction chamber is put in the substrate being formed with polysilicon gate; O is passed in described reaction chamber
2and H
2, and voltage is applied in described reaction chamber, make O
2produce oxygen radical; Apply bias voltage on the substrate, described oxygen radical and described polysilicon gate sidewall are reacted, form offset side wall at described polysilicon gate sidewall.
Optionally, the temperature in described reaction chamber is 500-1000 DEG C, described O
2volume fraction be 10%-60%.
Optionally, the thickness of described offset side wall is 4-10nm.
Optionally, before forming polysilicon layer on the substrate, high-k dielectric layer and the protective layer for the protection of described high-k dielectric layer is formed with from the bottom to top successively on the substrate.
Optionally, with described patterned photoresist for mask, when etching described polysilicon layer, described etching stopping, in described polysilicon layer lower surface or protective layer, after forming offset side wall, uses wet etching to remove protective layer and the high-k dielectric layer of exposure.
Optionally, with described patterned photoresist for mask, when etching described polysilicon layer, described etching stopping, in high-k dielectric layer, after forming offset side wall, uses wet etching to remove the high-k dielectric layer exposed.
Optionally, before forming polysilicon layer on the substrate, form the first silicon oxide layer on the substrate, described polysilicon layer is formed on described first silicon oxide layer.
Optionally, before described polysilicon layer forms patterned photoresist, described polysilicon layer forms hard mask layer, described patterned photoresist is formed on described hard mask layer.
Optionally, before described hard mask layer forms patterned photoresist, described hard mask layer is formed with amorphous carbon, the second silicon oxide layer and anti-reflecting layer from the bottom to top successively.
Optionally, described anti-reflecting layer is siliceous anti-reflecting layer.
Optionally, the material of described high-k dielectric layer is HfSiON, HfO
2, HfSiO, HfTaO, HfTiO, HfZrO, Al
2o
3, La
2o
3, ZrO
2, or LaAlO.
Optionally, the material of described protective layer is TaN or TiN.
Optionally, the material of described hard mask layer is silicon nitride or silicon oxynitride.
The present invention also provides a kind of formation method of transistor, comprising: use said method to form offset side wall.
Compared with prior art, technical scheme of the present invention has the following advantages:
The technical program forms silica by the sidewall of the described polysilicon gate of oxidation, described silica is as the offset side wall of described polysilicon gate, avoid by using chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald to form offset side wall in prior art, and then avoid an offset side wall difficult problem in uneven thickness.
Further, the technical program adopts free-radical oxidation method to be oxidized the sidewall of described polysilicon gate, because free-radical oxidation method can the thickness of accurate controlled oxidization layer, therefore can obtain size accurately, and the uniform offset side wall of thickness.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the cross-sectional view of offset side wall formation method each production phase in prior art;
Fig. 3 to Figure 12 is the cross-sectional view of offset side wall formation method each production phase of first embodiment of the invention;
Figure 13 is the cross-sectional view of the Transistor forming method of second embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
The present embodiment provides a kind of formation method of offset side wall, comprising:
With reference to figure 3, provide substrate 110.
In a particular embodiment, the material of described substrate 110 can be the semi-conducting material of the routines such as silicon, SiGe, silicon-on-insulator (siliconon insulator is called for short SOI).
With reference to figure 4, described substrate 110 forms the first silicon oxide layer 120.
The method forming described first silicon oxide layer 120 can be: in described substrate 110, deposit one deck silica as described first silicon oxide layer 120.
In other embodiments, also the first silicon oxide layer 120 can be formed by substrate described in thermal oxidation 110.
The effect forming described first silicon oxide layer 120 is the described substrate 110 of protection injury-free and pollution in subsequent etching processes.
With reference to figure 5, described first silicon oxide layer 120 is formed with high-k dielectric layer 131 and the protective layer 132 for the protection of described high-k dielectric layer 131 from the bottom to top successively.
Formation high-k dielectric layer 131 can improve the capacitance between polysilicon gate and channel region, effectively reduces the threshold voltage of transistor and improves drive current.
But because high-k dielectric layer 131 is easily oxidized in atmosphere and reduce its performance, so generally also need to be formed protective layer 132 in described high-k dielectric layer 131, to prevent the reduction of high-k dielectric layer 131 performance.
In a particular embodiment, the material of described high-k dielectric layer 131 is HfSiON, HfO
2, HfSiO, HfTaO, HfTiO, HfZrO, Al
2o
3, La
2o
3, ZrO
2, or LaAlO.The material of described protective layer 132 is TaN or TiN.
With reference to figure 6, described protective layer 132 forms polysilicon layer 140.
The method forming described polysilicon layer 140 can be sedimentation.
With reference to figure 7, described polysilicon layer 140 is formed with hard mask layer 150.
The effect of described hard mask layer 150 be first by the Graphic transitions in patterned photoresist in hard mask layer 150, then with patterned hard mask layer for polysilicon layer described in mask etching 140.The transfer precision of the figure in patterned photoresist can be improved on the one hand; On the other hand, because patterned photoresist is easily consumed when etching described polysilicon layer 140, cause polysilicon layer 140 also not by completely graphical, described patterned photoresist has just been consumed, and cannot complete the graphical of polysilicon layer 140.When etching described polysilicon layer 140, the general and hard mask layer 150 of described polysilicon layer 140 has higher etching selection ratio, can complete the graphical of polysilicon layer 140 smoothly.
The material of described hard mask layer 150 is silicon nitride, silicon oxynitride, silica or other materials known in the art.
With reference to figure 8, described hard mask layer 150 forms patterned photoresist 160, described patterned photoresist 160 defines the position of polysilicon gate.
In other embodiments, before described hard mask layer 150 forms patterned photoresist 160, first on described hard mask layer 150, form anti-reflecting layer, patterned photoresist 160 is formed on described anti-reflecting layer.
Described anti-reflecting layer for reducing the reflection produced in exposure process, to improve the transfer effect of fine pattern.Exposing the depth of field (DOF) to increase in exposure process, realizing the uniform exposure of photoresist, described anti-reflecting layer can for containing Si anti-reflecting layer (Si-ARC).
In other embodiments, before described hard mask layer 150 forms anti-reflecting layer, first on described hard mask layer 150, form amorphous carbon and the second silicon oxide layer successively from the bottom to top, described anti-reflecting layer is formed on described second silicon oxide layer, to improve the pattern of the polysilicon gate of formation further.
With reference to figure 9, with described patterned photoresist 160 for mask, etch described hard mask layer 150 and described polysilicon layer 140, form patterned hard mask layer 151 and polysilicon gate 141.
Etching stopping is at described polysilicon layer 140 lower surface.The method etching described hard mask layer 150 can be plasma etching, and the source of the gas of plasma is N
2and O
2.
In a particular embodiment, CCl can be adopted
4polysilicon layer 140 described in plasma etching.
In other embodiments, etching also can stop in described protective layer 132, when can prevent the sidewall of polysilicon gate 141 described in subsequent oxidation, is also oxidized described high-k dielectric layer 131.
In other embodiments, etching also can stop in high-k dielectric layer 131.
With reference to Figure 10, the sidewall being oxidized described polysilicon gate 141 forms offset side wall 142.
The method being oxidized described polysilicon gate 141 is free-radical oxidation.
The method of carrying out free-radical oxidation comprises:
Reaction chamber is put in the substrate 110 being formed with polysilicon gate 141;
O is passed in described reaction chamber
2and H
2, and voltage is applied in described reaction chamber, make O
2produce oxygen radical;
Described substrate 110 applies bias voltage, described oxygen radical and described polysilicon gate 141 sidewall are reacted, form oxide layer at described polysilicon gate 141 sidewall, described oxide layer is described offset side wall 142.
Wherein, the temperature in reaction chamber is 500-1000 DEG C, described O
2volume fraction be 10%-60%.Temperature in the time of being reacted by control, reaction chamber and O
2volume fraction, accurately can control the thickness of oxide layer that described polysilicon gate 141 sidewall is formed.
H
2effect be make O
2be evenly distributed in reaction chamber, form the uniform oxide layer of thickness at described polysilicon gate 141 sidewall.
In a particular embodiment, the thickness of described offset side wall is 4-10nm.
In free-radical oxidation process, described patterned photoresist 160 and patterned hard mask layer 151 protect the upper surface of described polysilicon gate 141, make it can not be oxidized.
Due to the sidewall being oxidized described polysilicon gate 141 form offset side wall 142 time, polysilicon gate 141 can be consumed, its size is reduced, so the size that described patterned photoresist 160 defines should be greater than the size of the polysilicon gate 141 finally obtained.
Described protective layer 132 and high-k dielectric layer 131 also serve the effect protecting described substrate 110, make it not oxidized.
The technical program forms silica by the sidewall of the described polysilicon gate 141 of oxidation, described silica is as the offset side wall 142 of described polysilicon gate 141, avoid by using chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald to form offset side wall in prior art, and then avoid an offset side wall difficult problem in uneven thickness.
Due to the sidewall adopting free-radical oxidation method to be oxidized described polysilicon gate 141, because free-radical oxidation method can the thickness of accurate controlled oxidization layer, size therefore can be obtained accurately, and the uniform offset side wall 142 of thickness.
In other embodiments, the sidewall that the methods such as thermal oxidation also can be used to be oxidized described polysilicon gate 141 forms offset side wall 142.
With reference to Figure 11, use wet etching to remove protective layer 132 and the high-k dielectric layer 131 of exposure, form patterned protective layer 133 and patterned high-k dielectric layer 134.
Use wet etching, because etch rate is slow, make to etch easy control, substrate 110 can not be damaged because of over etching.
With reference to Figure 12, remove described patterned photoresist 160 and patterned hard mask layer 151.
Be described to be formed with the first silicon oxide layer 120, high-k dielectric layer 131 and the protective layer 132 formation method to described offset side wall 142 above, in other embodiments, also can not form the one in the first silicon oxide layer 120 and high-k dielectric layer 131.If do not form high-k dielectric layer 131, described protective layer 132 also can not be formed.
Above to form hard mask layer 150, the formation method of described offset side wall is described, in other embodiments, also can not forms hard mask layer 150.
Second embodiment
The present embodiment provides a kind of formation method of transistor, comprising:
Offset side wall 142 is formed according to the method for the first embodiment;
Then, with reference to Figure 13, in the substrate 110 of polysilicon gate 141 both sides, source S and drain D is formed.
The method forming described source S and drain D is ion implantation or thermal diffusion.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a formation method for offset side wall, is characterized in that, comprising:
Substrate is provided;
Form polysilicon gate on the substrate;
The sidewall being oxidized described polysilicon gate forms offset side wall.
2. the formation method of offset side wall as claimed in claim 1, it is characterized in that, the method forming described polysilicon gate comprises:
Form polysilicon layer on the substrate;
Described polysilicon layer forms patterned photoresist, the position of described patterned photoresist definition polysilicon gate;
With described patterned photoresist for mask, etch described polysilicon layer, form polysilicon gate.
3. the formation method of offset side wall as claimed in claim 2, is characterized in that, after forming polysilicon gate, uses free-radical oxidation or thermal oxidation method to be oxidized the sidewall of described polysilicon gate, then removes described patterned photoresist.
4. the formation method of offset side wall as claimed in claim 3, is characterized in that, the method using free-radical oxidation method to be oxidized the sidewall of described polysilicon gate comprises:
Reaction chamber is put in the substrate being formed with polysilicon gate;
O is passed in described reaction chamber
2and H
2, and voltage is applied in described reaction chamber, make O
2produce oxygen radical;
Apply bias voltage on the substrate, described oxygen radical and described polysilicon gate sidewall are reacted, form offset side wall at described polysilicon gate sidewall.
5. the formation method of offset side wall as claimed in claim 4, it is characterized in that, the temperature in described reaction chamber is 500-1000 DEG C, described O
2volume fraction be 10%-60%.
6. the formation method of the offset side wall as described in claim 1 or 3, is characterized in that, the thickness of described offset side wall is 4-10nm.
7. the formation method of offset side wall as claimed in claim 2, is characterized in that, before forming polysilicon layer on the substrate, is formed with high-k dielectric layer and the protective layer for the protection of described high-k dielectric layer from the bottom to top successively on the substrate.
8. the formation method of offset side wall as claimed in claim 7; it is characterized in that; with described patterned photoresist for mask; when etching described polysilicon layer; described etching stopping is in described polysilicon layer lower surface or protective layer; after forming offset side wall, wet etching is used to remove protective layer and the high-k dielectric layer of exposure.
9. the formation method of offset side wall as claimed in claim 7, is characterized in that, with described patterned photoresist for mask, when etching described polysilicon layer, described etching stopping, in high-k dielectric layer, after forming offset side wall, uses wet etching to remove the high-k dielectric layer exposed.
10. the formation method of offset side wall as claimed in claim 2, is characterized in that, before forming polysilicon layer on the substrate, form the first silicon oxide layer on the substrate, described polysilicon layer is formed on described first silicon oxide layer.
The formation method of 11. offset side walls as claimed in claim 2, is characterized in that, before described polysilicon layer forms patterned photoresist, described polysilicon layer forms hard mask layer, described patterned photoresist is formed on described hard mask layer.
The formation method of 12. offset side walls as claimed in claim 11, is characterized in that, before described hard mask layer forms patterned photoresist, described hard mask layer is formed with amorphous carbon, the second silicon oxide layer and anti-reflecting layer from the bottom to top successively.
The formation method of 13. offset side walls as claimed in claim 12, it is characterized in that, described anti-reflecting layer is siliceous anti-reflecting layer.
The formation method of 14. offset side walls as claimed in claim 7, is characterized in that, the material of described high-k dielectric layer is HfSiON, HfO
2, HfSiO, HfTaO, HfTiO, HfZrO, Al
2o
3, La
2o
3, ZrO
2, or LaAlO.
The formation method of 15. offset side walls as claimed in claim 7, is characterized in that, the material of described protective layer is TaN or TiN.
The formation method of 16. offset side walls as claimed in claim 11, is characterized in that, the material of described hard mask layer is silicon nitride or silicon oxynitride.
The formation method of 17. 1 kinds of transistors, is characterized in that, comprising:
The arbitrary described method of 1-16 is used to form offset side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310382850.8A CN104425272A (en) | 2013-08-28 | 2013-08-28 | Forming methods for offset side wall and transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310382850.8A CN104425272A (en) | 2013-08-28 | 2013-08-28 | Forming methods for offset side wall and transistor |
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|---|---|
| CN104425272A true CN104425272A (en) | 2015-03-18 |
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ID=52973942
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| CN201310382850.8A Pending CN104425272A (en) | 2013-08-28 | 2013-08-28 | Forming methods for offset side wall and transistor |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000621A1 (en) * | 1997-12-30 | 2002-01-03 | Robert H. Havemann | Enhancements to polysilicon gate |
| CN101290880A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing etching injury on lateral wall of polysilicon gate and manufacturing method of gate |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
| CN102087966A (en) * | 2009-12-04 | 2011-06-08 | 中芯国际集成电路制造(上海)有限公司 | Method for re-oxidizing grid and method for manufacturing semiconductor structure |
| CN102420116A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Method for eliminating recess defect of gate electrode |
-
2013
- 2013-08-28 CN CN201310382850.8A patent/CN104425272A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000621A1 (en) * | 1997-12-30 | 2002-01-03 | Robert H. Havemann | Enhancements to polysilicon gate |
| CN101290880A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing etching injury on lateral wall of polysilicon gate and manufacturing method of gate |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
| CN102087966A (en) * | 2009-12-04 | 2011-06-08 | 中芯国际集成电路制造(上海)有限公司 | Method for re-oxidizing grid and method for manufacturing semiconductor structure |
| CN102420116A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Method for eliminating recess defect of gate electrode |
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