CN104410407A - Adaptive digital phase-locked loop and phase locking method - Google Patents
Adaptive digital phase-locked loop and phase locking method Download PDFInfo
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Abstract
Provided in the invention is an adaptive digital phase-locked loop comprising a phase discriminator, a PI regulator, a conversion unit, a sampling unit, a frequency multiplier, and an integral transformation unit. The sampling unit is used for carrying out sampling on a three-phase power grid voltage by using a sampling frequency generated by the frequency multiplier; the integral transformation unit is used for generating a phase-lock output phase according to a phase-lock output frequency; the frequency multiplier is used for generating a sampling frequency according to the phase-lock output frequency. The sampling frequency is Nth times larger than the phase-lock output frequency, wherein the N is a positive integer. In addition, the invention also provides a corresponding phase locking method. With the adaptive digital phase-locked loop, a problem of large phase lock error of the existing phase-locked loop based on synchronization rotation coordinate transformation can be solved; the adaptive digital phase-locked loop can adapt to the power grid frequency change automatically; the rapid power grid phase tracking can be realized; and the phase locking precision can be improved.
Description
Technical field
The present invention relates to Phase Lock Technique field, more particularly, relate to a kind of adaptive digital phase-locked loop and phase-lock technique, be applied to grid-connected converter.
Background technology
The basic function of phase-locked loop is the phase place of following the tracks of, locking AC signal, and provides frequency, the amplitude information of OFF signal where necessary.In the control of grid-connected converter, need the phase information of Dynamic Acquisition line voltage, therefore, the performance of phase-locked loop directly affects the cutting-in control performance of current transformer.
Be the phase-locked accuracy and the response fast that effectively improve phase-locked loop at present in engineering, general employing digital closed loop Phase Lock Technique, its scheme mainly contains: based on the phase-locked loop of zero passage detection, based on the phase-locked loop of multiplication phase demodulation, based on the phase-locked loop of fast Fourier transform (DFT), and based on the phase-locked loop etc. of synchronous rotating angle.The structure basic simlarity of different Phase Lock Technique, Main Differences is the acquisition differed.Wherein, the difference based on the phase-locked loop of zero passage detection obtains and usually needs a primitive period, and dynamic response is poor, and in line voltage distortion situation, phase-locked error is comparatively large, therefore applies less in actual three-phase system.Input signal is multiplied with estimated signal by the phase-locked loop based on multiplication phase demodulation, and two harmonics wherein of filtering afterwards, draw phase difference value signal, difference is made to be 0 through closed-loop adjustment, thus realize phase-locked, but in the method, phase-locked bandwidth will limit by filter, can not respond fast.The problem that the dynamic response existed based on the Phase Lock Technique of DFT is slow.Said method is applied more in single phase system, but its dynamic response is difficult to the requirement meeting three-phase system.
In three-phase system, widely use the phase-locked loop based on synchronous rotating angle, utilizing the phase angle estimating to obtain to carry out synchronous rotating angle (also claiming dq conversion) to line voltage, obtaining the voltage power-less component (u for characterizing difference
q), regulated by controller, make this component be 0, thus reach phase-locked object, and dynamic property is better.
Realize the phase-locked loop based on synchronous rotating angle, need to carry out digital sample to line voltage.Traditional method adopts fixing sample frequency, and the integral multiple of electrical network rated frequency (50Hz) often.For the situation that mains frequency is substantially constant, this method accurately can calculate the idle component (u characterizing difference
q).But in the situation that mains frequency excursion is larger, if keep sample frequency constant, then the sampling number in each grid cycle is dynamic change, makes the idle component (u that sample-synchronous rotating coordinate transformation calculates
q) comparatively big error can be there is, also accurately cannot find grid phase zero point simultaneously.Therefore, this phase-lock technique is difficult to follow the tracks of grid phase fast when mains frequency excursion is larger, reduces phase-locked precision.For this defect, impact can be reduced by improving sample frequency.But this method cannot inherently be dealt with problems, meanwhile, in a lot of application scenarios, sample frequency is often limited.
Summary of the invention
The technical problem to be solved in the present invention is, accurately cannot find grid phase zero point, provide a kind of adaptive digital phase-locked loop and phase-lock technique for existing PHASE-LOCKED LOOP PLL TECHNIQUE when mains frequency excursion is larger.
The technical scheme that the present invention solves the problem there is provided a kind of adaptive digital phase-locked loop, comprise phase discriminator, pi regulator and converter unit, it is characterized in that, this adaptive digital phase-locked loop also comprises sampling unit, frequency multiplier and integral transformation unit, wherein, described sampling unit, samples to three-phase power grid voltage for the sample frequency generated with described frequency multiplier; Described phase discriminator, carries out synchronous rotating angle for the voltage of being sampled by described sampling unit, obtains the voltage power-less component u for characterizing difference
q; Described pi regulator, for carrying out PI adjustment, makes described voltage power-less component u
qlevel off to zero; Described converter unit, for generating phase-locked output frequency according to the output of pi regulator; Described integral transformation unit, for generating phase-locked output phase place according to described phase-locked output frequency; Described frequency multiplier, for generating sample frequency according to described phase-locked output frequency, and this sample frequency is N times of described phase-locked output frequency, and described N is positive integer.
In adaptive digital phase-locked loop of the present invention, described phase discriminator adopts CLARKE conversion and PARK conversion to realize coordinate transform, and the phase-locked output phase place that this phase discriminator exports with described integral transformation unit is for benchmark, extracts the voltage power-less component u for characterizing difference
qas the output of described phase discriminator, and in a kth sampling instant, described phase-locked output phase place is k* (2 π/N), wherein k=0,1 ..., N-1.
In adaptive digital phase-locked loop of the present invention, described phase-locked output frequency is that the output of described pi regulator is carried out being added the frequency obtained with the specified angular frequency of actual electric network.
Present invention also offers a kind of phase-lock technique, the method is applied in grid-connected converter, it is characterized in that, comprises the following steps:
A () is sampled to line voltage with the sample frequency set, obtain the line voltage after sampling;
B line voltage after sampling for benchmark with phase-locked output phase place, being carried out synchronous rotating angle, obtaining the voltage power-less component u for characterizing difference by ()
q;
C () carries out PI adjustment by pi regulator, make voltage power-less component u
qlevel off to zero, and generate phase-locked output frequency according to the output of described pi regulator;
D described phase-locked output frequency is obtained phase-locked output phase place through integral transformation by (), and generate the sample frequency of described setting according to described phase-locked output frequency, and wherein, the sample frequency of this setting is N times of described phase-locked output frequency, and N is positive integer.
In phase-lock technique of the present invention, in described step (b), described synchronous rotating angle comprises CLARKE conversion and PARK conversion, and in a kth sampling instant, it is k* (2 π/N), wherein k=0 that described phase-locked loop exports phase place, 1 ..., N-1.
In phase-lock technique of the present invention, described phase-locked output frequency is that the output of described pi regulator is carried out being added the frequency obtained with the specified angular frequency of actual electric network.
When mains frequency excursion is larger, there is the larger problem of phase-locked error in the phase-locked loop that adaptive digital phase-locked loop of the present invention can overcome based on synchronous rotating angle.And pass through according to phase-locked output frequency dynamic corrections sample frequency, thus automatically adapt to mains frequency change, realize following the tracks of grid phase fast, improve phase-locked precision.
Accompanying drawing explanation
Fig. 1 is the polar plot of single synchronous coordinate system software phase-lock loop of three-phase system.
Fig. 2 is the structural representation of adaptive digital phase-locked loop embodiment of the present invention.
Fig. 3 is the sampling instant in a grid cycle.
Fig. 4 is the flow chart of phase-lock technique embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, be the polar plot of single synchronous coordinate system software phase-lock loop of three-phase system.Carry out to three-phase system the conversion that static coordinate is tied to rotating coordinate system, utilize the control synchronously settling down to realize three-phase phase-locked loop of rotating coordinate system, virtual voltage vector is U, with d axle homophase, and U
pllfor the voltage vector that phase-locked loop exports, θ is the vector angle of virtual voltage vector, and θ is the voltage vector angle that phase-locked loop exports, and obviously, works as U
plloverlap completely with U, namely during θ=θ, phase-locked loop is accurately phase-locked.
As shown in Figure 2, be the structural representation of adaptive digital phase-locked loop embodiment of the present invention.This adaptive digital phase-locked loop is applied in grid-connected converter, comprise sampling unit 1, phase discriminator 2, adjuster 3, converter unit 4, frequency multiplier 5 and integral transformation unit 6, above-mentioned sampling unit 1, phase discriminator 2, adjuster 3, converter unit 4, frequency multiplier 5 and integral transformation unit 6 can by hardware, software or its be bonded.
The input signal of sampling unit 1 is three-phase power grid voltage, and sampling unit 1 pair of three-phase power grid voltage is sampled; The input signal of phase discriminator 2 comprises the output of sampling unit 1, and phase discriminator 2 adopts coordinate transform, and for realizing the phase discrimination function of phase-locked loop, comprise CLARKE conversion and PARK conversion, the input signal of phase discriminator 2 also comprises phase-locked output phase place
Be appreciated that the three-phase power grid voltage after the sampling that sampling unit 1 exports carries out CLARKE conversion and PARK conversion respectively, obtain the voltage under dq coordinate system, be expressed as follows formula:
wherein U
m, ω, ω
0,
be expressed as the initial phase difference that the amplitude of line voltage, line voltage angular speed, the estimated angular velocity of phase-locked loop, line voltage vector actual angle and phase-locked loop estimate angle.
Extract the output of above-mentioned q shaft voltage as phase discriminator 2.
The input signal of adjuster 3 is q shaft voltage, and adjuster 3 is pi regulator, and adjuster 3 pairs of q shaft voltages carry out PI adjustment, make q shaft voltage level off to zero.
The output of adjuster 3 and the specified angular frequency of actual electric network
ff(corresponding to actual electric network rated frequency) is added, and obtains pilot angle frequencies omega
o(corresponding to control frequency).
Pilot angle frequencies omega
ophase-locked output frequency f is obtained through converter unit 4
pll, wherein, the transfer function of converter unit 4 is 1/2 π.
Pilot angle frequencies omega
oalso obtain phase-locked output phase place through integral transformation unit 6
wherein, integral transformation unit 6 comprises integrator and mod computing, and output and 2 π of integrator carry out mod computing.
The input of frequency multiplier 5 connects the output of converter unit 4, and the output of frequency multiplier 5 acts on sampling unit 1, and the transfer function of frequency multiplier 5 is expressed as N, and wherein N is positive integer.
Be appreciated that phase-lock-ring output frequency f
pllthe frequency obtaining exporting through frequency multiplier 5 is N*f
pll, the frequency effect of this output in sampling unit 1, i.e. the sample frequency f of sampling unit 1
sfor N*f
pll, in this case, the sample frequency f of current transformer
sfor N phase-lock-ring output frequency f doubly
pll.
Meanwhile, make the sampling number of current transformer in each grid cycle be N, and the time interval of sampled point can be inconsistent, as shown in Figure 3, is the sampling instant in a grid cycle.During the sampling instant of kth in each grid cycle, phase-locked output phase place
for k* (2 π/N), wherein k=0,1, ..., N-1, this phase-locked output phase place is supplied to phase discriminator 2, as synchronizing datum signal, can find out, the sample frequency of current transformer is determined by control frequency, in such situation, can ensure the quick adjustment of phase-locked loop, accurately phase-locked, simultaneously can continuous sampling rate adjusting.
As shown in Figure 4, be the flow chart of phase-lock technique embodiment of the present invention, the method is applied in grid-connected converter, comprises the following steps:
S41, with the sample frequency set, digital sample is carried out to line voltage, obtain the line voltage after sampling;
S42, with phase-locked output phase place
for benchmark, the line voltage after sampling being carried out synchronous rotating angle, obtaining the voltage power-less component u for characterizing difference
q;
S43, carry out PI adjustment by pi regulator, make voltage power-less component u
qlevel off to zero;
S44, by the output angle frequency of pi regulator and the specified angular frequency of electrical network
ffbe added as pilot angle frequencies omega
o, carry out conversion and obtain phase-locked output frequency f
pll, and according to phase-locked output frequency f
pll, obtain phase-locked output phase place through integral transformation
and according to phase-locked output frequency f
pllgenerate the sample frequency f of setting
s, wherein, the sample frequency f of this setting
sfor phase-locked output frequency f
plln doubly, N is positive integer.
In the above-mentioned methods, synchronous rotating angle comprises CLARKE conversion and PARK conversion, and in a kth sampling instant, phase-locked loop exports phase place
for k* (2 π/N), wherein k=0,1 ..., N-1, N are positive integer.
Said method is when mains frequency excursion is very large, due to sample frequency and the proportional relation of control frequency, can constantly adjust, and with phase-locked output phase place for benchmark, line voltage after sampling is carried out synchronous rotating angle, and making can real-time tracking grid phase.
The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (6)
1. an adaptive digital phase-locked loop, comprise phase discriminator, pi regulator and converter unit, it is characterized in that, this adaptive digital phase-locked loop also comprises sampling unit, frequency multiplier and integral transformation unit, wherein, described sampling unit, samples to three-phase power grid voltage for the sample frequency generated with described frequency multiplier; Described phase discriminator, carries out synchronous rotating angle for the voltage of being sampled by described sampling unit, obtains the voltage power-less component u for characterizing difference
q; Described pi regulator, for carrying out PI adjustment, makes described voltage power-less component u
qlevel off to zero; Described converter unit, for generating phase-locked output frequency according to the output of pi regulator; Described integral transformation unit, for generating phase-locked output phase place according to described phase-locked output frequency; Described frequency multiplier, for generating sample frequency according to described phase-locked output frequency, and this sample frequency is N times of described phase-locked output frequency, and described N is positive integer.
2. adaptive digital phase-locked loop according to claim 1, it is characterized in that, described phase discriminator adopts CLARKE conversion and PARK conversion to realize coordinate transform, and the phase-locked output phase place that this phase discriminator exports with described integral transformation unit is for benchmark, extracts the voltage power-less component u for characterizing difference
qas the output of described phase discriminator, and in a kth sampling instant, described phase-locked output phase place is k* (2 π/N), wherein k=0,1 ..., N-1.
3. adaptive digital phase-locked loop according to claim 1, is characterized in that, described phase-locked output frequency is that the output of described pi regulator is carried out being added the frequency obtained with the specified angular frequency of actual electric network.
4. a phase-lock technique, the method is applied in grid-connected converter, it is characterized in that, comprises the following steps:
A () is sampled to line voltage with the sample frequency set, obtain the line voltage after sampling;
B line voltage after sampling for benchmark with phase-locked output phase place, being carried out synchronous rotating angle, obtaining the voltage power-less component u for characterizing difference by ()
q;
C () carries out PI adjustment by pi regulator, make voltage power-less component u
qlevel off to zero, and generate phase-locked output frequency according to the output of described pi regulator;
D described phase-locked output frequency is obtained phase-locked output phase place through integral transformation by (), and generate the sample frequency of described setting according to described phase-locked output frequency, and wherein, the sample frequency of this setting is N times of described phase-locked output frequency, and N is positive integer.
5. phase-lock technique according to claim 4, it is characterized in that, in described step (b), described synchronous rotating angle comprises CLARKE conversion and PARK conversion, and in a kth sampling instant, it is k* (2 π/N) that described phase-locked loop exports phase place, wherein k=0,1 ..., N-1.
6. phase-lock technique according to claim 4, is characterized in that, described phase-locked output frequency is that the output of described pi regulator is carried out being added the frequency obtained with the specified angular frequency of actual electric network.
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| CN109547016A (en) * | 2018-11-30 | 2019-03-29 | 中国科学院广州能源研究所 | The adaptive single-phase phase-locked loop of frequency based on virtual three phase algorithm |
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