CN104410407B - A kind of adaptive digital phaselocked loop and phase-lock technique - Google Patents
A kind of adaptive digital phaselocked loop and phase-lock technique Download PDFInfo
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Abstract
The invention provides a kind of adaptive digital phaselocked loop, including phase discriminator, pi regulator and converter unit, the adaptive digital phaselocked loop also includes sampling unit, frequency multiplier and integral transformation unit, wherein, the sampling unit, the sample frequency for being generated with the frequency multiplier sample to three-phase power grid voltage；The integral transformation unit, for according to the lock phase output frequency generation lock phase output phase；The frequency multiplier, for generating sample frequency according to the lock phase output frequency, and the sample frequency is N times of the lock phase output frequency, and the N is positive integer.Present invention also offers a kind of corresponding phase-lock technique.The adaptive digital phaselocked loop of the present invention can overcome the phaselocked loop based on synchronous rotating angle the problem of lock phase error is larger to be present, can adapt to mains frequency change automatically, realize quick tracking grid phase, improve lock phase precision.
Description
Technical field
The present invention relates to Phase Lock Technique field, more specifically to a kind of adaptive digital phaselocked loop and phase-lock technique,
Applied to grid-connected converter.
Background technology
The basic function of phaselocked loop is tracking, locks the phase of AC signal, and is provided with the frequency of OFF signal when necessary
Rate, amplitude information., it is necessary to the phase information of dynamic access line voltage in the control of grid-connected converter, therefore, phaselocked loop
Performance directly affects the cutting-in control performance of current transformer.
It is the degree of accuracy of lock phase and the quick response for effectively improving phaselocked loop in engineering at present, is typically locked using digital closed loop
Phase technology, its scheme mainly have：Phaselocked loop based on zero passage detection, based on the phaselocked loop of multiplication phase demodulation, based on fast Fourier
Convert the phaselocked loop of (DFT), and phaselocked loop based on synchronous rotating angle etc..The basic phase of structure of different Phase Lock Techniques
Seemingly, Main Differences are the acquisition differed.Wherein, the difference of the phaselocked loop based on zero passage detection, which obtains, usually requires a fundamental wave
In the cycle, dynamic response is poor, and lock phase error is larger in the case of line voltage distortion, therefore is applied in actual three-phase system
It is less.Input signal with estimating signal multiplication, is filtered out two harmonic therein, obtained by the phaselocked loop based on multiplication phase demodulation afterwards
Go out phase difference value signal, make difference be 0 by closed loop regulation, so as to realize lock phase, but phase bandwidth is locked in this method to be filtered
Ripple device limits, it is impossible to quick response.Based on the problem of dynamic response is slow existing for DFT Phase Lock Technique.The above method is single-phase
Using more in system, but its dynamic response is difficult to the requirement that meets three-phase system.
The phaselocked loop based on synchronous rotating angle is widely used in three-phase system, the phase angle pair obtained using estimation
Line voltage synchronizes rotating coordinate transformation (also referred to as dq conversion), obtains the voltage power-less component (u for characterizing differenceq),
Adjusted by controller so that the component is 0, and so as to reach the purpose of lock phase, and dynamic property is preferable.
The phaselocked loop based on synchronous rotating angle is realized, it is necessary to carry out digital sample to line voltage.Tradition is done
Method is using fixed sample frequency, and the often integral multiple of power network rated frequency (50Hz).For mains frequency substantially not
The situation of change, this method can accurately calculate the reactive component (u for characterizing differenceq).But mains frequency excursion compared with
Big situation, if keeping, sample frequency is constant, and the sampling number in each grid cycle is dynamic change so that sampling is same
Reactive component (the u that step rotating coordinate transformation is calculatedq) there can be larger error, while also can not accurately find grid phase
Zero point.Therefore, this phase-lock technique is difficult to quickly track grid phase in the case where mains frequency excursion is larger, reduces
Lock phase precision.For this defect, can be influenceed by improving sample frequency to reduce.But this method can not be inherently
Solve the problems, such as, meanwhile, often it is limited in many application scenario sample frequencys.
The content of the invention
The technical problem to be solved in the present invention is, larger in mains frequency excursion for existing PHASE-LOCKED LOOP PLL TECHNIQUE
In the case of can not accurately find grid phase zero point, there is provided a kind of adaptive digital phaselocked loop and phase-lock technique.
Technical proposal that the invention solves the above-mentioned problems there is provided a kind of adaptive digital phaselocked loop, including phase discriminator,
Pi regulator and converter unit, it is characterised in that the adaptive digital phaselocked loop also includes sampling unit, frequency multiplier and integration and become
Unit is changed, wherein, the sampling unit, the sample frequency for being generated with the frequency multiplier is adopted to three-phase power grid voltage
Sample；The phase discriminator, the voltage for the sampling unit to be sampled synchronize rotating coordinate transformation, obtain for characterizing phase
The voltage power-less component u of differenceq；The pi regulator, for carrying out PI regulations, make the voltage power-less component uqLevel off to zero；Institute
Converter unit is stated, for generating lock phase output frequency according to the output of pi regulator, the lock phase output frequency is adjusted for the PI
The output of section device is added obtained frequency with the specified angular frequency of actual electric network；The integral transformation unit, for according to institute
State lock phase output frequency generation lock phase output phase；The frequency multiplier, for according to the lock phase output frequency generation sampling frequency
Rate, and the sample frequency is N times of the lock phase output frequency, the N is positive integer.
In the adaptive digital phaselocked loop of the present invention, the phase discriminator is realized and sat using CLARKE conversion and PARK conversion
Mark conversion, and on the basis of the lock phase output phase that export by the integral transformation unit of the phase discriminator, extract and differed for characterizing
Voltage power-less component uqAs the output of the phase discriminator, and in k-th of sampling instant, the lock phase output phase is k* (2
π/N), wherein k=0,1 ..., N-1.
Present invention also offers a kind of phase-lock technique, this method is applied in grid-connected converter, it is characterised in that including with
Lower step：
(a) line voltage is sampled with the sample frequency of setting, the line voltage after being sampled；
(b) on the basis of locking phase output phase, the line voltage after sampling is synchronized into rotating coordinate transformation, used
In the voltage power-less component u for characterizing differenceq；
(c) PI regulations are carried out by pi regulator, makes voltage power-less component uqLevel off to zero, and according to the pi regulator
Output generation lock phase output frequency, output and actual electric network specified angular frequency of the lock phase output frequency for the pi regulator
Rate is added obtained frequency；
(d) the lock phase output frequency is obtained by integral transformation locking phase output phase, and mutually exported according to the lock
Frequency generates the sample frequency of the setting, wherein, the sample frequency set is N times of the lock phase output frequency, and N is just
Integer.
In the phase-lock technique of the present invention, in the step (b), the synchronous rotating angle converts including CLARKE
Converted with PARK, and in k-th of sampling instant, the lock phase output phase is k* (2 π/N), wherein k=0,1 ..., N-1.
In the case where mains frequency excursion is larger, adaptive digital phaselocked loop of the invention can be overcome based on same
The problem of lock phase error is larger be present in the phaselocked loop for walking rotating coordinate transformation.And by according to lock phase output frequency dynamic corrections
Sample frequency, so as to adapt to mains frequency change automatically, quick tracking grid phase is realized, improves lock phase precision.
Brief description of the drawings
Fig. 1 is the polar plot of single synchronous coordinate system software phase-lock loop of three-phase system.
Fig. 2 is the structural representation of adaptive digital phaselocked loop embodiment of the present invention.
Fig. 3 is the sampling instant in a grid cycle.
Fig. 4 is the flow chart of phase-lock technique embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.
As shown in figure 1, the polar plot of single synchronous coordinate system software phase-lock loop for three-phase system.Three-phase system is carried out quiet
Only coordinate system utilizes synchronously settling down to realize the control of three-phase phase-locked loop for rotating coordinate system, reality to the conversion of rotating coordinate system
Border voltage vector is U, with the same phase of d axles, UpllFor the voltage vector of phaselocked loop output, θ is the vector angle of virtual voltage vector,It is the voltage vector angle of phaselocked loop output, it is clear that work as UpllIt is completely superposed with U, i.e.,When, phaselocked loop accurately locks phase.
As shown in Fig. 2 the structural representation for adaptive digital phaselocked loop embodiment of the present invention.The adaptive digital locks phase
Ring is applied in grid-connected converter, including sampling unit 1, phase discriminator 2, adjuster 3, converter unit 4, frequency multiplier 5 and integration become
Unit 6 is changed, above-mentioned sampling unit 1, phase discriminator 2, adjuster 3, converter unit 4, frequency multiplier 5 and integral transformation unit 6 can be by hard
Part, software or its be bonded.
The input signal of sampling unit 1 is three-phase power grid voltage, and sampling unit 1 samples to three-phase power grid voltage；Mirror
The input signal of phase device 2 includes the output of sampling unit 1, and phase discriminator 2 uses coordinate transform, for realizing the phase demodulation work(of phaselocked loop
Can, including CLARKE conversion and PARK conversion, the input signal of phase discriminator 2 is also including lock phase output phase
It is appreciated that the three-phase power grid voltage after the sampling that sampling unit 1 exports carries out CLARKE conversion and PARK respectively
Conversion, obtains the voltage under dq coordinate systems, is expressed as follows formula：
Wherein Um、ω、ω0、It is expressed as amplitude, the power network of line voltage
Voltage angular speed, the estimated angular velocity of phaselocked loop, line voltage vector actual angle and the initial phase of phaselocked loop estimation angle
Difference.
Extract output of the above-mentioned q shaft voltages as phase discriminator 2.
The input signal of adjuster 3 is q shaft voltages, and adjuster 3 is pi regulator, and adjuster 3 carries out PI tune to q shaft voltages
Section, q shaft voltages are made to level off to zero.
The output end of adjuster 3 and the specified angular frequency of actual electric networkff(corresponding to actual electric network rated frequency) carries out phase
Add, obtain controlling angular frequencyo(corresponding to control frequency).
Control angular frequencyoObtain locking phase output frequency f by converter unit 4pll, wherein, the transmission letter of converter unit 4
Number is 1/2 π.
Control angular frequencyoAlso obtain locking phase output phase by integral transformation unit 6Wherein, integral transformation unit 6
Including integrator and mod computings, the output of integrator carries out mod computings with 2 π.
The output end of the input connection converter unit 4 of frequency multiplier 5, the output end of frequency multiplier 5 act on sampling unit 1,
The transmission function of frequency multiplier 5 is expressed as N, and wherein N is positive integer.
It is appreciated that phase-lock-ring output frequency fpllThe frequency exported by frequency multiplier 5 is N*fpll, the frequency of the output
Rate acts on the sample frequency f of sampling unit 1, i.e. sampling unit 1sFor N*fpll, in this case, the sample frequency f of current transformers
For N times of phase-lock-ring output frequency fpll。
Meanwhile it is N to make the sampling number of current transformer in each grid cycle, and the time interval of sampled point can differ
Cause, as shown in figure 3, being the sampling instant in a grid cycle.During k-th of sampling instant in each grid cycle, lock
Phase output phaseFor k* (2 π/N), wherein k=0,1 ..., N-1, the lock phase output phase is supplied to phase discriminator 2, as synchronization
Reference signal, it can be seen that the sample frequency of current transformer determines by control frequency, so in the case of, can guarantee that the fast of phaselocked loop
Velocity modulation section, phase is accurately locked, while can continuous sampling rate adjusting.
As shown in figure 4, being the flow chart of phase-lock technique embodiment of the present invention, this method is applied in grid-connected converter, bag
Include following steps：
S41, with the sample frequency of setting to line voltage carry out digital sample, the line voltage after being sampled；
S42, to lock phase output phaseOn the basis of, the line voltage after sampling is synchronized into rotating coordinate transformation, obtained
For characterizing the voltage power-less component u of differenceq；
S43, by pi regulator carry out PI regulations, make voltage power-less component uqLevel off to zero；
S44, the specified angular frequency of output angular frequency and power network by pi regulatorffIt is added as control angular frequencyo, enter
Line translation obtains locking phase output frequency fpll, and according to lock phase output frequency fpll, obtain locking phase output phase by integral transformationAnd according to lock phase output frequency fpllGenerate the sample frequency f of settings, wherein, the sample frequency f of the settingsMutually exported for lock
Frequency fpllN times, N is positive integer.
In the above-mentioned methods, synchronous rotating angle includes CLARKE conversion and PARK conversion, and when sampling for k-th
Carve, phaselocked loop output phaseFor k* (2 π/N), wherein k=0,1 ..., N-1, N are positive integer.
The above method, can due to sample frequency relation proportional to control frequency when mains frequency excursion is very big
Constantly adjustment, and on the basis of locking phase output phase, the line voltage after sampling is synchronized into rotating coordinate transformation so that energy
Real-time tracking grid phase.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
It is defined.
Claims (4)
1. a kind of adaptive digital phaselocked loop, including phase discriminator, pi regulator and converter unit, it is characterised in that this is adaptive
Digital phase-locked loop also includes sampling unit, frequency multiplier and integral transformation unit, wherein, the sampling unit, for described times
The sample frequency of frequency device generation samples to three-phase power grid voltage；The phase discriminator, for sample the sampling unit
Voltage synchronizes rotating coordinate transformation, obtains the voltage power-less component u for characterizing differenceq；The pi regulator, be used for into
Row PI is adjusted, and makes the voltage power-less component uqLevel off to zero；The converter unit, for being generated according to the output of pi regulator
Phase output frequency is locked, the lock phase output frequency is added for the output of the pi regulator with the specified angular frequency of actual electric network
Obtained frequency；The integral transformation unit, for according to the lock phase output frequency generation lock phase output phase；The frequency multiplication
Device, for generating sample frequency according to the lock phase output frequency, and the sample frequency is N times of the lock phase output frequency,
The N is positive integer.
2. adaptive digital phaselocked loop according to claim 1, it is characterised in that the phase discriminator is converted using CLARKE
Coordinate transform is realized with PARK conversion, and on the basis of the lock phase output phase that is exported by the integral transformation unit of the phase discriminator,
Extract the voltage power-less component u for characterizing differenceqAs the output of the phase discriminator, and in k-th of sampling instant, the lock
Phase output phase is k* (2 π/N), wherein k=0,1 ..., N-1.
3. a kind of phase-lock technique, this method is applied in grid-connected converter, it is characterised in that comprises the following steps：
(a) line voltage is sampled with the sample frequency of setting, the line voltage after being sampled；
(b) on the basis of locking phase output phase, the line voltage after sampling is synchronized into rotating coordinate transformation, obtained for table
Levy the voltage power-less component u of differenceq；
(c) PI regulations are carried out by pi regulator, makes voltage power-less component uqLevel off to zero, and according to the defeated of the pi regulator
Lock phase output frequency is born into, the lock phase output frequency enters for the output of the pi regulator with the specified angular frequency of actual electric network
Row is added obtained frequency；
(d) the lock phase output frequency is obtained by integral transformation locking phase output phase, and according to the lock phase output frequency
The sample frequency of the setting is generated, wherein, for the sample frequency set as N times of the lock phase output frequency, N is just whole
Number.
4. phase-lock technique according to claim 3, it is characterised in that in the step (b), the synchronously rotating reference frame becomes
Change including CLARKE conversion and PARK conversion, and in k-th of sampling instant, the lock phase output phase is k* (2 π/N), wherein k
=0,1 ..., N-1.
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| CN106707271B (en) * | 2015-11-16 | 2019-04-16 | 南京理工大学 | A kind of adaptive angleonly tracking method based on digital phase-locked loop |
| CN106911329A (en) * | 2017-02-23 | 2017-06-30 | 国网江西省电力公司电力科学研究院 | A kind of single-phase phase-locked loop based on FPGA |
| CN109980678B (en) * | 2017-12-28 | 2022-12-16 | 北京金风科创风电设备有限公司 | Phase locking device, phase locking control method and wind generating set |
| CN108776254B (en) * | 2018-09-05 | 2020-08-28 | Tcl空调器(中山)有限公司 | Amplitude detection method, motor drive device, storage medium, and apparatus |
| CN109547016B (en) * | 2018-11-30 | 2022-10-28 | 中国科学院广州能源研究所 | Frequency self-adaptive single-phase-locked loop based on virtual three-phase algorithm |
| CN110308326A (en) * | 2019-07-15 | 2019-10-08 | 国网山西省电力公司电力科学研究院 | A method of open loop can be improved and surveys phase algorithm noiseproof feature |
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