CN104410132A

CN104410132A - Voltage balancing device of supercapacitor and control method of voltage balancing device

Info

Publication number: CN104410132A
Application number: CN201410798400.1A
Authority: CN
Inventors: 段建东; 李树生; 孙力; 王志刚; 国海峰; 王令金; 李寻迹; 郭安东; 张润松; 刘龙海; 赵克; 吴凤江; 安群涛
Original assignee: Harbin Institute of Technology
Current assignee: Harbin Institute of Technology
Priority date: 2014-12-19
Filing date: 2014-12-19
Publication date: 2015-03-11
Anticipated expiration: 2034-12-19
Also published as: CN104410132B

Abstract

The invention provides a voltage balancing device of a supercapacitor and a control method of the voltage balancing device, relates to the energy storage technology of the supercapacitor, and aims to solve the problem that the service life of the supercapacitor is shortened due to inconsistent voltage of shunt sections of the supercapacitor. According to the voltage balancing device of the supercapacitor and the control method of the voltage balancing device, each energy storage unit is equipped with a balance controller which is controlled by a master controller, so that voltage of the shunt sections of the supercapacitor is balanced, consistent voltage of the shunt sections is kept, the service life of the supercapacitor is prolonged, and the energy storage quality of the supercapacitor is improved; and besides, the voltage balancing device of the supercapacitor and the control method of the voltage balancing device have the advantages that detection for voltage of the shunt sections of the supercapacitor is accurate, charge and discharge efficiency of the supercapacitor is high, the voltage balancing speed is high, the voltage consistency is good, capacity and internal resistance of the supercapacitor are identified accurately, module power density is high and the like.

Description

Voltage balancing device of super capacitor and control method of voltage balancing device

Technical Field

The invention relates to an energy storage technology of a super capacitor.

Background

Super capacitors are electrochemical elements developed from the seventh and eighties of the last century that store energy through polarized electrolytes. The method has the outstanding advantages of high power density, short charge-discharge time, long cycle life and wide working temperature range, and is one of the electric double layer capacitors which are put into mass production in the world and have the largest capacity. However, the super capacitor also has some problems, such as inconsistent parallel voltage saving, shortened service life of the super capacitor, etc.

Disclosure of Invention

The invention aims to solve the problem that the service life of a super capacitor is shortened due to inconsistent parallel connection voltage of the super capacitor, and provides a voltage balancing device of the super capacitor and a control method of the voltage balancing device.

The voltage balancing device of the super capacitor comprises a main controller, a total current/voltage detection unit, a plurality of balance controllers and a DC-DC power supply module;

the DC-DC power supply module provides working power supply for the main controller, the total current/voltage detection unit and the plurality of balance controllers;

the main controller is connected with the plurality of balance controllers and the total current/voltage detection unit;

each balance controller is used for measuring the terminal voltage of n parallel nodes of the super capacitor and charging the n parallel nodes;

the total current/voltage detection unit is used for detecting the total voltage and the total current of the output port of the super capacitor.

The balance controller comprises n parallel-connection balance units, m analog switching circuits, an AD processing circuit, a balance control processor, a temperature signal processing circuit, an optical coupling isolation communication circuit and an isolation power supply, wherein m is smaller than n;

each parallel-link balancing unit is used for charging one parallel link, and the control signal input end of each parallel-link balancing unit is connected with the charging control signal output end of the balance control processor;

each analog switching circuit is used for measuring the terminal voltage of a plurality of parallel joints, m analog switching circuits measure the terminal voltages of n parallel joints in total, and the measurement result is sent to the balance control processor through the AD processing circuit;

the output end of the temperature signal processing circuit is connected with the temperature signal input end of the balance control processor, and the input end of the temperature signal processing circuit is used for being connected with a temperature sensor;

the temperature sensor is used for measuring the temperature of the energy storage unit and sending a measurement result to the balance control processor through the temperature signal processing circuit, and the energy storage unit comprises a balance controller and a parallel connection connected with the balance controller;

the refrigeration control signal output end of the balance control processor is used for being connected with the control signal input end of the fan;

and the balance control processor performs data transmission with the main controller through a CAN signal transmission line.

The equalization control processor is embedded with an equalization control interruption submodule realized by software, and the module comprises the following units:

a parallel voltage-saving reading unit: continuously reading and storing n parallel voltage values sent by m analog switching circuits; starting the parallel voltage-saving sequencing unit after the unit finishes running;

parallel voltage-saving sequencing unit: sequencing the n parallel connection voltage values according to the sequence from top to bottom; starting the whole charging instruction judging unit after the unit finishes running;

integral charging instruction judgment unit: judging whether an integral charging instruction sent by the main controller is received or not, starting an integral charging instruction sending unit if the judgment result is yes, and starting a first maximum voltage difference judgment unit if the judgment result is no;

integral charging instruction transmitting unit: sending a charging instruction to the n parallel-joint balancing units; starting an integral charging end instruction judging unit after the unit finishes running;

an overall charging end instruction determination unit: judging whether an integral charging finishing instruction sent by the main controller is received or not, and starting a stopping integral charging instruction sending unit when the judgment result is yes; restarting the whole charging ending instruction judging unit when the judging result is negative;

stop the whole charging instruction transmitting unit: sending a charging stopping instruction to the n parallel-joint balancing units; starting a first maximum voltage difference judgment unit after the unit finishes running;

a first maximum voltage difference judgment unit: judging whether the difference between the maximum value and the minimum value in the n parallel-connection voltage values is larger than delta U or not, starting the selective charging instruction sending unit when the judgment result is yes, and starting the identification unit when the judgment result is no;

a selective charging instruction transmitting unit: sending a charging instruction to parallel joint balancing units corresponding to the three parallel joints with the lowest voltage values; starting a second maximum voltage difference judgment unit after the unit finishes running;

a second maximum voltage difference determination unit: judging whether the difference between the maximum value and the minimum value in the n parallel-connection voltage values is larger than delta U, restarting a second maximum voltage difference judging unit if the judgment result is yes, and starting a selective charging stopping instruction sending step if the judgment result is not;

a step of sending a stop selective charging command: sending a charging stopping instruction to the parallel joint balancing units corresponding to the three parallel joints; and starting the identification unit after the unit finishes running;

an identification unit: calculating the capacity and the internal resistance of the super capacitor; and starting the identification result sending unit after the unit finishes running;

an identification result transmitting unit: sending the parallel connection node capacity and the internal resistance calculated by the identification unit to a main controller; and starting the temperature control unit after the unit finishes running;

a temperature control unit: controlling the temperature of the energy storage unit within the temperature range of normal operation of the energy storage unit; and starting the whole charging instruction judgment unit after the unit operation is finished.

The control method of the voltage balancing device of the super capacitor comprises the following steps:

reading parallel connection voltage: continuously reading and storing n parallel voltage values sent by m analog switching circuits; and after the step is finished, executing a parallel voltage-saving sequencing step;

parallel voltage-saving sequencing: sequencing the n parallel connection voltage values according to the sequence from top to bottom; and executing the whole charging instruction judging step after the step is finished;

and an integral charging instruction judging step: judging whether an integral charging instruction sent by the main controller is received or not, executing an integral charging instruction sending step when the judgment result is yes, and executing a first maximum voltage difference judging step when the judgment result is no;

and sending an overall charging instruction: sending a charging instruction to the n parallel-joint balancing units; and executing the whole charging end instruction judging step after the step is finished;

and an integral charging end instruction judging step: judging whether an integral charging finishing instruction sent by the main controller is received or not, and executing an integral charging stopping instruction sending step when the judgment result is yes; re-executing the whole charging ending instruction judging step when the judging result is negative;

stopping sending the integral charging command: sending a charging stopping instruction to the n parallel-joint balancing units; and executing a first maximum voltage difference judging step after the step is finished;

a first maximum voltage difference judging step: judging whether the difference between the maximum value and the minimum value in the n parallel-connection voltage values is larger than delta U or not, executing the selective charging instruction sending step when the judgment result is yes, and executing the identification step when the judgment result is no;

a selective charging instruction sending step: sending a charging instruction to parallel joint balancing units corresponding to the three parallel joints with the lowest voltage values; and executing a second maximum voltage difference judging step after the step is finished;

a second maximum voltage difference judging step: judging whether the difference between the maximum value and the minimum value in the n parallel-connection voltage values is larger than delta U, re-executing the second maximum voltage difference judging step when the judgment result is yes, and executing the selective charging stopping instruction sending step when the judgment result is no;

a step of sending a stop selective charging command: sending a charging stopping instruction to the parallel joint balancing units corresponding to the three parallel joints; and performing an identification step after the step is finished;

identification: calculating the capacity and the internal resistance of the super capacitor; and after the step is finished, executing an identification result sending step;

an identification result sending step: sending the parallel connection node capacity and the internal resistance calculated in the identification step to a main controller; and after the step is finished, executing a temperature control step;

temperature control: controlling the temperature of the energy storage unit within the temperature range of normal operation of the energy storage unit; and returning to the step of judging the overall charging command after the step line is finished.

According to the voltage balancing device of the super capacitor and the control method of the voltage balancing device, a balancing controller is configured for each energy storage unit, the balancing controller is controlled by a main controller to balance the voltage of each parallel connection of the super capacitor, so that the voltage of each parallel connection is kept consistent, the service life of the super capacitor is prolonged, and the energy storage quality of the super capacitor is improved. The DC-DC power supply module converts the voltage of the capacitor into a 24V constant voltage power supply to supplement the voltage difference for the energy storage unit. The device has the advantages of accurate detection of the parallel connection voltage-saving of the super capacitor, high charging and discharging efficiency of the super capacitor, high voltage balancing speed, good voltage consistency, accurate identification of the capacity and the internal resistance of the super capacitor, high module power density and the like.

Drawings

Fig. 1 is a schematic block diagram of an ultracapacitor voltage equalizing device according to an embodiment;

FIG. 2 is a functional block diagram of a host controller chip according to a first embodiment;

FIG. 3 is a schematic block diagram of an energy storage unit according to a second embodiment;

FIG. 4 is a functional block diagram of an equalization control processor according to a second embodiment;

fig. 5 is a functional block diagram of an AD processing circuit in the third embodiment;

fig. 6 is a circuit configuration diagram of an analog switching circuit and an AD processing circuit in the third embodiment;

FIG. 7 is a circuit configuration diagram of a temperature signal processing circuit according to a fourth embodiment;

fig. 8 is a flowchart of a control method in the tenth embodiment;

FIG. 9 is a flowchart showing a temperature control step in an eleventh embodiment;

FIG. 10 is an equivalent circuit diagram of the parallel connection of the capacitor capacity and the internal resistance in the twelfth embodiment;

FIG. 11 is a schematic diagram of voltage calculation in the twelfth embodiment;

FIG. 12 is a flowchart illustrating an identification method according to a twelfth embodiment;

fig. 13 is a circuit configuration diagram of a DC-DC power supply module in an eighth embodiment.

Detailed Description

The first embodiment is as follows: the present embodiment is described with reference to fig. 1 and fig. 2, and the supercapacitor voltage balancing device according to the present embodiment includes a main controller 1, a total current/voltage detection unit 2, a plurality of balancing controllers 3, and a DC-DC power supply module 4;

the DC-DC power supply module 4 provides working power supply for the main controller 1, the total current/voltage detection unit 2 and the plurality of balance controllers 3;

the main controller 1 is connected with the plurality of balance controllers 3 and the total current/voltage detection unit 2;

each balance controller 3 is used for measuring the terminal voltage of n parallel nodes of the super capacitor and charging the n parallel nodes;

the total current/voltage detection unit 2 is used for detecting the total voltage and the total current of the output port of the super capacitor.

In the present embodiment, the capacitors connected to the balance controller 3 are connected in parallel by supercapacitors. The chip of the main controller 1 selects an ARM chip with the model of STM32F407, the structure of the chip is Cortex-M4, a 32-bit MCU is provided with an FPU unit, 210DMIPS is provided, the number of the MCU is up to 1MB FLASH/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 timers, 3 ADCs, 15 communication interfaces and a camera, and the clock frequency is 168 MHz. The main controller 1 is responsible for sampling the total current and the total voltage of the energy storage unit, an LEM current sensor is selected as the current sensor, the output voltage is 5V, and the current is sent into a 16-bit AD sampling chip after passing through a sampling processing circuit. The voltage sensor adopts an LEM voltage sampling module, the output voltage is 5V, and the voltage is transmitted into a 16-bit AD sampling chip with the model number of AD32680 after passing through a sampling processing circuit. The energy storage unit comprises a balance controller 3 and a parallel connection connected with the balance controller 3.

The functions of the main controller 1 include: the method comprises the steps of reading main command contact input, judging whether the voltage of an energy storage unit is balanced or not, detecting the temperature, detecting the total voltage and the total current, outputting the state and the protection contact, reading bus data, downloading a balance instruction, controlling the discharge of the energy storage unit and controlling a fan of an integral cabinet, displaying monitoring voltage monitoring data in real time, carrying out remote communication and the like.

The second embodiment is as follows: the present embodiment is described with reference to fig. 3 and 4, and is a further limitation to the supercapacitor voltage balancing device according to the first embodiment, in the present embodiment, the balancing controller 3 includes n parallel-connected balancing units 3-1, m analog switching circuits 3-2, an AD processing circuit 3-3, a balancing control processor 3-4, a temperature signal processing circuit 3-5, an optical coupling isolation communication circuit 3-6, and an isolation power supply, where m is less than n;

each parallel-link balancing unit 3-1 is used for charging one parallel link, and the control signal input end of the parallel-link balancing unit 3-1 is connected with the charging control signal output end of the balance control processor 3-4;

each analog switching circuit 3-2 is used for measuring the terminal voltage of a plurality of parallel joints, m analog switching circuits 3-2 measure the terminal voltages of n parallel joints in total, and the measurement result is sent to the balance control processor 3-4 through the AD processing circuit 3-3;

the output end of the temperature signal processing circuit 3-5 is connected with the temperature signal input end of the balance control processor 3-4, and the input end of the temperature signal processing circuit 3-5 is used for being connected with the temperature sensor 3-7

The temperature sensor 3-7 is used for measuring the temperature of the energy storage unit and sending the measurement result to the balance control processor 3-4 through the temperature signal processing circuit 3-5, and the energy storage unit comprises a balance controller 3 and a parallel connection connected with the balance controller 3;

the refrigeration control signal output end of the balance control processor 3-4 is used for being connected with the control signal input end of the fan 3-8;

and the balance control processor 3-4 carries out data transmission with the main controller 1 through a CAN signal transmission line.

As shown in figure 3, when the device is used, the balance control processor 3-4 is connected with the fan 3-8, the temperature signal processing circuit 3-5 is connected with the temperature sensor 3-7, and the temperature sensor 3-7 is used for measuring the temperature of the energy storage unit. A plurality of temperature signal processing circuits 3-5 and a plurality of temperature sensors 3-7 may be provided for measuring the temperature at different locations of the energy storage unit. Each analog switching circuit 3-2 performs differential sampling on the voltage of one parallel connection joint, converts the voltage difference at two ends of the parallel connection joint into absolute voltage to the ground, and sends the absolute voltage to an AD sampling chip after passing through a proportion link, a filtering link and an amplitude limiting protection link, and the AD sampling chip converts analog quantity into digital quantity for voltage dynamic balance control and related abnormity and fault detection. As shown in fig. 4, the equalization control processor 3-4 is implemented by a DSPIC30F5011 chip, and its main function is to make a charging judgment on the relevant parallel node and issue a relevant parallel node charging command. And the parallel joint balancing unit 3-1 is started after receiving the command, and charges the corresponding parallel joint. When the voltage of the parallel joint rises to a preset value, the balance control processor 3-4 sends a charging stopping command, and the parallel joint balancing unit 3-1 stops working. The equalization control processor 3-4 also has a function of monitoring the temperature of the energy storage unit including the equalization controller 3 and a parallel link connected to the equalization controller 3. The temperature sensor 3-7 outputs a voltage signal representing temperature, the voltage signal is sent to the balance control processor 3-4 after the links of proportion adjustment, filtering and amplitude limiting protection of the temperature signal processing circuit 3-5, the balance control processor 3-4 converts the temperature analog signal into a digital signal, and when the temperature exceeds a preset value, the balance control processor 3-4 sends a command of starting the fan. The DC-DC power supply module 4 provides a working power supply for an isolation power supply and the parallel connection balancing unit 3-1, and the isolation power supply outputs two voltage levels including 24V voltage provided for m analog switching circuits 3-2 and AD processing circuits 3-3 and 5V voltage provided for the balance control processor 3-4, the temperature signal processing circuits 3-5 and the optical coupling isolation communication circuits 3-6.

The functions of the equalization control processor 3-4 include: the method comprises the following steps of parallel connection voltage detection, internal temperature detection of the energy storage unit, parallel connection capacitance capacity and internal resistance identification, state monitoring of parallel connection capacitance, temperature control of the energy storage unit, control of an internal balancing unit of the energy storage unit, information exchange with the main controller 1 and the like. The functional block diagram is shown in fig. 4, and a control chip of the balance control processor 3-4 selects a high-performance 16-bit digital signal single chip microcomputer with the model number of DSPIC30F 5011. The chip has 16-path 12-bit ADC, and other functions comprise: the DSPIC30F5011 chip adopts a high-performance improved RISC CPU, 8 interrupt priorities including data converter interfaces such as I2C and two CAN bus modules compatible with the CAN2.0B standard.

After n parallel voltage-saving signals are selected by m multi-path analog switching circuits 3-2, the signals are converted into digital quantity by an AD processing circuit 3-3 and then sent into a singlechip of a balance control processor 3-4 through SPI serial signals of an optical coupling isolation communication circuit 3-6. In the embodiment, 2 temperature sensors 3-7 and 2 temperature signal processing circuits 3-5 are arranged, the temperature signals of the 2 paths of energy storage units are directly sent to a single chip microcomputer, and conversion from analog quantity to digital quantity is carried out by utilizing AD in the single chip microcomputer. The gating of the multi-path analog switching circuit 3-2 is controlled by four paths of IO ports of the single chip microcomputer, the 16 paths of parallel-connection balancing units are controlled by the 16 paths of IO ports of the single chip microcomputer in starting and stopping, and the on-off of the fan 3-8 is also controlled by one path of IO ports. The external storage space is expanded through a parallel data port.

The third concrete implementation mode: the present embodiment is described with reference to fig. 5 and 6, and the present embodiment is a further limitation of the supercapacitor voltage equalizing device according to the second embodiment, and in the present embodiment, the AD processing circuit 3-3 includes an analog processing circuit 3-3-1, an analog/digital conversion module 3-3-2, and a digital isolation module 3-3-3;

the m signal input ends of the analog processing circuit 3-3-1 are respectively connected with the signal output ends of the m analog switching circuits 3-2, the signal output end of the analog processing circuit 3-3-1 is connected with the analog signal input end of the analog/digital conversion module 3-3-2, the digital signal output end of the analog/digital conversion module 3-3-2 is connected with the parallel voltage-saving signal input end of the balance control processor 3-4 through the digital isolation module 3-3-3, and the channel selection control signal output end of the digital isolation module 3-3-3 is connected with the channel selection control signal input ends of the m analog switching circuits 3-2.

As shown in fig. 6, when the middle position of a series-parallel connection in one energy storage unit is selected as ground, the 60V energy storage unit becomes ± 30V, and then the voltage is further reduced to ± 15V by each parallel connection through a voltage dividing resistor, which is within the operating voltage of the operational amplifier, and the voltage dividing resistor is 32 resistors between the four analog switching circuits 3-2 and the capacitor module in fig. 6. After the 16 parallel voltage-dividing signals are transformed by the voltage-dividing resistors, the transformed voltage-dividing signals enter the analog processing circuit 3-3-1 through the channel selection of the 4 multi-channel analog switching circuits 3-2 (namely, the analog switch chip in fig. 6). The parallel link voltage of each path can be sampled separately by the differential operational amplifier. The analog processing circuit 3-3-1 is realized by three operational amplifiers, the model of the operational amplifier is LT1014, and a double power supply 15V supplies power. The R1 and the C1 form a first-order low-pass filter to filter the voltage signal, and the D1 plays a role in limiting protection. When the voltage exceeds 5V, the Vi voltage will be clamped to 5.7V, which prevents damage to the analog processing circuit 3-3-1 by overvoltage of the voltage signal. As shown in fig. 6, the follower circuit formed by the two operational amplifiers on the left side in the analog processing circuit 3-3-1 can be used for impedance isolation to eliminate the influence of the on-resistance of the analog switch on the sampling voltage.

The significant advantages of this design are: 1. the sampling precision is high, the voltage of the super capacitor is directly sampled, and the resolution of each parallel voltage-saving sample is fixed; 2. errors are not coupled, the errors of voltage sampling are only related to the sampling channel of the channel, and adjacent voltage sampling is not coupled.

The fourth concrete implementation mode: the present embodiment will be described with reference to fig. 7, and the present embodiment is a further limitation of the supercapacitor voltage balancing device according to the second embodiment. Because the temperature has a significant influence on the service life of the super capacitor, the temperature in the energy storage unit is ensured not to exceed the working temperature range of the super capacitor in the using process, and therefore the temperature in the energy storage unit needs to be monitored. In the scheme, two temperature sensors are placed at different positions of the energy storage unit and are powered by an isolated 5V power supply. The temperature sensor 3-7 adopts PT100, and the output voltage signal is input into the balance control processor 3-4 after passing through the temperature signal processing circuit 3-5 shown in figure 7. The operational amplifier circuit in the temperature signal processing circuit 3-5 realizes the proportional amplification of the output signal of the temperature sensor, and R2 and C2 form a first-order low-pass filtering link to filter the high-frequency interference in the signal. VD prevents damage to the equalization control processor 3-4 caused by excessive voltage on the temperature signal.

The fifth concrete implementation mode: the present embodiment will be described with reference to fig. 8, and the present embodiment is a further limitation of the supercapacitor voltage balancing device according to the second embodiment, and in the present embodiment, the balancing control processor 3-4 has embedded therein a balancing control interruption sub-module implemented by software, and the module includes the following means:

a parallel voltage-saving reading unit: continuously reading and storing n parallel voltage values sent by m analog switching circuits 3-2; starting the parallel voltage-saving sequencing unit after the unit finishes running;

integral charging instruction judgment unit: judging whether an integral charging instruction sent by the main controller 1 is received or not, starting an integral charging instruction sending unit if the judgment result is yes, and starting a first maximum voltage difference judgment unit if the judgment result is no;

integral charging instruction transmitting unit: sending a charging instruction to the n parallel-joint balancing units 3-1; starting an integral charging end instruction judging unit after the unit finishes running;

an overall charging end instruction determination unit: judging whether an integral charging finishing instruction sent by the main controller 1 is received or not, and starting a stopping integral charging instruction sending unit when the judgment result is yes; restarting the whole charging ending instruction judging unit when the judging result is negative;

stop the whole charging instruction transmitting unit: sending a charging stopping instruction to the n parallel-joint balancing units 3-1; starting a first maximum voltage difference judgment unit after the unit finishes running;

a selective charging instruction transmitting unit: sending a charging instruction to a parallel joint balancing unit 3-1 corresponding to the three parallel joints with the lowest voltage values; starting a second maximum voltage difference judgment unit after the unit finishes running;

a step of sending a stop selective charging command: sending a charging stopping instruction to a parallel joint balancing unit 3-1 corresponding to the three parallel joints; and starting the identification unit after the unit finishes running;

an identification result transmitting unit: sending the parallel connection node capacity and the internal resistance calculated by the identification unit to the main controller 1; and starting the temperature control unit after the unit finishes running;

The software flow of the equalization control processor 3-4 is as shown in fig. 8, with the equalization control interrupt submodule first performing reading of the parallel link voltage. And storing the parallel-connection voltage value read each time, and covering the parallel-connection voltage value read last time, namely only storing the parallel-connection voltage value read last time. The read voltage signals are subjected to digital filtering and then are subjected to parallel joint voltage sequencing from high to low. And then judging whether the main controller 1 sends an integral charging instruction of the energy storage unit, if so, sending the charging instruction to all the parallel-joint balancing units 3-1 in the energy storage unit until the integral charging instruction is cancelled. And if the integral charging instruction does not exist, voltage equalization inside the energy storage unit is carried out, whether the difference value of the highest parallel joint voltage and the lowest parallel joint voltage exceeds delta U or not is judged, if the difference value of the highest parallel joint voltage and the lowest parallel joint voltage exceeds delta U, a charging instruction is sent to 3 parallel joint balancing units with lower voltage values until the internal equalization is finished, and if the difference value of the highest parallel joint voltage and the lowest parallel joint voltage does not exceed delta U, the internal equalization inside the energy storage unit is quitted. In the present embodiment, Δ U is 25 mV. And then, identifying the capacity and the internal resistance of the parallel super capacitor, and sending an identification result to the main controller 1. And finally, reading the temperature of the energy storage unit and judging whether the temperature is over-temperature, and starting a cooling system, namely the fan 3-8, if the temperature is over-temperature.

The sixth specific implementation mode: the present embodiment will be described with reference to fig. 9, and the present embodiment is a further limitation of the supercapacitor voltage balancing device according to the fifth embodiment, and the temperature control means in the present embodiment includes:

temperature signal reading unit: reading and storing the temperature value sent by the temperature signal processing circuit 3-5; and starting a temperature judgment unit after the unit finishes running;

a first temperature determination unit: judging whether the temperature value is higher than T₀Starting a fan starting unit when the judgment result is yes, and stopping the operation of the balance control interruption submodule when the judgment result is no;

the described delta U and T₀Are all preset values, T₀The upper limit of the temperature at which the energy storage unit can normally work is set;

a fan starting unit: sending a starting instruction to the fans 3-8; and starting a second temperature judgment unit after the unit finishes running;

a second temperature determination unit: judging whether the temperature value is higher than T₀And the second temperature judging unit is restarted when the judgment result is yes,starting a fan stopping unit when the judgment result is negative;

a fan stop unit: and sending a stop operation instruction to the fans 3-8, and finishing the operation of the balance control interruption submodule after the unit is operated.

The seventh embodiment: the present embodiment will be described with reference to fig. 10 to 12, and the present embodiment is a further limitation of the supercapacitor voltage balancing device according to the fifth embodiment, and in the present embodiment, the identification unit includes:

the super capacitor terminal voltage and input current reading unit: continuously reading and storing the terminal voltage and the input current of the super capacitor sent by the main controller 1; and starting the end voltage and input current average value calculating unit after the unit finishes operation;

terminal voltage and input current average value calculating unit: calculating the latest voltage average value u₃And the latest average value i of the input current₃，u₃Average value of terminal voltage of super capacitor for last p times₃The average value of the input current of the super capacitor which is read for the last p times is obtained; p is an integer greater than or equal to 3; starting the capacitance and internal resistance calculating unit after the unit finishes operation;

capacitance and internal resistance calculation unit: calculating the capacitance C and the internal resistance r of the super capacitor according to the following formulas; starting a calculation result judgment unit after the unit finishes running;

u₂is the average value of the terminal voltages of the super capacitors read from the last second to the p +1 th time, i₂The average value of the input current of the super capacitor read from the last second time to the p +1 th time;

u₁is the average value of the terminal voltages of the super capacitor read from the last third time to the p +2 th time, i₁The average value of the input current of the super capacitor read from the last third time to the p +2 th time;

a calculation result judgment unit: judging whether the calculated values of C and r are in a correct range or not, and starting a calculation result sending unit when the judgment result is yes; if the judgment result is negative, the capacitor and internal resistance updating unit is started;

a calculation result transmitting unit: sending the calculated values of C and r to the main controller 1; after the unit finishes running, the capacitor and internal resistance updating unit is started;

a capacitance and internal resistance updating unit: u. of₁＝u₂,i₁＝i₂,u₂＝u₃,i₂＝i₃(ii) a And the unit operation is finished after the unit operation is finished.

The capacity and the internal resistance of the super capacitor are identified in real time on line, so that the capacity and the internal resistance of the super capacitor are significant for service life estimation and fault detection of the super capacitor, the method adopted by the embodiment is obtained by calculating 3 continuous groups of average voltage and average current values, the equivalent capacitance and the equivalent series resistance of the parallel connection of the super capacitor can be calculated by using the method, and the principle is shown in fig. 10 and fig. 11. In FIG. 10, u is the terminal voltage of the super capacitor, i is the input current of the super capacitor, r is the internal resistance of the super capacitor, C is the capacitance of the super capacitor, and the subscripts 1 and 2 represent the previous different time points, T₁Is i₁Corresponding time, T₂Is i₂The corresponding time.

As can be seen from fig. 10 and 11, the following relationship exists between the voltage and the current at different times:

<math> <mrow> <msub> <mi>u</mi> <mn>2</mn> </msub> <mo>=</mo> <mi>r</mi> <mrow> <mo>(</mo> <msub> <mi>i</mi> <mn>2</mn> </msub> <mo>-</mo> <msub> <mi>i</mi> <mn>1</mn> </msub> <mo>)</mo> </mrow> <mo>+</mo> <msub> <mi>u</mi> <mn>1</mn> </msub> <mo>+</mo> <mfrac> <mn>1</mn> <mi>C</mi> </mfrac> <msubsup> <mo>&Integral;</mo> <msub> <mi>T</mi> <mn>1</mn> </msub> <msub> <mi>T</mi> <mn>2</mn> </msub> </msubsup> <mi>idt</mi> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>

wherein,can use an upper edge and a lower edge which are i respectively₁、i₂Height of T ═ T₂-T₁The trapezoidal approximation of (a) indicates that three sets of data at different times are taken to obtain:

then the formula (2) is used to obtain the identification formula of the capacity and the internal resistance of the super capacitor:

the algorithm flow of the super capacitor capacity and internal resistance identification is shown in fig. 12, and average filtering is performed on continuous 5-time samples of the parallel-connected voltage and current, and the obtained result is used as the latest voltage value u₃Sum current value i₃Substituting the capacitance into the formula (3) for calculation, judging the calculation result, updating the values of the capacitance and the internal resistance and uploading the calculation result to the main controller 1 if the calculation is correct; if not, the calculation result is discarded. The update method is to discard u₁And i₁Will u₂And i₂Are respectively assigned to u₁And i₁Will u₃And i₃Are respectively assigned to u₂And i₂And then ends the operation of the recognition unit. Calculating knotIn the step of determining the result, the correct range may be determined according to the average value of the previous calculation results, for example, the upper and lower 10% of the average value of the calculation results are taken as the correct range.

The specific implementation mode is eight: the present embodiment will be described with reference to fig. 13, and the present embodiment is a further limitation of the supercapacitor voltage equalizing device according to the first embodiment, and in the present embodiment, the DC-DC power supply module 4 is used to supply energy to the entire voltage equalizing device. The index requirements are as follows: the power requirement of simultaneously charging one fourth of the parallel-connection balancing units 3-1 of the total number of the parallel-connection nodes can be met.

One fourth of all the parallel-connected balance units 3-1 is calculated according to 120 paths, the maximum power of each path is 50W, and the rated power of the DC-DC power conversion is 120 multiplied by 50W to 6 kW. The principle of the DC-DC power module 4 is shown in fig. 13, and in order to improve the conversion efficiency and reduce the harmonic interference, an LLC resonant half-bridge converter structure is adopted, so that the primary MOSFET can be switched on and off at ZVS (zero voltage) and the secondary rectifier diode can be switched on and off at ZCS (zero current) within the full voltage range and under the full load condition, thereby reducing the switching loss and greatly improving the efficiency. And under the condition that the input voltage and the load range change greatly, the switching frequency change is small, and the design of main parameters is facilitated. In this embodiment, the efficiency of the DC-DC power module 4 is 94%, the efficiency of the parallel link balancing unit 3-1 is 90%, and the total efficiency of the voltage equalizing system is 85%.

The specific implementation method nine: in this embodiment, the supercapacitor voltage balancing device according to the first embodiment is further limited, and in this embodiment, the supercapacitor voltage balancing device further includes a display device, and the display device is connected to the main controller 1.

The display device is realized by adopting a touch screen and is used for selecting functions, setting parameters and the like.

The detailed implementation mode is ten: the present embodiment will be described with reference to fig. 8, and the present embodiment is a method for controlling a supercapacitor voltage balancing device according to embodiment two, the method including the steps of:

reading parallel connection voltage: continuously reading and storing n parallel voltage values sent by m analog switching circuits 3-2; and after the step is finished, executing a parallel voltage-saving sequencing step;

and an integral charging instruction judging step: judging whether an integral charging instruction sent by the main controller 1 is received or not, executing an integral charging instruction sending step when the judgment result is yes, and executing a first maximum voltage difference judgment step when the judgment result is no;

and sending an overall charging instruction: sending a charging instruction to the n parallel-joint balancing units 3-1; and executing the whole charging end instruction judging step after the step is finished;

and an integral charging end instruction judging step: judging whether an integral charging finishing instruction sent by the main controller 1 is received or not, and executing an integral charging stopping instruction sending step when the judgment result is yes; re-executing the whole charging ending instruction judging step when the judging result is negative;

stopping sending the integral charging command: sending a charging stopping instruction to the n parallel-joint balancing units 3-1; and executing a first maximum voltage difference judging step after the step is finished;

a selective charging instruction sending step: sending a charging instruction to a parallel joint balancing unit 3-1 corresponding to the three parallel joints with the lowest voltage values; and executing a second maximum voltage difference judging step after the step is finished;

a step of sending a stop selective charging command: sending a charging stopping instruction to a parallel joint balancing unit 3-1 corresponding to the three parallel joints; and performing an identification step after the step is finished;

an identification result sending step: sending the parallel connection node capacity and the internal resistance calculated in the identification step to the main controller 1; and after the step is finished, executing a temperature control step;

In this embodiment, when the main controller 1 issues a general charging instruction, the equalization control processor 3-4 controls all the parallel nodes connected thereto to perform general charging. When the integral charging is not carried out, the balance control processor 3-4 monitors the voltage of each parallel connection joint, and when the maximum value of each parallel connection electricity-saving pressure difference exceeds a preset value, the balance control processor starts to charge 3 parallel connection joints with lower voltage so as to balance the voltage of each parallel connection joint until the maximum value of each parallel connection electricity-saving pressure difference is smaller than the preset value. In the charging process, the temperature is required to be detected continuously, and when the temperature is too high, the balance control processor 3-4 controls the fan to start working and cool until the temperature is reduced to the normal working temperature range. In addition, the balance control processor 3-4 also needs to calculate the capacitance capacity and the internal resistance of the super capacitor and send the calculation result to the main controller 1 for real-time display.

The concrete implementation mode eleven: the present embodiment will be described with reference to fig. 9, and the present embodiment is further limited to the method for controlling the supercapacitor voltage balancing device according to embodiment ten, and in the present embodiment, the temperature control step includes the steps of:

temperature signal reading step: reading and storing the temperature value sent by the temperature signal processing circuit 3-5; and executing a first temperature judgment step after the step is finished;

a first temperature judging step: judging whether the temperature value is higher than T₀If the judgment result is yes, executing a fan starting step, and if the judgment result is no, finishing the temperature control step;

the described delta U and T₀Are all preset values, T₀The upper temperature limit for normal operation of the energy storage unit step;

a fan starting step: sending a starting instruction to the fans 3-8; and executing a second temperature judgment step after the operation of the step is finished;

a second temperature judging step: judging whether the temperature value is higher than T₀If the judgment result is yes, the fan stopping step is executed, and if the judgment result is no, the second temperature judging step is executed;

a fan stopping step: sending a stop operation instruction to the fans 3-8; and the temperature control step is ended after the step operation is ended.

The specific implementation mode twelve: the present embodiment will be described with reference to fig. 10 to 12, and the present embodiment is further limited to the method for controlling the supercapacitor voltage balancing device according to embodiment ten, and in the present embodiment, the identifying step includes the steps of:

reading the terminal voltage and the input current of the super capacitor: continuously reading and storing the terminal voltage and the input current of the super capacitor sent by the main controller 1; and after the step is finished, performing a calculation step of the average value of the end voltage and the input current;

calculating the average value of the terminal voltage and the input current: calculating the latest voltage average value u₃And the latest average value i of the input current₃，u₃Average value of terminal voltage of super capacitor for last p times₃The average value of the input current of the super capacitor which is read for the last p times is obtained; p is an integer greater than or equal to 3; and executing the step of calculating the capacitance and the internal resistance after the step is finished;

and calculating capacitance and internal resistance: calculating the capacitance C and the internal resistance r of the super capacitor according to the following formulas; and executing a calculation result judgment step after the step is finished;

u₁is the average value of the terminal voltages of the super capacitor read from the last third time to the p +2 th time, i₁Input of super capacitor for last third to p +2 readingThe average value of the current;

and a calculation result judgment step: judging whether the calculated values of C and r are in a correct range or not, and executing a calculation result sending step when the judgment result is yes; if the judgment result is negative, the step of updating the capacitance and the internal resistance is executed;

and a calculation result sending step: sending the calculated values of C and r to the main controller 1; and after the step is finished, the step of updating the capacitance and the internal resistance is executed;

updating the capacitance and the internal resistance: u. of₁＝u₂,i₁＝i₂,u₂＝u₃,i₂＝i₃And, at this point, the identification step is finished.

The flow of the identification step is shown in FIG. 12. The method adopted by the embodiment is obtained by calculating the average voltage and the average current of 3 continuous groups of average voltages and average current values, the equivalent capacitance and the equivalent series resistance of the parallel connection of the super capacitors can be calculated by using the method, and the principle is shown in fig. 10 and fig. 11. In FIG. 10, u is the terminal voltage of the super capacitor, i is the input current of the super capacitor, r is the internal resistance of the super capacitor, C is the capacitance of the super capacitor, and the subscripts 1 and 2 represent the previous different time points, T₁Is i₁Corresponding time, T₂Is i₂The corresponding time. In the calculation result determination step, the correct range may be determined based on the average of the results of the previous calculations, for example, the upper and lower 10% of the average of the results of the previous calculations are taken as the correct range.

Claims

1. Ultracapacitor system voltage balancing unit, its characterized in that: the device comprises a main controller (1), a total current/voltage detection unit (2), a plurality of balance controllers (3) and a DC-DC power supply module (4);

the DC-DC power supply module (4) provides working power supply for the main controller (1), the total current/voltage detection unit (2) and the plurality of balance controllers (3);

the main controller (1) is connected with the plurality of balance controllers (3) and the total current/voltage detection unit (2);

each balancing controller (3) is used for measuring the terminal voltage of n parallel nodes of the super capacitor and charging the n parallel nodes;

the total current/voltage detection unit (2) is used for detecting the total voltage and the total current of the output port of the super capacitor.

2. The supercapacitor voltage balancing device according to claim 1, wherein: the balance controller (3) comprises n parallel-connection balance units (3-1), m analog switching circuits (3-2), an AD processing circuit (3-3), a balance control processor (3-4), a temperature signal processing circuit (3-5), an optical coupling isolation communication circuit (3-6) and an isolation power supply, wherein m is smaller than n;

each parallel-link balancing unit (3-1) is used for charging one parallel link, and the control signal input end of the parallel-link balancing unit (3-1) is connected with the charging control signal output end of the balance control processor (3-4);

each analog switching circuit (3-2) is used for measuring the terminal voltage of a plurality of parallel joints, m analog switching circuits (3-2) measure the terminal voltages of n parallel joints in total, and the measurement result is sent to the balance control processor (3-4) through the AD processing circuit (3-3);

the output end of the temperature signal processing circuit (3-5) is connected with the temperature signal input end of the balance control processor (3-4), and the input end of the temperature signal processing circuit (3-5) is used for being connected with the temperature sensor (3-7);

the temperature sensor (3-7) is used for measuring the temperature of the energy storage unit and sending the measurement result to the balance control processor (3-4) through the temperature signal processing circuit (3-5), and the energy storage unit comprises a balance controller (3) and a parallel connection section connected with the balance controller (3);

the refrigeration control signal output end of the balance control processor (3-4) is used for being connected with the control signal input end of the fan (3-8);

and the balance control processor (3-4) performs data transmission with the main controller (1) through a CAN signal transmission line.

3. The supercapacitor voltage balancing device according to claim 2, wherein: the AD processing circuit (3-3) comprises an analog processing circuit (3-3-1), an analog/digital conversion module (3-3-2) and a digital isolation module (3-3-3);

the m signal input ends of the analog processing circuit (3-3-1) are respectively connected with the signal output ends of the m analog switching circuits (3-2), the signal output end of the analog processing circuit (3-3-1) is connected with the analog signal input end of the analog/digital conversion module (3-3-2), the digital signal output end of the analog/digital conversion module (3-3-2) is connected with the parallel voltage-saving signal input end of the balance control processor (3-4) through the digital isolation module (3-3-3), and the channel selection control signal output end of the digital isolation module (3-3-3) is connected with the channel selection control signal input ends of the m analog switching circuits (3-2).

4. The supercapacitor voltage balancing device according to claim 2, wherein: the equalization control processor (3-4) is embedded with an equalization control interruption submodule realized by software, and the module comprises the following units:

a parallel voltage-saving reading unit: continuously reading and storing n parallel-connection voltage values sent by m analog switching circuits (3-2); starting the parallel voltage-saving sequencing unit after the unit finishes running;

integral charging instruction judgment unit: judging whether an integral charging instruction sent by the main controller (1) is received or not, starting an integral charging instruction sending unit if the judgment result is yes, and starting a first maximum voltage difference judgment unit if the judgment result is no;

integral charging instruction transmitting unit: sending a charging instruction to the n parallel-joint balancing units (3-1); starting an integral charging end instruction judging unit after the unit finishes running;

an overall charging end instruction determination unit: judging whether an integral charging finishing instruction sent by the main controller (1) is received or not, and starting a stopping integral charging instruction sending unit when the judgment result is yes; restarting the whole charging ending instruction judging unit when the judging result is negative;

stop the whole charging instruction transmitting unit: sending a charging stopping instruction to the n parallel-joint balancing units (3-1); starting a first maximum voltage difference judgment unit after the unit finishes running;

a selective charging instruction transmitting unit: sending a charging instruction to a parallel joint balancing unit (3-1) corresponding to the three parallel joints with the lowest voltage values; starting a second maximum voltage difference judgment unit after the unit finishes running;

a step of sending a stop selective charging command: sending a charging stopping instruction to a parallel joint balancing unit (3-1) corresponding to the three parallel joints; and starting the identification unit after the unit finishes running;

an identification result transmitting unit: sending the parallel connection node capacity and the internal resistance calculated by the identification unit to a main controller (1); and starting the temperature control unit after the unit finishes running;

5. The supercapacitor voltage balancing device according to claim 4, wherein: the temperature control unit comprises the following units:

temperature signal reading unit: reading and storing the temperature value sent by the temperature signal processing circuit (3-5); and starting a temperature judgment unit after the unit finishes running;

a fan starting unit: sending a starting instruction to the fan (3-8); and starting a second temperature judgment unit after the unit finishes running;

a second temperature determination unit: judging whether the temperature value is higher than T₀Restarting the second temperature judging unit when the judging result is yes, and starting the fan stopping unit when the judging result is no;

a fan stop unit: and sending a stop operation instruction to the fans (3-8), and finishing the operation of the balance control interruption submodule after the unit finishes operating.

6. The supercapacitor voltage balancing device according to claim 4, wherein: the identification unit comprises the following units:

the super capacitor terminal voltage and input current reading unit: continuously reading and storing the terminal voltage and the input current of the super capacitor sent by the main controller (1); and starting the end voltage and input current average value calculating unit after the unit finishes operation;

a calculation result transmitting unit: sending the calculated values of C and r to a main controller (1); after the unit finishes running, the capacitor and internal resistance updating unit is started;

7. The control method of the supercapacitor voltage balancing device according to claim 2, characterized in that: the method comprises the following steps:

reading parallel connection voltage: continuously reading and storing n parallel-connection voltage values sent by m analog switching circuits (3-2); and after the step is finished, executing a parallel voltage-saving sequencing step;

and an integral charging instruction judging step: judging whether an integral charging instruction sent by the main controller (1) is received or not, executing an integral charging instruction sending step when the judgment result is yes, and executing a first maximum voltage difference judgment step when the judgment result is no;

and sending an overall charging instruction: sending a charging instruction to the n parallel-joint balancing units (3-1); and executing the whole charging end instruction judging step after the step is finished;

and an integral charging end instruction judging step: judging whether an overall charging ending instruction sent by the main controller (1) is received or not, and executing an overall charging stopping instruction sending step when the judgment result is yes; re-executing the whole charging ending instruction judging step when the judging result is negative;

stopping sending the integral charging command: sending a charging stopping instruction to the n parallel-joint balancing units (3-1); and executing a first maximum voltage difference judging step after the step is finished;

a selective charging instruction sending step: sending a charging instruction to a parallel joint balancing unit (3-1) corresponding to the three parallel joints with the lowest voltage values; and executing a second maximum voltage difference judging step after the step is finished;

a step of sending a stop selective charging command: sending a charging stopping instruction to a parallel joint balancing unit (3-1) corresponding to the three parallel joints; and performing an identification step after the step is finished;

an identification result sending step: sending the parallel connection node capacity and the internal resistance calculated in the identification step to a main controller (1); and after the step is finished, executing a temperature control step;

8. The control method of the supercapacitor voltage balancing device according to claim 7, wherein: the temperature control step comprises the following steps:

temperature signal reading step: reading and storing the temperature value sent by the temperature signal processing circuit (3-5); and executing a first temperature judgment step after the step is finished;

a fan starting step: sending a starting instruction to the fan (3-8); and executing a second temperature judgment step after the operation of the step is finished;

a fan stopping step: sending a stop operation instruction to the fan (3-8); and the temperature control step is ended after the step operation is ended.

9. The control method of the supercapacitor voltage balancing device according to claim 7, wherein: the identifying step comprises the following steps:

reading the terminal voltage and the input current of the super capacitor: continuously reading and storing the terminal voltage and the input current of the super capacitor sent by the main controller (1); and after the step is finished, performing a calculation step of the average value of the end voltage and the input current;

u₁is the average value of the terminal voltages of the super capacitor read from the last third time to the p +2 th time, i₁From the last third to the p +2 thReading the average value of the input current of the super capacitor;

and a calculation result sending step: sending the calculated values of C and r to a main controller (1); and after the step is finished, the step of updating the capacitance and the internal resistance is executed;