CN104393153B - A kind of wafer-level encapsulation method of semiconductor devices - Google Patents
A kind of wafer-level encapsulation method of semiconductor devices Download PDFInfo
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- CN104393153B CN104393153B CN201410700670.4A CN201410700670A CN104393153B CN 104393153 B CN104393153 B CN 104393153B CN 201410700670 A CN201410700670 A CN 201410700670A CN 104393153 B CN104393153 B CN 104393153B
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000005538 encapsulation Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 230000008878 coupling Effects 0.000 claims abstract description 31
- 238000010168 coupling process Methods 0.000 claims abstract description 31
- 238000005859 coupling reaction Methods 0.000 claims abstract description 31
- 239000000843 powder Substances 0.000 claims abstract description 31
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 21
- 238000005516 engineering process Methods 0.000 claims abstract description 11
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000000608 laser ablation Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 5
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- 238000005520 cutting process Methods 0.000 claims description 4
- 238000001962 electrophoresis Methods 0.000 claims description 4
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- 238000005507 spraying Methods 0.000 claims description 3
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- 239000010410 layer Substances 0.000 description 93
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- 238000007493 shaping process Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
- H01L33/502—Wavelength conversion materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present invention relates to a kind of wafer-level encapsulation method of semiconductor devices, belong to technical field of semiconductor encapsulation.It includes following technological process：Silicon substrate disk is provided, the upper surface growth of its silicon substrate has epitaxial layer；The metal coupling of array-like is formed by bump technology on the surface of the epitaxial layer of silicon substrate disk；Encapsulated metal projection, thinning encapsulated layer exposes the surface of metal coupling；Upset and the another side of thinning silicon substrate；The central region for removing silicon substrate by the mask or tool of ring-type exposes the exiting surface of epitaxial layer, and exiting surface to exposed epitaxial layer carries out micro-structural treatment；Segmentation epitaxial layer forms crisscross epitaxial layer interval；Phosphor powder layer and photic zone are formed in ring-type die cavity；Along epitaxial layer cut-space, the encapsulation monomer of independent photodiode is formed.The invention provides with thickness of thin, stress is small, low cost photodiode method for packing.
Description
Technical field
The present invention relates to a kind of wafer-level encapsulation method of semiconductor devices, belong to technical field of semiconductor encapsulation.
Background technology
Photodiode is the semiconductor devices that electricity is converted into light, and length is had been achieved for as New Solid lighting source
The development of foot.Due to being influenceed by factors such as properties of product, manufacturing cost and appearance and sizes, the packing forms of photodiode
Also constantly develop and enrich：Traditional photodiode packing forms mainly have stent-type to encapsulate, plastic packaging material formula EMC is encapsulated, gold
The COB encapsulation of category printed board type, and the board-like encapsulation of ceramic base.As shown in figure 1, traditional photodiode is with expensive sapphire
Or carborundum is that substrate forms photodiode chip, limits the decline space of the production cost of photodiode, Er Qieqi
Thickness typically more than 500 microns, is limiting the space of packaged light source；Meanwhile, the phosphor powder layer of white light photodiode with
The mechanical property difference of substrate is larger, in technical process or using process because temperature change easily forms thermal stress, and causes
The cracking of photodiode encapsulating products, the failure such as fracture, and reduces product reliability.
The content of the invention
It is an object of the invention to overcome the shortcomings of current photodiode encapsulation technology, there is provided a kind of thickness thinning, carry
High product reliability, the difficulty for reducing packaging technology, the wafer-level encapsulation method of the semiconductor devices of reduction production cost.
The object of the present invention is achieved like this：
A kind of wafer-level encapsulation method of semiconductor devices of the present invention, including following technological process：
Step one, offer silicon substrate disk, the upper surface growth of its silicon substrate have epitaxial layer；
Step 2, the metal coupling for passing through bump technology formation array-like on the surface of the epitaxial layer of silicon substrate disk；
Step 3, using encapsulating process encapsulated metal projection, form encapsulated layer；
Step 4, encapsulated layer is thinned to by rubbing down, corrosion or lithographic method for the surface for exposing metal coupling, and in gold
The surface for belonging to projection is initially formed the method shape that nickel dam re-forms the nickel-gold layer of layer gold or passes through chemical plating by the method for chemical plating
Into tin layers；
Step 5, spin upside down 180 degree, the another side of silicon substrate is carried out by rubbing down, corrosion or lithographic method it is thinning,
Residual thickness H is 200~1000 microns；
Step 6, the mask by ring-type or tool protect the edge of silicon substrate, and silicon is removed by corrosion or lithographic method
The central region of substrate exposes the exiting surface of epitaxial layer, while retaining the fringe region of silicon substrate, forms ring-type die cavity, and to naked
The exiting surface of the epitaxial layer of dew carries out microstructure graph treatment；
Step 7, the epitaxial layer for being split completion micro-structural treatment by etching, corrosion or laser ablation methods, are formed in length and breadth
Epitaxial layer interval staggeredly；
Step 8, in ring-type die cavity by spraying or electrophoresis method formed phosphor powder layer；
Step 9, the method formation photic zone for passing through dispensing or printing rubber on the surface of phosphor powder layer；
Step 10, along epitaxial layer cut-space, form the encapsulation monomer of independent photodiode.
Residual thickness H of the thickness of phosphor powder layer of the present invention less than silicon substrate.
In step 2, the bump technology includes step to the present invention：Splash-proofing sputtering metal is sequentially passed through on the surface of epitaxial layer
Seed Layer, the photoresist opening figure of being formed by photoetching process, in photoresist opening electroplated conductive metal, gone with degumming process
Except remaining photoresist and the invalid metal seed layer of erosion removal, the array of metal coupling is formed.
In step 4, the scope of the height h of the metal coupling is 20~200 microns to the present invention.
Further, in step 4, the scope of the height h of the metal coupling is 60~80 microns.
In step 5, the residual thickness H of the silicon substrate is 500~700 microns to the present invention
In step 6, the width D of the fringe region of the silicon substrate is 500~10000 microns to the present invention.
Further, in step 6, the width D of the fringe region of the silicon substrate is 800~5000 microns
In step 7, the depth at epitaxial layer interval is not less than the thickness of epitaxial layer for invention.
In step 7, the bottom at the epitaxial layer interval carries out roughening treatment to the present invention, and the roughening treatment is will be outer
Prolong interlayer every bottom by dry etching, cutting or laser ablation method formed with microstructure Non-smooth surface face.
Compared to existing scheme, the beneficial effects of the invention are as follows：
（1）The present invention realizes the encapsulating structure of photodiode using only the epitaxial layer that silicon substrate grows, and is thinned light
The thickness of electric diode, increases the flexibility of Lighting Design, and can be also used for before this cannot packaged light source space；And
Silicon substrate is easy to process, cheap, while using the production technology of wafer level, reducing the production cost of photodiode；
（2）With photic zone be formed separately phosphor powder layer by the present invention, by the selection of material, makes photic zone and encapsulated layer power
Learn performance it is more close, so as to during reducing technique or use due to temperature change formed thermal stress, reduce in response to
The cracking of photodiode caused by force deformation, the failure such as fracture, and improves the reliability of photodiode；
（3）Silicon substrate disk is made annulation by the present invention in photodiode encapsulation process, not only remains its firm
Spend, do not allow rupture diaphragm, and easily held in technical process, reduce the difficulty of packaging technology.
Brief description of the drawings
Fig. 1 is the generalized section of conventional photodiode chip structure；
Fig. 2 is a kind of flow chart of the wafer-level encapsulation method of semiconductor devices of the invention；
Fig. 3 is the generalized section of the embodiment of the encapsulating structure of photodiode of the present invention；
Fig. 4 is the schematic diagram of the metal coupling of the photodiode of Fig. 3；
Fig. 5~17 are a kind of flow chart of the wafer-level encapsulation method of semiconductor devices of Fig. 3；
Figure 18 and Figure 19 is the deformation one of Fig. 3；
Figure 20 is the deformation two of Fig. 3；
In figure：
Silicon substrate 11
Epitaxial layer 12
Exiting surface 121
Epitaxial layer interval 122
Mask or tool 16
Metal coupling 2
Nickel-gold layer or tin layers 21
Encapsulated layer 3
Connection reinforcement face 31
Phosphor powder layer 4
Photic zone 5；
Silicon substrate disk 10
Ring-type die cavity 111.
Specific embodiment
Referring to Fig. 2, a kind of technological process of the wafer-level encapsulation method of semiconductor devices of the invention is as follows：
S101：Silicon wafer is taken, growth has epitaxial layer on its silicon substrate；
S102：The metal coupling of array-like is formed on the surface of epitaxial layer and encapsulated, be thinned to and expose metal coupling
The other end surface；
S103：Thinning silicon substrate, the central region for removing silicon substrate exposes the exiting surface of epitaxial layer；
S104：Segmentation epitaxial layer, and phosphor powder layer, photic zone are sequentially formed on epitaxial layer；
S105：The silicon wafer for completing packaging technology is cut into the single packaging body of semiconductor devices.
The present invention is described more fully hereinafter with reference to accompanying drawing now, example of the invention is shown in the drawings
Property embodiment, so that the disclosure fully conveys the scope of the present invention to those skilled in the art.However, the present invention can be with
It is embodied in many different forms, and should not be construed as limited to embodiments set forth here.
Embodiment, referring to Fig. 3 to Fig. 5
The encapsulating structure of photodiode of the present invention, it includes an epitaxial layer 12, and the epitaxial layer 12 is outer for silicon substrate 11
Epitaxial layer, as shown in figure 5, in potting process, silicon substrate 11 is removed by methods such as burn into etchings.In figure 3,
The upper surface of epitaxial layer 12 is its exiting surface 121, such as prismatic, the miniature light emitting structures of taper is provided with, to lift photodiode
Light extraction efficiency.
Two metal couplings 2 used as positive and negative electrode are formed by the bump technology manufacturing process such as plating, chemical plating
In the lower surface of epitaxial layer 12, and its one end and epitaxial layer 12 are connected within the vertical area of epitaxial layer 12, metal coupling 2 with
Metal seed layer is generally set between epitaxial layer 12（Not shown in Fig. 3）, be beneficial to metal coupling 2 in the surface of epitaxial layer 12 into
Shape.Therefore the material of metal coupling 2 includes but is not limited to copper, and its height h is 20~200 microns, with the scope of height h as 60~
80 microns are preferred.The shape of cross section of metal coupling 2 is generally rectangular, as shown in figure 4, being suitable for existing pcb board, wiring board etc.
Use.
The lower surface of epitaxial layer 12 and two metal couplings 2 are encapsulated by encapsulated layer 3, the end face of the other end of metal coupling 2
Expose encapsulated layer 3.The material of encapsulated layer 3 can be silica gel, epoxy glue etc., preferably silica gel.The side border of encapsulated layer 3 is general not
Less than the side border of epitaxial layer 12, to protect epitaxial layer 12, while preventing epitaxial layer 12 from leaking electricity.In order to adjust encapsulated layer 3
Mechanical property, can mix filler such as silica, aluminum oxide etc..The exposing surface of metal coupling 2 sets nickel-gold layer or tin layers, with
The surface oxidation of the metal coupling 2 of metallic copper is prevented, and meets the requirement of soldering reliability.
The cladding thickness scope of exiting surface 121 of epitaxial layer 12 is 20~60 microns of phosphor powder layer 4.Phosphor powder layer 4 passes through
Bloom, green powder, yellowish green powder or the rouge and powder commonly used using industry pass through glue（Generally silica gel）Colloid mixture is mixed to form, by spray
The methods such as painting, electrophoresis cover epitaxial layer 12, and colloid mixture can improve the manufacturability and cementability of fluorescent material.
The exposed surface of phosphor powder layer 4 sets the good photic zones of translucency such as silica gel, epoxy glue by methods such as dispensing, printings
5, preferred silica gel, with close with the mechanical property of encapsulated layer 3, reduces technique or using process because the heat that temperature change is formed is answered
Power, is reduced in response to the cracking of photodiode encapsulation structure product caused by force deformation, the failure such as fracture.Further, may be used also
To blend the fillers such as silica in photic zone 5, mechanical property is adjusted；Or fluorescent material is blended in photic zone 5 as filler,
Not only improve mechanical property but also play a part of regulation light conversion.
The outgoing blue light of epitaxial layer 12, some blue light excites yellow fluorescent powder to send gold-tinted, and then mixed with remainder blue light
Close and obtain white light, or warm white is obtained with the mixing of a small amount of red fluorescence powder using yellow fluorescent powder.
A kind of wafer-level encapsulation method of semiconductor devices of the above embodiment of the present invention, including step：
Step one, referring to Fig. 5, there is provided silicon substrate disk 10, and silicon substrate 11 upper surface growth be distributed it is uniform outer
Prolong layer 12, the thickness of epitaxial layer 12 is general in 10 microns.
Step 2, referring to Fig. 6, sequentially passes through splash-proofing sputtering metal Seed Layer on the surface of epitaxial layer 12 of silicon substrate disk 10, passes through
Photoetching process formed photoresist opening figure, in photoresist opening electroplated conductive metal, remove remaining light with degumming process
Photoresist and the invalid metal seed layer of erosion removal, form the array of metal coupling 2, and the material of metal coupling 2 is with can
The metal of weldability, its material includes but is not limited to copper.
Step 3, using the encapsulating process encapsulated metal projection 2 including methods such as dispensing, gluing, print glue, pad pasting, injections,
Encapsulated layer 3 is formed, the material of encapsulated layer 3 can be silica gel, epoxy glue etc., be preferred with silica gel；In order to adjust the mechanics of encapsulated layer 3
Performance, can mix filler such as silica, aluminum oxide etc.；Referring to Fig. 7.
, referring to Fig. 8, be thinned to for encapsulated layer 3 by methods such as rubbing down, burn into etchings expose metal coupling 2 by step 4
Surface, and make the scope of the height h of metal coupling 2 for 20~200 microns, it is preferred with the scope of height h as 60~80 microns；Again
The side that nickel dam re-forms the nickel-gold layer of layer gold or passes through chemical plating is initially formed by the method for chemical plating on the surface of metal coupling 2
Method forms tin layers.
Step 5, referring to Fig. 9, spins upside down 180 degree, and the another side to silicon substrate 11 is square by rubbing down, burn into etching etc.
Method carries out thinning, the thinning face of formation, and makes the residual thickness H of silicon substrate 11 be 200~1000 microns, with the residue of silicon substrate 11
Thickness H is preferred for 500~700 microns.
Step 6, referring to Figure 10 to Figure 12, sets silicon oxide film, silicon nitride thin at the edge in the thinning face of silicon substrate 11
Mask or tool 16 that film or photoresist are made, to protect the edge of silicon substrate disk 10, are removed by methods such as burn into etchings
The central region of silicon substrate 11 exposes the exiting surface 121 of epitaxial layer, while retaining the fringe region of silicon substrate 11, makes silicon substrate 11
Fringe region width D be 500~10000 microns, preferable width D be 800~5000 microns, make silicon substrate 11 formed ring-type
Die cavity 111, it has cofferdam function, to contribute to the shaping of follow-up phosphor powder layer 4.Ring-type die cavity 111 can retain silicon substrate circle
The part rigidity of piece 10, it is to avoid the deformation of silicon substrate disk 10, fragment, for subsequent technique provides support, also allows for holding, and is conducive to
The carrying out of subsequent technique.
Exiting surface 121 to exposed epitaxial layer 12 is patterned treatment, forms such as prismatic, taper micro-structural, with
Lift the light extraction efficiency of photodiode.
Step 7, referring to Figure 13, is split by etching, corrosion or laser ablation methods and completes the epitaxial layer that micro-structural is processed
12, crisscross epitaxial layer interval 122 is formed, the width at size and the epitaxial layer interval 122 of epitaxial layer 12 is by being actually needed
Design determines.
Step 8, referring to Figure 14, to improve manufacturability and cementability, colloid mixture is mixed to form by fluorescent material by glue,
The glue is usually silica gel；By the colloid mixture, by methods such as spraying, electrophoresis, the formation thickness in ring-type die cavity 111 is suitably glimmering
Light bisque 4, the residual thickness H of the thickness less than silicon substrate 11 of phosphor powder layer 4；Phosphor material powder can be the conventional Huang of industry
Powder, green powder, yellowish green powder or rouge and powder, to obtain the photodiode of different-colour.
Step 9, referring to Figure 15, photic zone 5, printing opacity is formed on the surface of phosphor powder layer 4 by methods such as dispensing, printings
The material of layer 5 is silica gel, epoxy glue etc., preferably silica gel, with close with the mechanical property of encapsulated layer 3, reduce technique or uses
The thermal stress that process is formed by temperature change, is reduced in response to the failure such as ftractureed caused by force deformation, fractureed.Further, may be used also
To blend the fillers such as silica in photic zone 5, mechanical property is adjusted；Or fluorescent material is blended in photic zone 5 as filler,
Not only improve mechanical property but also play a part of regulation light conversion.
Step 10, referring to Figure 16 and Figure 17, photic zone 5 is located at the upper strata of phosphor powder layer 4, because of the fluorescent material of phosphor powder layer 4
Density is big, so harder；Photic zone 5 is small therefore softer without filler or packing density.Therefore can be spaced along epitaxial layer
122 first cut softer photic zone 5, with diamond tool cut harder phosphor powder layer 4 again from steel edge or laser knife,
Independent photodiode encapsulation monomer is formed after completing cutting, as shown in figure 17.It is distinguishing according to the actual conditions of material
Selection cutter, can reduce technology difficulty, while reducing the loss of blade.
The encapsulating structure and its method for packing of a kind of wafer level photodiode of the present invention are not limited to above preferred embodiment,
Such as to improve the reliability of the encapsulating structure of photodiode, encapsulated layer 3 and phosphor powder layer 4 intersection on encapsulated layer 3
Connection reinforcement face 31 is formed by the method for roughening treatment.Connection reinforcement face 31 can be by the downward of the method formation of etching
The inclined plane that trend is made up of some grades of steps 31, as shown in Figure 18 and Figure 19；It can also be the Non-smooth surface with microstructure
Face, the numerous micro-recesses for such as being formed by dry etching or machinery knives（As shown in figure 20）, or by laser ablation
The numerous miniature pit that is formed of method, or irregular mat surface, but the structure in connection reinforcement face 31 is not limited to
This.
Further, in order to preferably improve conductive, the heat dispersion of the encapsulating structure of photodiode, two metals are convex
The extension area of block 2 is big as far as possible, as shown in Figure 4.
Therefore, any those skilled in the art without departing from the spirit and scope of the present invention, according to technology of the invention
Any modification, equivalent variations and modification that essence is made to above example, each fall within the guarantor that the claims in the present invention are defined
In the range of shield.
Claims (10)
1. a kind of wafer-level encapsulation method of semiconductor devices, including following technological process：
Step one, offer silicon substrate disk（10）, its silicon substrate（11）Upper surface growth have epitaxial layer（12）；
Step 2, in silicon substrate disk（10）Epitaxial layer（12）Surface pass through bump technology formed array-like metal coupling
（2）；
Step 3, using encapsulating process encapsulated metal projection（2）, form encapsulated layer（3）；
Step 4, by rubbing down, corrosion or lithographic method by encapsulated layer（3）It is thinned to and exposes metal coupling（2）Surface, and
Metal coupling（2）Surface the side that nickel dam re-forms the nickel-gold layer of layer gold or passes through chemical plating is initially formed by the method for chemical plating
Method forms tin layers；
Step 5,180 degree is spun upside down, to silicon substrate（11）Another side by rubbing down, corrosion or lithographic method carry out it is thinning,
Residual thickness H is 200~1000 microns；
Step 6, mask or tool by ring-type（16）Protection silicon substrate（11）Edge, by corrosion or lithographic method go
Except silicon substrate（11）Central region expose the exiting surface of epitaxial layer（121）, while retaining silicon substrate（11）Fringe region, shape
Circlewise die cavity（111）, and to the exiting surface of exposed epitaxial layer（121）Carry out microstructure graph treatment；
Step 7, the epitaxial layer for splitting completion micro-structural treatment by etching, corrosion or laser ablation methods（12）, formed in length and breadth
Epitaxial layer interval staggeredly（122）；
Step 8, in ring-type die cavity（111）It is interior that phosphor powder layer is formed by spraying or electrophoresis method（4）；
Step 9, in phosphor powder layer（4）Surface photic zone is formed by the method for dispensing or printing rubber（5）；
Step 10, along epitaxial layer be spaced（122）Cutting, forms the encapsulation monomer of independent photodiode.
2. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：The fluorescent material
Layer（4）Thickness be less than silicon substrate（11）Residual thickness H.
3. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：In step 2
In, the bump technology includes step：In epitaxial layer（12）Surface sequentially pass through splash-proofing sputtering metal Seed Layer, by photoetching process
Formed photoresist opening figure, in photoresist opening electroplated conductive metal, removed with degumming process remaining photoresist and
The invalid metal seed layer of erosion removal, forms metal coupling（2）Array.
4. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：In step 4
In, the metal coupling（2）Height h scope be 20~200 microns.
5. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 4, it is characterised in that：In step 4
In, the metal coupling（2）Height h scope be 60~80 microns.
6. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：In step 5
In, the silicon substrate（11）Residual thickness H be 500~700 microns.
7. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：In step 6
In, the silicon substrate（11）Fringe region width D be 500~10000 microns.
8. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 7, it is characterised in that：In step 6
In, the silicon substrate（11）Fringe region width D be 800~5000 microns.
9. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 1, it is characterised in that：In step 7
In, epitaxial layer interval（122）Depth be not less than epitaxial layer（12）Thickness.
10. the wafer-level encapsulation method of a kind of semiconductor devices according to claim 9, it is characterised in that：In step 7
In, the epitaxial layer interval（122）Bottom carry out roughening treatment, the roughening treatment is to be spaced epitaxial layer（122）Bottom
Portion forms the Non-smooth surface face with microstructure by the method for dry etching, cutting or laser ablation.
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