CN104391147A - Low error oscilloscope with improved amplifier structure - Google Patents
Low error oscilloscope with improved amplifier structure Download PDFInfo
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- CN104391147A CN104391147A CN201410679518.2A CN201410679518A CN104391147A CN 104391147 A CN104391147 A CN 104391147A CN 201410679518 A CN201410679518 A CN 201410679518A CN 104391147 A CN104391147 A CN 104391147A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0218—Circuits therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0218—Circuits therefor
- G01R13/0272—Circuits therefor for sampling
Abstract
The invention discloses a low error oscilloscope with an improved amplifier structure, and the Low error oscilloscope with the improved amplifier structure comprises an attenuator, a pre-amplifier, a sampling apparatus, an analog-digital converter, a storage, a sampling clock, a time-base circuit, a crystal oscillator, a central processing unit (CPU), a display and an antenna module; the attenuator, the pre-amplifier, the sampling apparatus, the analog-digital converter, the storage, the central processing unit (CPU) and the display are connected orderly; the analog-digital converter is connected to the sampling clock, the time-base circuit is connected to the sampling clock, the crystal oscillator and the central processing unit (CPU) respectively; the central processing unit (CPU) is further connected to the antenna module; the Low error oscilloscope with the improved amplifier structure has strong operational capability and processing function by adopting the CPU, not only is the performance of the oscilloscope strengthened, but a plurality of interfaces capable of being expanded are increased, the circuit of the sampling part is divided into multiple modules, as sampling clock, time-base circuit and crystal oscillator, the error of the internal circuit can be reduced by detailing the function and the internal setting is more human.
Description
Technical field
The invention discloses a kind of low error oscillograph improving amplifier architecture, belong to signal handling equipment field.
Background technology
Oscillograph is as time domain electronic measuring instrument, extremely extensive in fields of measurement application, no matter the research and development of electronic circuit and electronic information, experiment, training, or the place such as the manufacturing, fault diagnosis, testing inspection, oscillographic figure can be seen everywhere.
Along with Continuous Innovation and the development of information and communication technology (ICT), the continuous introducing of all kinds of industry standard, the technology of the end products such as communication facilities, computing machine and consumer electronics in research and development, design and production etc. and environmental requirement also more and more higher, thus also requirements at the higher level are proposed to oscillographic application.
Oscillograph is the characteristic utilizing electronics oscillatron, converts the alternate electrical signal that human eye cannot directly be observed to image, is presented on video screen so that the electronic measuring instrument measured.It observes problem, the requisite important instrument of experiments of measuring result in digital circuit experiment phenomenon, analysis design mothod.
Along with the development of electronic technology, the progress of signal processing technology, existing equipment and testing tool more and more higher to oscillographic requirement, how to improve oscillographic signal transacting precision and accuracy, become the problem needing most solution at present.
The patent No. is 201210301583.2, and patent name is a kind of oscillograph, and this patent proposes the problem of solution for problem in prior art, but this patent does not point out how just to reduce the error of display and to propose corresponding solution.
The patent No. is 201410284448.0, and patent name is a kind of oscillograph, and this patent indicates prior art oscillograph Problems existing, but does not propose the problem of oscillograph error, does not also expand existing oscillographic function simultaneously.
Meanwhile, the further improvement of amplifier circuit is also a practical problems urgently to be resolved hurrily in prior art.
Summary of the invention
Technical matters to be solved by this invention is: for the defect of prior art, a kind of low error oscillograph improving amplifier architecture is provided, adopt CPU, the arithmetic capability of CPU is strong, and processing capacity is powerful, not only enhances oscillographic performance, and add the interface much can expanded, the circuit of sampling section is divided into multiple module by the present invention simultaneously, is divided into sampling clock, time base circuit, crystal oscillator etc., function is carried out refinement.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
Improve a low error oscillograph for amplifier architecture, comprise attenuator, prime amplifier, sampling thief, analog to digital converter, storer, sampling clock, time base circuit, crystal oscillator, central processing unit, display and Anneta module;
Described attenuator, prime amplifier, sampling thief, analog to digital converter, storer, central processing unit, display are connected successively;
Described analog to digital converter is also connected with sampling clock, and described time base circuit is whole with sampling clock, crystal respectively swings device, central processing unit is connected; Described central processing unit is also connected with Anneta module;
Signal enters and enters prime amplifier after attenuator is decayed and carry out signal amplification, signal after amplifying enters sampling thief and samples, signal after over-sampling enters analog to digital converter, digital signal is converted to by simulating signal, time signal enters sampling thief, crystal oscillator provides driving for time base circuit, time base circuit produces pulse signal under the control of central processing unit, be supplied to sampling clock, sampling clock is clock reference when sampling thief provides sampling, the signal being converted into digital signal stores by storer, shown by display screen after entering central processing unit process,
Signal is sent by Anneta module after central processing unit process.
The particular circuit configurations of described prime amplifier comprises the first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, 11 resistance, 12 resistance, first triode, second triode, 3rd triode, 4th triode, wherein, described first electric capacity connects one end of the 8th electric capacity respectively, one end of 6th resistance, the base stage of the first triode, the other end of described 8th electric capacity connects one end of the first resistance, the other end of described first resistance connects one end of the 4th electric capacity, the other end of described 4th electric capacity connects one end of the tenth resistance, and the other end of described tenth resistance connects one end of one end of the 9th resistance, the 7th electric capacity respectively, the other end of described 7th electric capacity connects one end of the 12 resistance, the other end of described 9th resistance connects one end of the 6th electric capacity, one end of the 11 resistance respectively, the other end of described 11 resistance connects the emitter of the 3rd triode, the base stage of described 3rd triode connects the other end of the 6th electric capacity, the collector of described 3rd triode connects one end of the second resistance, the other end of described second resistance connects the emitter of the second triode, one end of the tenth electric capacity, the base stage of the 4th triode respectively, the emitter of described 4th triode connects the other end of the 12 resistance, the collector of described 4th triode connects one end of the 3rd electric capacity, the other end of described 3rd electric capacity connects one end of the 7th resistance, one end of the 5th resistance, one end of the 9th electric capacity, one end of the 3rd resistance, the other end of the 6th resistance respectively, the other end of described 7th resistance connects the other end of the tenth electric capacity, the other end of described 5th resistance connects the collector of the second triode, the base stage of the second triode connects one end of the 5th electric capacity, the other end of described 5th electric capacity connects the collector of the first triode, the other end of the 3rd resistance, the emitter of described first triode connects one end of the second electric capacity, the other end of described second electric capacity connects one end of the 8th resistance, one end of the 4th resistance respectively, the other end of described 4th resistance connects the other end of the 9th electric capacity, the other end of described 8th resistance connects the other end of the 6th electric capacity, the base stage of the 3rd triode respectively.
As further prioritization scheme of the present invention, the chip model that described attenuator adopts is FAC0603.
As further prioritization scheme of the present invention, described central processing unit adopts the model of CPU, described CPU to be MT6129.
As further prioritization scheme of the present invention, the antenna adopted in described Anneta module is micro-strip paster antenna.
As further prioritization scheme of the present invention, also comprise keyboard, described keyboard is connected with controller.
As further prioritization scheme of the present invention, also comprise wave filter, described wave filter is arranged between attenuator and prime amplifier, enters prime amplifier and amplify after the filtering of the signal device after filtering exported via attenuator.
The present invention adopts above technical scheme compared with prior art, there is following technique effect: the present invention adopts CPU, the arithmetic capability of CPU is strong, processing capacity is powerful, not only enhance oscillographic performance, and add the interface much can expanded, the circuit of sampling section is divided into multiple module by the present invention simultaneously, be divided into sampling clock, time base circuit, crystal oscillator etc., function carried out refinement, be conducive to the error reducing internal circuit, improve operating efficiency, inside arranges hommization more, novel in design, is worthy to be popularized.Improve the structure of amplifier, further increase the work efficiency of amplifier.
Accompanying drawing explanation
Fig. 1 is circuit module connection diagram of the present invention.
Fig. 2 is in the present invention, the physical circuit figure of prime amplifier,
Wherein: C1-C10 represents the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity respectively, R1-R12 represents the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance respectively, and D1-D4 represents the first triode, the second triode, the 3rd triode, the 4th triode respectively.
Embodiment
Be described below in detail embodiments of the present invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
Those skilled in the art of the present technique are understandable that, the correlation module related in the present invention and the function of realization thereof are the devices of hardware after improvement and formation thereof, device or system carry computer software programs conventional in prior art or pertinent protocols just can realize, and are not improve computer software programs of the prior art or pertinent protocols.Such as, the computer hardware system after improvement still can realize the specific function of this hardware system by loading existing operation system of software.Therefore, be understandable that, innovation of the present invention is the improvement of hardware module in prior art and connects syntagmatic, but not be only in hardware module for realizing the improvement of software or the agreement of carrying about function.
Those skilled in the art of the present technique are understandable that, the correlation module mentioned in the present invention is the one or more hardware device for performing in step in operation, method, flow process described in the application, measure, scheme.Described hardware device for required object and specialized designs and manufacture, or also can adopt the known device in multi-purpose computer or other known hardware devices.Described multi-purpose computer activates or reconstructs with having storage procedure Selection within it.
Those skilled in the art of the present technique are appreciated that unless expressly stated, and singulative used herein " ", " one ", " described " and " being somebody's turn to do " also can comprise plural form.Should be further understood that, the wording used in instructions of the present invention " comprises " and refers to there is described feature, integer, step, operation, element and/or assembly, but does not get rid of and exist or add other features one or more, integer, step, operation, element, assembly and/or their group.Should be appreciated that, when we claim element to be " connected " or " coupling " to another element time, it can be directly connected or coupled to other elements, or also can there is intermediary element.In addition, " connection " used herein or " coupling " can comprise wireless connections or couple.Wording "and/or" used herein comprises one or more arbitrary unit listing item be associated and all combinations.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, and all terms used herein (comprising technical term and scientific terminology) have the meaning identical with the general understanding of the those of ordinary skill in field belonging to the present invention.Should also be understood that those terms defined in such as general dictionary should be understood to have the meaning consistent with the meaning in the context of prior art, unless and define as here, can not explain by idealized or too formal implication.
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
Circuit module connection diagram of the present invention as shown in Figure 1, comprises attenuator, prime amplifier, sampling thief, analog to digital converter, storer, sampling clock, time base circuit, crystal oscillator, central processing unit, display and Anneta module;
Described attenuator, prime amplifier, sampling thief, analog to digital converter, storer, central processing unit, display are connected successively;
Analog-digital conversion circuit as described is also connected with sampling clock, and described time base circuit is whole with sampling clock, crystal respectively swings device, central processing unit is connected; Described central processing unit is also connected with Anneta module;
Signal enters and enters prime amplifier after attenuator is decayed and carry out signal amplification, signal after amplifying enters sampling thief and samples, signal after over-sampling enters analog to digital converter, digital signal is converted to by simulating signal, time signal enters sampling thief, crystal oscillator provides driving for time base circuit, time base circuit produces pulse signal under the control of central processing unit, be supplied to sampling clock, sampling clock is clock reference when sampling thief provides sampling, the signal being converted into digital signal stores by storer, shown by display screen after entering central processing unit process,
Signal is sent by Anneta module after central processing unit process.
In the present invention, the physical circuit figure of prime amplifier as shown in Figure 2, the particular circuit configurations of described prime amplifier comprises the first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, 11 resistance, 12 resistance, first triode, second triode, 3rd triode, 4th triode, wherein, described first electric capacity connects one end of the 8th electric capacity respectively, one end of 6th resistance, the base stage of the first triode, the other end of described 8th electric capacity connects one end of the first resistance, the other end of described first resistance connects one end of the 4th electric capacity, the other end of described 4th electric capacity connects one end of the tenth resistance, and the other end of described tenth resistance connects one end of one end of the 9th resistance, the 7th electric capacity respectively, the other end of described 7th electric capacity connects one end of the 12 resistance, the other end of described 9th resistance connects one end of the 6th electric capacity, one end of the 11 resistance respectively, the other end of described 11 resistance connects the emitter of the 3rd triode, the base stage of described 3rd triode connects the other end of the 6th electric capacity, the collector of described 3rd triode connects one end of the second resistance, the other end of described second resistance connects the emitter of the second triode, one end of the tenth electric capacity, the base stage of the 4th triode respectively, the emitter of described 4th triode connects the other end of the 12 resistance, the collector of described 4th triode connects one end of the 3rd electric capacity, the other end of described 3rd electric capacity connects one end of the 7th resistance, one end of the 5th resistance, one end of the 9th electric capacity, one end of the 3rd resistance, the other end of the 6th resistance respectively, the other end of described 7th resistance connects the other end of the tenth electric capacity, the other end of described 5th resistance connects the collector of the second triode, the base stage of the second triode connects one end of the 5th electric capacity, the other end of described 5th electric capacity connects the collector of the first triode, the other end of the 3rd resistance, the emitter of described first triode connects one end of the second electric capacity, the other end of described second electric capacity connects one end of the 8th resistance, one end of the 4th resistance respectively, the other end of described 4th resistance connects the other end of the 9th electric capacity, the other end of described 8th resistance connects the other end of the 6th electric capacity, the base stage of the 3rd triode respectively.
As further prioritization scheme of the present invention, the chip model that described attenuator adopts is FAC0603.
As further prioritization scheme of the present invention, described central processing unit adopts the model of CPU, described CPU to be MT6129, CPU is compared to single-chip microcomputer, and performance is more complete, and inner structure is also more complicated, the function that can realize is also more, can be faster at processing signals medium velocity.
As further prioritization scheme of the present invention, the antenna adopted in described Anneta module is micro-strip paster antenna, and micro-strip paster antenna uses the most extensive, and its volume can be accomplished very little, and signal frequency is more accurate.
As further prioritization scheme of the present invention, also comprise keyboard, described keyboard is connected with controller.
As further prioritization scheme of the present invention, also comprise wave filter, described wave filter is arranged between attenuator and prime amplifier, enters prime amplifier and amplify after the filtering of the signal device after filtering exported via attenuator.
Described display is touch-screen, is provided with operation interface in controller, is shown by display screen, for operation.
As further prioritization scheme of the present invention, the chip that described sampling clock adopts is DS1302, and this chip can directly be connected with single-chip microcomputer, realizes clock, avoids the problem arranging separately clock in single-chip microcomputer inside in the past, goes wrong and be convenient to search.
As further prioritization scheme of the present invention, also comprise keyboard, described keyboard is connected with controller, display in the present invention has contact action function, adds both cooperatings after keyboard, convenient during use, improve operating efficiency, when a side goes wrong, have alternatives.
By reference to the accompanying drawings embodiments of the present invention are explained in detail above, but the present invention is not limited to above-mentioned embodiment, in the ken that those of ordinary skill in the art possess, can also makes a variety of changes under the prerequisite not departing from present inventive concept.The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to technical spirit of the present invention, within the spirit and principles in the present invention, to any simple amendment that above embodiment is done, equivalent replacement and improvement etc., within the protection domain all still belonging to technical solution of the present invention.
Claims (6)
1. improve a low error oscillograph for amplifier architecture, it is characterized in that: comprise attenuator, prime amplifier, sampling thief, analog to digital converter, storer, sampling clock, time base circuit, crystal oscillator, central processing unit, display and Anneta module;
Described attenuator, prime amplifier, sampling thief, analog to digital converter, storer, central processing unit, display are connected successively;
Described analog to digital converter is also connected with sampling clock, and described time base circuit is whole with sampling clock, crystal respectively swings device, central processing unit is connected; Described central processing unit is also connected with Anneta module;
Signal enters and enters prime amplifier after attenuator is decayed and carry out signal amplification, signal after amplifying enters sampling thief and samples, signal after over-sampling enters analog to digital converter, digital signal is converted to by simulating signal, time signal enters sampling thief, crystal oscillator provides driving for time base circuit, time base circuit produces pulse signal under the control of central processing unit, be supplied to sampling clock, sampling clock is clock reference when sampling thief provides sampling, the signal being converted into digital signal stores by storer, shown by display screen after entering central processing unit process,
Signal is sent by Anneta module after central processing unit process;
The particular circuit configurations of described prime amplifier comprises the first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, 11 resistance, 12 resistance, first triode, second triode, 3rd triode, 4th triode, wherein, described first electric capacity connects one end of the 8th electric capacity respectively, one end of 6th resistance, the base stage of the first triode, the other end of described 8th electric capacity connects one end of the first resistance, the other end of described first resistance connects one end of the 4th electric capacity, the other end of described 4th electric capacity connects one end of the tenth resistance, and the other end of described tenth resistance connects one end of one end of the 9th resistance, the 7th electric capacity respectively, the other end of described 7th electric capacity connects one end of the 12 resistance, the other end of described 9th resistance connects one end of the 6th electric capacity, one end of the 11 resistance respectively, the other end of described 11 resistance connects the emitter of the 3rd triode, the base stage of described 3rd triode connects the other end of the 6th electric capacity, the collector of described 3rd triode connects one end of the second resistance, the other end of described second resistance connects the emitter of the second triode, one end of the tenth electric capacity, the base stage of the 4th triode respectively, the emitter of described 4th triode connects the other end of the 12 resistance, the collector of described 4th triode connects one end of the 3rd electric capacity, the other end of described 3rd electric capacity connects one end of the 7th resistance, one end of the 5th resistance, one end of the 9th electric capacity, one end of the 3rd resistance, the other end of the 6th resistance respectively, the other end of described 7th resistance connects the other end of the tenth electric capacity, the other end of described 5th resistance connects the collector of the second triode, the base stage of the second triode connects one end of the 5th electric capacity, the other end of described 5th electric capacity connects the collector of the first triode, the other end of the 3rd resistance, the emitter of described first triode connects one end of the second electric capacity, the other end of described second electric capacity connects one end of the 8th resistance, one end of the 4th resistance respectively, the other end of described 4th resistance connects the other end of the 9th electric capacity, the other end of described 8th resistance connects the other end of the 6th electric capacity, the base stage of the 3rd triode respectively.
2. a kind of low error oscillograph improving amplifier architecture as claimed in claim 1, is characterized in that: the chip model that described attenuator adopts is FAC0603.
3. a kind of low error oscillograph improving amplifier architecture as claimed in claim 1, is characterized in that: the model of described central processing unit is MT6129.
4. a kind of low error oscillograph improving amplifier architecture as claimed in claim 3, is characterized in that: the antenna adopted in described Anneta module is micro-strip paster antenna.
5. a kind of low error oscillograph improving amplifier architecture as claimed in claim 1, it is characterized in that: also comprise keyboard, described keyboard is connected with controller.
6. a kind of low error oscillograph improving amplifier architecture as claimed in claim 1, it is characterized in that: also comprise wave filter, described wave filter is arranged between attenuator and prime amplifier, enters prime amplifier and amplify after the filtering of the signal device after filtering exported via attenuator.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410679518.2A CN104391147B (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087672.4A CN106771457A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087668.8A CN106841732A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087669.2A CN106841733A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087673.9A CN106872745A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087674.3A CN106872746A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710088296.0A CN106855581A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410679518.2A CN104391147B (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710087673.9A Division CN106872745A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710088296.0A Division CN106855581A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087672.4A Division CN106771457A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087669.2A Division CN106841733A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087674.3A Division CN106872746A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087668.8A Division CN106841732A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
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| CN104391147A true CN104391147A (en) | 2015-03-04 |
| CN104391147B CN104391147B (en) | 2017-03-15 |
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| CN201710087673.9A Withdrawn CN106872745A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087669.2A Withdrawn CN106841733A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201410679518.2A Active CN104391147B (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087674.3A Withdrawn CN106872746A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710088296.0A Pending CN106855581A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087668.8A Withdrawn CN106841732A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087672.4A Pending CN106771457A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
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| CN201710087673.9A Withdrawn CN106872745A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087669.2A Withdrawn CN106841733A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
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| CN201710088296.0A Pending CN106855581A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
| CN201710087668.8A Withdrawn CN106841732A (en) | 2014-11-25 | 2014-11-25 | Improve the low error oscillograph of amplifier architecture |
| CN201710087672.4A Pending CN106771457A (en) | 2014-11-25 | 2014-11-25 | A kind of low error oscillograph for improving amplifier architecture |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN106855581A (en) | 2017-06-16 |
| CN106872746A (en) | 2017-06-20 |
| CN104391147B (en) | 2017-03-15 |
| CN106872745A (en) | 2017-06-20 |
| CN106841733A (en) | 2017-06-13 |
| CN106841732A (en) | 2017-06-13 |
| CN106771457A (en) | 2017-05-31 |
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