CN104375972B - 用于可配置数学硬件加速器的微处理器集成配置控制器 - Google Patents
用于可配置数学硬件加速器的微处理器集成配置控制器 Download PDFInfo
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- CN104375972B CN104375972B CN201410403538.7A CN201410403538A CN104375972B CN 104375972 B CN104375972 B CN 104375972B CN 201410403538 A CN201410403538 A CN 201410403538A CN 104375972 B CN104375972 B CN 104375972B
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7885—Runtime interface, e.g. data exchange, runtime control
- G06F15/7889—Reconfigurable logic implemented as a co-processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Stored Programmes (AREA)
- Advance Control (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/968,844 | 2013-08-16 | ||
US13/968,844 US9785444B2 (en) | 2013-08-16 | 2013-08-16 | Hardware accelerator configuration by a translation of configuration data |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104375972A CN104375972A (zh) | 2015-02-25 |
CN104375972B true CN104375972B (zh) | 2018-04-06 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410403538.7A Active CN104375972B (zh) | 2013-08-16 | 2014-08-15 | 用于可配置数学硬件加速器的微处理器集成配置控制器 |
Country Status (2)
Country | Link |
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US (1) | US9785444B2 (zh) |
CN (1) | CN104375972B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
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US9785444B2 (en) | 2013-08-16 | 2017-10-10 | Analog Devices Global | Hardware accelerator configuration by a translation of configuration data |
US9483291B1 (en) * | 2015-01-29 | 2016-11-01 | Altera Corporation | Hierarchical accelerator registry for optimal performance predictability in network function virtualization |
CN104778148A (zh) * | 2015-04-03 | 2015-07-15 | 哈尔滨工业大学 | 基于fpga的动态可重构嵌入式数据协处理平台及采用该平台实现的数据处理方法 |
WO2016184525A1 (en) * | 2015-05-21 | 2016-11-24 | Projoule Gmbh | Apparatus and method for configuring a microcontroller system |
JP6515771B2 (ja) * | 2015-10-07 | 2019-05-22 | 富士通コネクテッドテクノロジーズ株式会社 | 並列処理装置及び並列処理方法 |
US20170153892A1 (en) * | 2015-11-30 | 2017-06-01 | Intel Corporation | Instruction And Logic For Programmable Fabric Hierarchy And Cache |
CN105824706B (zh) * | 2015-12-31 | 2020-11-06 | 华为技术有限公司 | 一种配置加速器的方法和装置 |
CN105930598B (zh) * | 2016-04-27 | 2019-05-03 | 南京大学 | 一种基于控制器流水架构的层次化信息处理方法及电路 |
US10031760B1 (en) * | 2016-05-20 | 2018-07-24 | Xilinx, Inc. | Boot and configuration management for accelerators |
US11086967B2 (en) * | 2017-03-01 | 2021-08-10 | Texas Instruments Incorporated | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) |
US10275217B2 (en) * | 2017-03-14 | 2019-04-30 | Samsung Electronics Co., Ltd. | Memory load and arithmetic load unit (ALU) fusing |
CN108446096B (zh) | 2018-03-21 | 2021-01-29 | 杭州中天微系统有限公司 | 数据计算系统 |
US10802995B2 (en) * | 2018-07-26 | 2020-10-13 | Xilinx, Inc. | Unified address space for multiple hardware accelerators using dedicated low latency links |
GB2577890B (en) * | 2018-10-08 | 2021-03-10 | Advanced Risc Mach Ltd | Data processing with swizzle operation |
FR3087907B1 (fr) * | 2018-10-24 | 2021-08-06 | St Microelectronics Grenoble 2 | Microcontroleur destine a executer un traitement parametrable |
FR3087908B1 (fr) * | 2018-10-24 | 2021-08-06 | St Microelectronics Grenoble 2 | Microcontroleur capable d'executer de facon acceleree un traitement parametrable |
US10713196B1 (en) * | 2018-12-20 | 2020-07-14 | Intel Corporation | Flexible and scalable accelerator architecture |
CN111338769B (zh) * | 2019-12-31 | 2023-08-29 | 深圳云天励飞技术有限公司 | 一种数据处理方法、装置及计算机可读存储介质 |
US20220100575A1 (en) * | 2020-09-25 | 2022-03-31 | Huawei Technologies Co., Ltd. | Method and apparatus for a configurable hardware accelerator |
CN112163187B (zh) * | 2020-11-18 | 2023-07-07 | 无锡江南计算技术研究所 | 一种超长点数高性能fft计算装置 |
EP4080354A1 (en) * | 2021-04-23 | 2022-10-26 | Nxp B.V. | Processor and instruction set |
EP4394616A1 (en) * | 2022-12-29 | 2024-07-03 | STMicroelectronics S.r.l. | Programmable hardware accelerator controller |
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EP0410778A3 (en) | 1989-07-28 | 1992-12-02 | Texas Instruments Incorporated | Graphics processor having a floating point coprocessor |
US5721945A (en) * | 1996-05-06 | 1998-02-24 | Advanced Micro Devices | Microprocessor configured to detect a DSP call instruction and to direct a DSP to execute a routine corresponding to the DSP call instruction |
EP0945788B1 (en) | 1998-02-04 | 2004-08-04 | Texas Instruments Inc. | Data processing system with digital signal processor core and co-processor and data processing method |
EP0992895A1 (en) | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Hardware accelerator for data processing systems |
US6526430B1 (en) | 1999-10-04 | 2003-02-25 | Texas Instruments Incorporated | Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing) |
US6842844B1 (en) * | 2000-02-24 | 2005-01-11 | Agere Systems Inc. | Parameter memory for hardware accelerator |
US20030028751A1 (en) * | 2001-08-03 | 2003-02-06 | Mcdonald Robert G. | Modular accelerator framework |
US7228401B2 (en) | 2001-11-13 | 2007-06-05 | Freescale Semiconductor, Inc. | Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor |
EP1391812A1 (en) | 2002-08-20 | 2004-02-25 | Texas Instruments Incorporated | Hardware accelerator for performing division |
US7430652B2 (en) * | 2003-03-28 | 2008-09-30 | Tarari, Inc. | Devices for performing multiple independent hardware acceleration operations and methods for performing same |
JP4224430B2 (ja) | 2003-07-07 | 2009-02-12 | 株式会社ルネサステクノロジ | 情報処理装置 |
US20060179273A1 (en) | 2005-02-09 | 2006-08-10 | Advanced Micro Devices, Inc. | Data processor adapted for efficient digital signal processing and method therefor |
US7669037B1 (en) * | 2005-03-10 | 2010-02-23 | Xilinx, Inc. | Method and apparatus for communication between a processor and hardware blocks in a programmable logic device |
US7856546B2 (en) * | 2006-07-28 | 2010-12-21 | Drc Computer Corporation | Configurable processor module accelerator using a programmable logic device |
US7953221B2 (en) * | 2006-12-28 | 2011-05-31 | Intel Corporation | Method for processing multiple operations |
US8275975B2 (en) * | 2008-01-25 | 2012-09-25 | Mtekvision Co., Ltd. | Sequencer controlled system and method for controlling timing of operations of functional units |
US8239442B2 (en) | 2008-08-08 | 2012-08-07 | Analog Devices, Inc. | Computing module for efficient FFT and FIR hardware accelerator |
US9785444B2 (en) | 2013-08-16 | 2017-10-10 | Analog Devices Global | Hardware accelerator configuration by a translation of configuration data |
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2013
- 2013-08-16 US US13/968,844 patent/US9785444B2/en active Active
-
2014
- 2014-08-15 CN CN201410403538.7A patent/CN104375972B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US9785444B2 (en) | 2017-10-10 |
US20150052332A1 (en) | 2015-02-19 |
CN104375972A (zh) | 2015-02-25 |
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