CN104370270A - Method for preparing silicon oxide nano island array by precise positioning - Google Patents
Method for preparing silicon oxide nano island array by precise positioning Download PDFInfo
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- CN104370270A CN104370270A CN201410667606.0A CN201410667606A CN104370270A CN 104370270 A CN104370270 A CN 104370270A CN 201410667606 A CN201410667606 A CN 201410667606A CN 104370270 A CN104370270 A CN 104370270A
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Abstract
The invention relates to a method for preparing a silicon oxide nano island array by precise positioning. The method is characterized in that a sacrificial layer corrosion technology is utilized, and contact exposure photoetching and wet-process corrosion processes are utilized, that is, the product is prepared by carrying out three times of photoetching process and three times of BOE corrosion process. According to the method, a unique design is combined on the basis of a traditional method 'from top to bottom'; direct writing is carried out without the help of an electron beam or a focusing ion beam; and the precise positioning machining and manufacturing of the silicon oxide nano island array can be realized by only combining the contact exposure technology with the precisely-controlled sacrificial layer corrosion technology. The method is skillful in design, simple in process, low in manufacturing cost, and easy to manufacture in batches.
Description
Technical field
The present invention relates to a kind of method preparing monox nanometer island array, the present invention relates to a kind of accurate positioning or rather for the method for monox nanometer island array, belong to technical field of semiconductors.
Background technology
Nanometer technology refers to research electronics, atom and other types of materials characteristics of motion, interaction and characteristic in nanometer-scale spatial (1nm ~ 100nm), and in this range scale, atom, molecule etc. handled and process, and realize the science and technology of the multi-crossed disciplines of peculiar function and intelligence effect in the application.When a kind of structure of material enters nanoscale features scope, can there is marked change in its certain or some characteristic, show the specific physical effect that many body materials do not have, and makes nanometer technology become the focus of research.
Nanofabrication technique is then the important branch of nanometer technology, and the method preparing nano material at present mainly can be divided into two classes.One is the method for " from bottom to top " (bottom-up), namely adopt the methods such as chemical vapor deposition, physical vapor deposition, laser ablation, catalyst auxiliary under on large-area substrate randomly or part directionally grow nano material.This processing mode takes full advantage of the feature of material self, can realize the structure to device, the isoparametric accurate control of size in theory.But the method working (machining) efficiency is relatively low, repeatable poor, operation inconvenience, is difficult to location, can not meet the requirement that large-scale integrated manufactures.Another kind is the method for " from top to bottom " (top-down), namely adopts the process being similar to traditional integrated circuit to make nano material.This method is on the material layer prepared, and by modes such as photoetching, etching and depositions, produces required figure.The advantage of this method is that manufacture craft accuracy is higher, and the size of nano wire is convenient to control, and figure accurate positioning.But the precision that traditional processing technology makes it process due to the inherent characteristic of light source is difficult to further improve, nano graph many employings electron beam that current employing " from top to bottom " makes or FIB exposure, the deficiency brought thus is that cost of manufacture is expensive, production efficiency is low, is unfavorable for batch production.And the present invention intends the sacrifice layer corrosion technology utilizing controllable precise, devise a kind of technique simple, cost of manufacture is low, is easy to the nanoprocessing method of batch micro operations, not by means of electron beam or FIB exposure, the processing and manufacturing of the controlled monox nanometer island array of size can be realized.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of accurate positioning for the method for monox nanometer island array, also namely the present invention proposes a kind of method utilizing sacrifice layer corrosion technology to prepare monox nanometer island array accurate as to position.This method is on the basis of tradition " from top to bottom " method, in conjunction with unique design, not by means of electron beam or FIB exposure, only with the sacrifice layer corrosion technology that contact exposure combine with technique accurately controls, achieve the accurate location processing and manufacturing of monox nanometer island array.This method deft design, technique is simple, and cost of manufacture is low, is easy to batch micro operations, for the extensive accurately location manufacture of silicon nano material is had laid a good foundation.
Described method utilizes sacrifice layer corrosion technology, uses contact exposure photoetching and wet corrosion technique, namely by third photo etching technique with carry out three BOE etching process preparations.
Specifically, method of the present invention specifically comprises the steps: single sheet of throwing to put into oxidation furnace, uses thermal oxidation process to grow one deck silica (SiO
2) film; Carry out photoetching process, define the array of micron level figure; Carry out BOE (buffered oxide etching) etching process, remove not by the oxide layer film that photoresist is protected, prepare the array of micron level silica figure; Again carry out photoetching process, in the micron level silica graphics field of having prepared, define a corrosion window slightly less than figure; Again carry out BOE etching process, by the sacrifice layer corrosion accurately controlled, prepare silica white nano-wire; Again carry out photoetching process, the silica white nano-wire prepared defines corrosion window; Again carry out BOE etching process, by the sacrifice layer corrosion accurately controlled, prepare monox nanometer island array.The method preparing monox nanometer island array provided by the present invention is the contact exposure photoetching process utilizing micron accuracy, in conjunction with the sacrifice layer corrosion technology accurately controlled, prepare monox nanometer island array accurate as to position, specific design is accurate, technique is simple, cost of manufacture is low, and can the advantage of batch micro operations.
Realizing technical scheme of the present invention is:
1) one is provided singly to throw silicon chip;
2) at described grown above silicon SiO
2film;
3) first time photoetching process is carried out, by described SiO
2film patterning, form the first corrosion window;
4) carry out BOE etching process, remove the SiO exposed along the first corrosion window
2film, corrosion terminates rear removal photoresist;
5) second time photoetching process is carried out, by remaining SiO
2film patterning, form the second corrosion window; Second corrosion window is slightly less than the unexposed area in first time photoetching process;
6) carry out BOE etching process, remove the SiO exposed along the second corrosion window
2film, and proceed first time sacrifice layer corrosion, form SiO
2nano wire, corrosion terminates rear removal photoresist;
7) third time photoetching process is carried out, by SiO
2nano wire is graphical, forms the 3rd corrosion window;
8) carry out BOE etching process, remove the SiO exposed along the 3rd corrosion window
2, and proceed second time sacrifice layer corrosion, form SiO
2nano island array, corrosion terminates rear removal photoresist.
Preferably, described step 2) SiO
2film thickness is 18-22nm.
Preferably, step 3 described in described step), 5), 7) in photoetching process be contact exposure photoetching, described step 4), 6), 8) in BOE etching process be wet corrosion technique under normal temperature.
Preferably, described step 4) in the BOE etching process time be 20s-40s.
Preferably, described step 5) in the second corrosion window lower edges apart from SiO
2film edge is 0.8 μm-1.2 μm.
Preferably, described step 6) it is middle that the sacrifice layer corrosion time is 12-15min for the first time.
Preferably, described step 7) in the 3rd corrosion window be 1 × 6 corrosion window array, single window size 2 μm × 6 μm in corrosion window array, adjacent window apertures spacing 2 μm.
Preferably, described step 8) it is middle that the sacrifice layer corrosion time is 10-12min for the second time.
The present invention is on the basis of tradition " from top to bottom " method, in conjunction with unique design, not by means of electron beam or FIB exposure, only accurately control ground sacrifice layer corrosion technology with contact exposure combine with technique, the method preparing monox nanometer island array provided by the present invention is the contact exposure photoetching process utilizing micron accuracy, in conjunction with the sacrifice layer corrosion technology accurately controlled, prepare monox nanometer island array accurate as to position, specific design is accurate, technique is simple, cost of manufacture is low, and can the advantage of batch micro operations.
Accompanying drawing explanation
Fig. 1 is shown as present invention process schematic flow sheet.
Wherein, scheming a display is grown to have 20nm SiO
2silicon chip schematic diagram thrown by the list of film.
Figure b is shown as through first time photoetching with after the BOE corrosion of the first corrosion window, residue SiO
2the schematic diagram of film.
Figure c is shown as the second corrosion window schematic diagram that second time photoetching is formed.
SiO is formed after figure d is shown as first time sacrifice layer corrosion
2the structural representation of nano wire.
Figure e is shown as the 3rd corrosion window schematic diagram that third time photoetching is formed.
Figure f forms SiO after being shown as second time sacrifice layer corrosion
2the structural representation of nano island array.
Fig. 2 is shown as SEM and the AFM token image of monox nanometer island array prepared by the present invention.
Wherein, a is shown as the SEM image of the monox nanometer island array of preparation, and b is shown as the SEM image of single silica rectangle nano island.
C is shown as the AFM 3D rendering of the single silica rectangle nano island of preparation.
Detailed description of the invention
Below by way of instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this description can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by detailed description of the invention different in addition, and the every details in this description also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to shown in accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment
Embodiment 1: throw on sheet at silicon list and adopt following steps:
A) silicon list is thrown sheet and be placed in thermal oxidation furnace;
B) one deck SiO is grown
2film, film thickness is 20nm;
C) carry out photoetching process, define the rectangular graph array of 40 μm × 10 μm;
D) carry out normal temperature BOE etching process, remove not by the oxide layer film that photoresist is protected, etching time is 30s, removes the photoresist on silicon chip after corrosion;
E) carry out photoetching process, in the micron level silica graphics field of having prepared, define the corrosion window of one 30 μm × 8 μm, window lower edges is 1 μm apart from silica pattern edge;
F) carry out normal temperature BOE etching process, by the sacrifice layer corrosion accurately controlled, prepare silica white nano-wire, etching time is 15min, removes the photoresist on silicon chip after corrosion;
G) carry out photoetching process, the silica white nano-wire prepared defines 2 × 6 corrosion window arrays, single window size is 2 μm × 6 μm, window pitch 2 μm;
H) carry out BOE etching process, by the sacrifice layer corrosion accurately controlled, prepare monox nanometer island array, etching time is 10min, removes the photoresist on silicon chip after corrosion.
Claims (9)
1. an accurate positioning is for the method for monox nanometer island array, it is characterized in that described method utilizes sacrifice layer corrosion technology, use contact exposure photoetching and wet corrosion technique, namely by third photo etching technique with carry out three BOE etching process preparations.
2., by method according to claim 1, it is characterized in that concrete steps are:
1) one is provided singly to throw silicon chip;
2) at described grown above silicon SiO
2film;
3) first time photoetching process is carried out, by described SiO
2film patterning, form the first corrosion window;
4) carry out BOE etching process, remove the SiO exposed along the first corrosion window
2film, corrosion terminates rear removal photoresist;
5) second time photoetching process is carried out, by remaining SiO
2film patterning, form the second corrosion window; Second corrosion window is slightly less than the unexposed area in first time photoetching process;
6) carry out BOE etching process, remove the SiO exposed along the second corrosion window
2film, and proceed first time sacrifice layer corrosion, form SiO
2nano wire, corrosion terminates rear removal photoresist;
7) third time photoetching process is carried out, by SiO
2nano wire is graphical, forms the 3rd corrosion window;
8) carry out BOE etching process, remove the SiO exposed along the 3rd corrosion window
2, and proceed second time sacrifice layer corrosion, form SiO
2nano island array, corrosion terminates rear removal photoresist;
Described step 3), 5), 7) in photoetching process be contact exposure photoetching, described step 4), 6), 8) in BOE etching process be wet corrosion technique under normal temperature.
3. method according to claim 2, is characterized in that step 2) described in SiO
2film thickness is 18-22nm.
4. method according to claim 2, is characterized in that described step 4) in time of BOE etching process be 20s-40s.
5. method according to claim 2, is characterized in that described step 5) in the lower edges of the second corrosion window apart from SiO
2film edge is 0.8 μm-1.2 μm.
6. method according to claim 2, is characterized in that described step 6) it is middle that the sacrifice layer corrosion time is 12-15min for the first time.
7. method according to claim 2, is characterized in that described step 7) in the 3rd corrosion window be 1 × 6 corrosion window array.
8. in accordance with the method for claim 7, it is characterized in that in corrosion window array, single window is of a size of 2 μm × 6 μm, adjacent window apertures spacing 2 μm.
9. method according to claim 2, is characterized in that, described step 8) it is middle that the sacrifice layer corrosion time is 10-12min for the second time.
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| CN102983212A (en) * | 2012-11-06 | 2013-03-20 | 华南师范大学 | Preparation method for crystalline silicon solar cell nanometer transparent buried gate electrode |
| CN103030096A (en) * | 2011-10-09 | 2013-04-10 | 中国科学院高能物理研究所 | Silicon material with nano-structure surface and manufacturing method thereof |
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Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030052080A1 (en) * | 1999-01-27 | 2003-03-20 | Young Joon Baik | Method for fabricating nano-sized diamond whisker, and nano-sized diamond whisker fabricated thereby |
| CN101305280A (en) * | 2005-06-10 | 2008-11-12 | 吉卢比有限公司 | Diagnostic-nanosensor and its use in medicine |
| CN101086966A (en) * | 2006-06-07 | 2007-12-12 | 中国科学院微电子研究所 | A making method for nano coulomb structure |
| WO2008072498A1 (en) * | 2006-12-13 | 2008-06-19 | National Institute Of Advanced Industrial Science And Technology | Mold for optical element, having nanostructure, mold for nanostructure, method for manufacturing the mold, and optical element |
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