CN104365178A - Led芯片载体中集成的零能量存储驱动器 - Google Patents
Led芯片载体中集成的零能量存储驱动器 Download PDFInfo
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- CN104365178A CN104365178A CN201380005967.2A CN201380005967A CN104365178A CN 104365178 A CN104365178 A CN 104365178A CN 201380005967 A CN201380005967 A CN 201380005967A CN 104365178 A CN104365178 A CN 104365178A
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- led
- chip carrier
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Abstract
提供包括在LED芯片载体上的LED芯片的LED器件。所述LED器件可以进而容纳于封装(诸如小外形晶体管(SOT)封装或径向LED器件封装)中。可以从AC(线路)电压或其被整流的版本直接操作单个LED器件或多个这样的LED器件的串联连接。在一些示例实施例中,开关电路集成到所述LED芯片载体中,以用于响应于例如亮度调节控制信号而控制流过(多个)LED的电流。提供整体LED器件的大量示例实施例,包括用于这样的LED器件的制造处理以及各种示例封装。
Description
相关申请
本申请要求于2012年1月20日提交的美国临时申请No.61/588,838的优先权。这些申请中的每一个被通过在其整体上进行引用而并入于此。
技术领域
本申请涉及照明系统,并且更具体地说,涉及被配置有集成驱动器电路从而提供整体照明系统的LED器件。
背景技术
发光二级管(LED)和驱动电路是分离地制造的,并且之后被电连接,以提供给定的照明系统。已知用于LED的串联连接的简单且廉价的驱动器由并联于LED串的桥式整流器和滤波电容器构成。可选地,可以添加串联于与LED串的线性电阻控制器。
附图说明
图1a示意性地图解根据本发明实施例的可以使用的零能量存储(ZES)LED驱动器。
图1b图解根据本发明实施例的可以在ZES LED驱动器中使用的示例控制电路的框图。
图2示意性地图解根据本发明实施例的LED芯片载体中所集成的零能量存储(ZES)驱动器。
图3示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图4示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图5示意性地图解根据本发明实施例的被配置有多个LED芯片(配置有集成ZES驱动器)的系统。
图6a图解一些示例像素形状,并且图6b-图6e的每一个图解根据本发明实施例的可以在LED芯片载体中所集成的ZES驱动器中实现的像素的示例横向布置。
图7示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图8示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图9示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图10a图解根据本发明实施例的被配置有集成ZES驱动器的LED器件的截面侧视图。
图10b图解根据本发明另一实施例的被配置有集成ZES驱动器的LED器件的截面侧视图。
图11图解根据本发明另一实施例的被配置有集成ZES驱动器的LED器件的侧视图。
图12示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图13示意性地图解根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。
图14图解根据本发明另一实施例的被配置有集成ZES驱动器的LED器件的截面侧视图。
图15图解易受与LED串的末端相比在LED串的开始处的各像素之间的显著亮度差影响的ZES电路拓扑,假设每组为相同的像素和像素数量。
图16示意性地图解根据本发明另一实施例的被配置有多个LED芯片(被配置有集成ZES驱动器)的系统。
具体实施方式
提供包括在LED芯片载体上的LED芯片的LED器件。所述LED器件可以进而被容纳在封装(诸如小外形晶体管(SOT)封装或径向LED器件封装)中。可以从AC(线路)电压或其被整流的版本直接操作单个LED器件或多个这样的LED器件的串联连接。在一些示例实施例中,开关电路集成到所述LED芯片载体中,以用于响应于例如亮度调节控制信号而控制流过(多个)LED的电流。提供整体LED器件的大量示例实施例,包括用于这样的LED器件的制造处理以及各种示例封装。
概述
如先前所述,LED和驱动电路是分离地制造的,并且之后被电连接。整流器的功能可以通过若干半导体分段的芯片内反并联连接或类似于桥式整流器的这样的分段的连接而集成到LED芯片。然而,这样的配置具有如下缺点:因为光发射只是发生在半波的短时段中,所以所得光源强烈闪烁(半波整流器;50或60Hz光调制)和/或展现出强烈的闪动(strobing)(有时也误解地被称为闪烁)效果。由于从线路抽取的电流基本上看似重复的尖峰序列,因此输入电流波形同样显现为不利的;每个半周期尖峰发生在线路电压的峰值附近。除此之外,在大多数时间里LED在不适宜的条件下被驱动。
图1a图解根据本发明实施例的可以用于克服这些问题的用于LED串的驱动电路。如在该示例实施例中可见那样,LED串(LED的串联连接)被再划分为N个组(组可以包括单个LED或串联连接和/或并联连接的一组LED;所示示例包括每组有三个串联连接的LED)。可以利用基于晶体管的或其它合适的开关技术来实现的并联连接的可控制的开关sw1、sw2、……、swN,从而对各组进行短路。如进一步可见那样,开关响应于控制电路,控制电路被配置为:感测(经由Rsense)流过LED的电流,并且取决于沿着正弦波的实际电压而控制开关,并且由此调整LED串对于瞬时线路电压(或供给电压)的有效长度。干线或其它外部源耦接到整流器电路(D1至D4以及Cin)。该驱动器电路可以通常在此被提及为零能量存储(ZES)驱动器电路。ZES驱动器电路的附加细节可在先前并入的美国申请No.13/229,611中找到。根据一些这样的示例实施例,ZES驱动器电路的全部或至少一部分可以与(多个)LED集成到LED器件中。
存在其中可以执行在此所描述的整体方法的很多方式。例如,在一个示例实施例中,通过例如在用于创建LED的同一结构化处理中制备(与发光二极管并联的)开关以及开关周围的无源组件,一些或所有ZES驱动器电路组件被集成到LED器件中。在这样的示例实施例中,将由相同半导体材料制成电路的所有集成组件。例如,对于蓝光LED、绿光LED、磷转换的白光LED而言,可以利用铟镓氮(InGaN)来实现LED和ZES驱动器电路组件。替换地,对于红光LED、黄光LED、琥珀色光LED而言,可以利用铟镓铝磷(InGaAlP)来实现LED和ZES驱动器电路组件。
取决于期望的LED色彩和照明电路的(多个)目标应用,可以使用大量其它合适的半导体材料。例如,虽然可以利用如上面描述的无机半导体材料来实现在此提供的一些实施例,但同样可以使用有机材料来提供具有集成到OLED器件中的驱动电路的所谓的有机LED(OLED)照明器件。在此,将由有机材料(例如导电聚合物和绝缘聚合物等)制成发光材料以及晶体管和电路的其它电子组件。如根据本公开将领会那样,所要求的发明并非意图被限制于任何特定材料系统。
在一些实施例中,可以利用被编程或另外被配置为如在此解释的那样或如另外期望的那样而控制开关的微控制器来实现控制电路。在一个特定示例实施例中,控制电路可以如图1b所示而被实现,并且包括运算放大器电路、将电力供给至运算放大器电路的电源电路、耦接到可选谐波失真控制电路的电压基准电路以及可选频率稳定电路。电源电路可以是已知的DC电源电路配置,并且在一些实施例中,可以直接或间接从干线或其它电压源供给电力。如将进一步可见那样,电压基准电路被配置为:提供基于电压源(干线或干线的整流输出等)所提供的电压的一小部分的电压。在一些实施例中,该小部分可以是可调整的,因此,使得系统的通过(多个)LED的串的电流(并且因此平均电力)的变化是可能的。该小部分电压提供给谐波失真控制电路,其将该信号耦接到运算放大器电路的非反相输入。谐波失真控制电路也可以将附加DC组件提供给运算放大器电路的正电力输入,以补偿电压源中的电压降,这可以改进电力因子并且减少系统的谐波失真。
监控通过多个LED组中的LED的电流流动的电流监控电路(例如Rsense或一些其它合适的感测电路)的输出通过频率稳定电路耦接到运算放大器电路的反相输入。运算放大器电路被配置为:通过调整其提供给图1a所示的开关(sw1至swN)的控制信号,保持被监控的LED电流流动与来自电压源的输入电压之间的平衡。频率稳定电路被配置为:调整运算放大器电路的频率响应,以避免不期望的振荡。在一些示例的这样的实施例中,频率稳定电路可以包括电阻器-电容器(RC)网络,并且电流监控电路是如图1a所示的电阻器。
一个特定示例实施例提供LED器件,所述LED器件包括LED封装中容纳的LED芯片载体上的LED芯片,其中,LED芯片载体包含ZES驱动器电路的电子组件。LED芯片可以是例如薄膜芯片,其中,外延层从生长衬底转印到芯片载体。随后,生长衬底可以被移除,或者替换地,也可以保留在芯片载体(例如蓝宝石倒装芯片)上。外延层可以被横向划分为通过由附加处理步骤所提供的合适的导体而电串联连接的两个或更多个像素(多像素薄膜LED芯片)。从电的观点来看,像素通常是可以被看作LED的封装器件内的最小发光单元。在一个特定示例实施例中,芯片载体是利用硅实现的,并且包括ZES驱动器电路的电子组件,诸如图1所示的开关(例如晶体管和必要/辅助电子组件,比如晶体管周围的电阻器和二极管),其以集成方式来控制LED组。为此目的,开关可以以每个像素形成一组或串联连接的多于一个的像素形成一组这样的方式而连接到LED像素。可以在外延层到包含芯片载体的ZES驱动器的转印处理期间形成这种电连接。替换地,在例如通过键合引线来分离地执行键合和电连接期间完成仅机械附接。从LED芯片与包含ZES驱动器电路的电子组件的芯片载体集成得到的器件可以然后放置到合适的封装中。
根据本公开,在此所提供的技术的大量优点将是显而易见的。例如,在一些实施例中,在LED周围的附加器件或芯片并非是必须的,这节省了用于LED应用的成本和空间,并且允许非常紧致的线路供电光引擎,具有期望的光学性质。在例如作为光源的所有像素的LED点光可以密集地封装到小面积中的情况下,集光率将更少有问题。此外,由于存在更少的分立式组件和更少的互连(例如焊接结合),因此可以实现鲁棒性和寿命的增加。这还减少了组装时间和成本。
电路架构
图2示意性图解根据本发明实施例的LED芯片载体中所集成的零能量存储(ZES)驱动器。如可见那样,该特定示例实施例包括LED芯片载体,其包括ZES驱动器电路并且具有数目为N的在其上转印或生长的LED外延层。载体芯片可以是LED外延层可以生长或转印到其上的任何合适的衬底,诸如硅、锗、蓝宝石、氮化镓和砷化镓衬底。每个LED有效地提供LED器件的像素。
可以使用典型的半导体加工和材料来实现外延LED。在所示的示例实施例中,在上方(epi-)LED多层结构与衬底之间提供欧姆接触和镜层,以提供对芯片载体(衬底)的机械、热和电连接。每个LED包括所示的夹在p型层与n型层之间的有源层。取决于诸如所使用的材料和期望的性能的因素,其它实施例可以包括其它层,例如粘接层或扩散层。所示的上方材料的三层可以通过一揽子(blanket)方式而形成在衬底上,并且然后刻蚀到不同的LED中;替换地,LED可以被有选择地形成在衬底上。在其它实施例中,上方LED形成在生长衬底上,并且然后转印到衬底(芯片载体)。虽然在衬底上形成上方LED消除了对转印的需要,但假定LED形成处理将不损坏或另外不利地影响衬底(芯片载体)上和/或其内的任何先前所形成的组件。替换地,在一些实施例中,可以在外延LED层生长在衬底上之后形成ZES组件。
在一个特定示例实施例中,利用p型氮化镓来实现第一层(p侧),利用无掺杂氮化铟镓来实现第二(有源)层,并且利用n型氮化镓来实现第三层(n侧)。其它示例实施例可以包括适合于实现上方LED(例如基于铟铝镓磷的LED)的列V和/或III-V材料的任何合适的组合。所要求的发明并非意图被限制于任何特定材料系统;相反地,取决于诸如期望的器件性能的因素,可以利用任何数量的合适的上方LED材料来实现在此所提供的整体方法,如根据本公开将领会的那样。
如将要进一步领会的那样,外延层可以成晶片规模地或芯片接芯片地转印到ZES芯片载体。对于在这样的基于转印的实施例中将外延层键合到ZES芯片载体而言,可以使用比如载体共熔焊接、直接键合或冲压的方法。ZES组件可以位于例如靠近键合界面或在芯片载体的相对侧上而由过孔电连接。注意,完整的ZES电路可以集成到LED芯片载体中,包括桥式整流器和控制电路(比如在图2的示例情况下)。在此情况下,像素的数量可以足够大以直接在线路电压下工作。这是因为,使用大量像素,除了成本,并不存在由在上端上的ZES电路所给定的约束。
LED像素的数量范围可以从两个到VLine/VfPixel。VLine/VfPixel通常提及为最大常期待线路电压(例如,其可以恰高于在线路上的电涌的情况下的电压的幅度)除以单个像素在标称电流下的最小前向电压(考虑例如产生扩展、温度和在寿命上的老化)。组的数量可以在两个与VLine/VfPixel之间变化。为了简化的原因,每个组中的像素的数量可以选取为对于特定电路实现内的所有组而言是相同的,但这并非在此所提供的ZES拓扑的操作原理所强制的。其它实施例可以在各组中的一个或更多个中具有不同数量的像素。如进一步可见那样,存在各像素之间所提供的机械和电分离以及对芯片载体的机械和电连接。如可见那样在进一步参照图2的情况下,可以利用垂直LED像素来完成像素串联连接,其中,一个LED的n侧触点连接到下一像素的p侧。在本发明的该特定示例实施例中,p侧被机械连接到芯片载体。在另一实施例中,这可以是n侧。
图3示意性示出根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。在该示例情况中,可以利用基于UX:3的LED像素来完成像素串联连接,其中,两个触点都位于有源区域的一侧上,并且一个像素的n触点在该侧处连接到下一像素的p触点。串联连接可以例如位于(例如在LED芯片加工期间所沉积的导电层所提供的)LED芯片中或ZES芯片载体内部。如在图3中可见那样,在这样的情况下提供触点过孔,以提供对上方LED的n侧的接入,并且无需n侧触点栅格。OSRAM Opto Semiconductors的UX:3芯片技术采用薄GaN技术,该技术通常采用在半导体有源层之下的金属镜以及良好限定的散射表面,以用于优化的光提取。在一些实施例中,除了像素的横向串联连接以外(或者替换地除了这样的串联连接以外),还可以使用多于一个的有源LED结构的外延堆叠(堆叠的LED)。
图4示意性示出根据本发明另一实施例的LED芯片载体中所集成的ZES驱动器。在该示例情况中,像素化的LED芯片载体仅包括根据芯片上的像素组的数量的可控制开关。可以在外部添加桥式整流器和控制电路组件,并且给定线路电压所需的串联连接中的像素可以位于图4所示的仅一个芯片上,或如图5的示例实施例所示的许多个(N个)不同的芯片上。在该后一示例情况下,芯片通过三个电连接而连接成串。因此,每个芯片具有至少三个电端子或其它电连接的部件:像素组的p侧和n侧以及控制(根据一些实施例,如图5所示的串末端的返回可以添加附加的两个电连接)。
虽然同样可以使用其它更低效的形状(例如圆形、卵形等),但像素的形式可以是例如如图6a所示的正方形、矩形、三角形和六边形。在芯片载体上串联连接的像素的横向布置可以是例如如图6b所示的一行接一行的,或如图6c所示仅一行,或如图6d所示的螺旋形,或诸如如图6e所示的其它期望形状。如将领会的那样,如果对于给定应用而言是这样期望的话,则螺旋形状对于类似点的(非线性)光源而言特别有利。
封装
除了串的末端并不路由通过芯片之外,图7示出根据本发明实施例的与图5所示的相似的单个芯片Cp的电路图。如可见那样,芯片包括像素D1至Dn的组GRP,组GRP连接到其关联的开关SW。芯片具有对周围电路的三个电连接:像素组的p侧上的Jc+、像素组的n侧上的Jc-以及控制电路过孔Jcc。
由晶体管Q、二极管D和电阻器R制成该示例实施例中的可控制开关SW。由于跨晶体管的电压被跨对应开关连接到的组的所有像素的最大前向电压所限制,因此低电压(例如5伏特或更小)在大多数应用中将是足够的。然而,在线路电压应用中,二极管将需要能够阻断高电压,并且因此典型地高电压二极管可以用在这样的情况下。图7还示出用于交变电流的二极管(或所谓的双向元件)Di。
一旦有其中例如像素之一或其互连之一无法打开的故障,可选器件Di可以用于限制晶体管Q的漏极-栅极电压。在没有这种可选双向元件D1的情况下,跨组GRP高电压可能引起晶体管Q归因于高电压或显著的电力耗散而出故障,这最终可能导致开路,并且整个光引擎将无法发射任何光。因此,通过包括双向元件,晶体管可以在这样的故障的情况下接通,并且基本上分流有缺陷的组,导致仍操作的光引擎。增加的故障容限的特征例如在其中几百或甚至更多的像素串联连接的线路电力应用中特别受青睐。
在其它实施例中,替代双向元件Di,可以替代地集成基于晶闸管的电路或甚至电阻器,以实现相似的益处。包括锁存器件(比如双向元件或晶闸管)的电路可以通常是优于简单的电阻器或其它非锁存电路的,因为在它们已经被锁存之后,锁存电路和器件典型地具有跨它们的低降电压,这极大地减少了将另外地在晶体管Q中耗散的电力量。如根据本公开将领会的那样,同样可以使用除了图7所示的示例之外的大量开关方案,包括使用高侧驱动器或光耦接器的各种晶体管布置。参照图7–图9、图12以及图13,注意到虚线框通常用于绘制或参照电路和功能块,而实线框通常用于绘制或参照机械部分。
在本发明另一实施例中,每个单个芯片被封装为器件(诸如表面安装器件(SMD))。这样的器件可以具有至少3个管脚,如图8的示例实施例中所描绘的那样。封装Pk具有三个管脚1、2和3。如进一步可见那样,分别通过连接键合焊盘Jp+和Jc+、Jp-和Jc-以及Jpc和Jcc的键合引线B+、B-来完成从芯片到封装的引线框L的电连接。如将根据本公开而领会的那样,根据实施例,这些封装器件中的若干可以焊接到印刷电路板上,并且形成光引擎。
图9示出像是在图8中所示的封装的类似的SMD封装,但在该示例情况下,封装Pk更像SOT23封装。单个芯片载体Cp被安装到引线框上,以机械地将芯片支承在适当位置,并且建立用于冷却芯片载体的有效热路径。由于芯片载体Cp通过导电焊料焊接到引线框(根据一些实施例),因此形成电连接Jcp-。因此,在该示例配置中,仅两个键合引线B+和Bc出现在封装中。这也如可见那样于图10a的示例实施例的截面侧视图中。表1限定根据一个特定的这样的实施例的在图10a中所使用的各种标记。
标记 | 特征 |
GRP | 包括像素组的薄膜芯片 |
Cp | 芯片载体 |
L | 引线框 |
M | 模制化合物(塑料) |
SiL | 由透明硅化人造橡胶制成的透镜 |
Pin1,Pin2 | 伸出模制化合物的引线框所创建的封装的管脚(pin3未示出) |
表1:示例实现。
根据本公开,大量其它合适的配置和材料根据本发明将是显而易见的,并且所要求的发明并非意图被限制于配置或材料的任何特定集合。
图10b图解与图10a所示的示例实施例十分相似的基于另一SMD封装的实施例的截面侧视图。然而,应注意薄膜芯片GRP具有与芯片载体Cp相同的横向尺寸,并且键合引线Bw完全在透明硅化人造橡胶(或其它合适的这样的材料)的体积的内部。
图11示出根据本发明实施例所配置的带导线的封装Pk中的径向LED器件的侧视图。可以例如通过与图9所示的方式相同或另外地相似的方式来配置封装内部的电子电路。
图12示出根据本发明实施例的包括两个芯片载体Cp1和Cp2的封装Pk。在一些示例情况下,具有五个管脚的像是SOT23-5的封装可以用于此目的。应注意两个芯片载体可以共享控制管脚。如可见那样,虽然根据本公开任何数量的变形和其它实施例将是显而易见的,但为了简化,使用对功能上相同的对象的相同引用。
图13示出根据本发明实施例的保持包括两个开关SW1和SW2的单个芯片载体Cp的封装Pk。此外,芯片载体承载两个像素组GRP1和GRP2。从应用角度来说,用户可能不能在图12与图13所示的各器件之间进行区分。然而,从器件制造观点来说,可能存在显著差别。根据图12的示例布置的优点可以是可能在几何上将两个组放置得更靠近在一起。另一方面,图13所示的布置中的芯片设计可能更难以实现,因为芯片上的电势取决于两个组位于LED串中的位置而可能是显著的。除了通过将芯片载体Cp焊接到引线框来完成引向管脚1的连接Jc-至Jp-并且因此仅一个键合引线B-出现在LED器件中之外,图14示出与图13所示的相似的根据本发明实施例所配置的LED器件的截面图。进一步的连接并未被示出,但也可以被包括。根据本公开,大量变形将是显而易见的。
假设每组有相同的像素和像素数量,ZES电路拓扑的一些实现示出与LED串的末端(靠近图15中的Str-)相比在LED串的开始(靠近图15中的Str+)处的各像素之间的显著亮度差异。根据本发明的实施例,因为封装内的组的靠近接近,亮度差异在空间上取平均,并且由此导致在观看者的眼中的更一致的亮度印象,所以通过将来自LED串的开始的一个或更多个组与来自LED串的末端的一个或更多个组封装到单个封装中可以显著减轻这种亮度差异。
图16示出布居有其中每一个可以例如根据图8和/或图9实现的器件Pk1至Pk9的印刷电路板(PCB)的顶视图。PCB有效地实现图15所示的电路的Eng部分,并且包括整流器和控制电路的输入部分Inp可以实现在不同的PCB上,其中,两个PCB可以通过三个引线而彼此连接。图12和图13的示例实施例所示的引出管脚(边沿上的管脚的布置和器件的布置以及电功能对于管脚的分配)带来这样的优点:对于实现根据图16的光引擎而言,可以利用单侧PCB,因为可能没有在PCB上实现铜轨迹的无导通交叉的需要。因此,可以在PCB布局中提供铜轨迹的类似蜗牛壳的布置,如图16的示例实施例所示。如参照图16进一步可见那样,铜轨迹被设计为在可见处的Cu以及在隐藏在LED器件之下处的CuH。
根据本公开,所描绘的示例实施例的大量变形将是显而易见的。例如,LED的类型可以随着芯片的不同而不同,尤其是芯片的发射色彩可以变化(例如R/G/B或带绿的白色/红色)。如果波长转换元件给出芯片的最终发射色彩,则可以存在随着芯片和/或像素组和/或像素的不同而不同的转换元件(例如不同的发射色彩)。还应注意,ZES驱动器电路可能恰已经在集成芯片中包括正常地必须作为分立式器件而添加的ESD保护功能。例如,在图6所示的示例实施例中,MOSFET Q的体二极管可以充当ESD保护器件。
根据本公开,大量变形和实施例将是显而易见的。例如,本发明的一个实施例提供:一种半导体器件,包括:芯片载体;发光二极管(LED),形成在所述芯片载体上或键合到所述芯片载体;以及开关,形成于所述芯片载体上或所述芯片载体中,并且操作地跨所述LED而耦接,并且被配置为:响应于控制信号而对通过所述LED的电流进行调节。在一些情况下,所述器件还包括:控制电路,用于提供控制信号,以用于控制所述开关。在一种这样的情况下,所述控制电路包括:感测电路,用于感测流过所述LED的电流。在一些情况下,所述器件还包括:整流器电路,被配置为:接收电压源,并且提供跨所述LED的整流电压。在一些情况下,所述LED被包括在串联连接的LED串中,并且所述开关跨所述串中的多个LED而连接。在一些这样的情况下,所述器件还包括:多个附加开关,每个附加开关跨所述串中的多个LED的不同集合而连接。在一些情况下,所述LED包括:薄膜LED芯片。在一些情况下,所述LED包括:蓝宝石倒装芯片。在一些情况下,所述LED包括:有源层,夹在p型层与n型层之间;以及触点过孔,被配置为:允许n侧触点和p侧触点两者都位于所述有源层的一侧上。在一些情况下,所述器件还包括:镜层,在所述芯片载体与所述LED之间。在一些情况下,所述器件还包括:集成电路封装,其包含包括所述LED和开关的芯片载体。在一些这样的情况下,所述集成电路封装具有三个或更多个引线,并且是小外形晶体管(SOT)封装、表面安装封装(SMP)或径向LED器件封装之一。在其它这样的情况下,所述集成电路封装容纳多个芯片载体,每个芯片载体承载一个或更多个LED并且被配置有一个或更多个开关,用于控制LED电流流动。在其它这样的情况下,所述芯片载体仅是所述集成电路封装中的芯片载体,所述芯片载体包括多个可开关LED电路。在一种这样的情况下,所述可开关LED电路的每一个与p触点引线、n触点引线和控制引线关联。另一示例实施例包括:一种系统,包括如在该段落中的各种限定的所述半导体器件中的两个或更多个,并且被操作地耦接以提供串联连接的LED串。在一个这样的系统中,所述两个或更多个器件布居于印刷电路板上。另一示例实施例提供一种光引擎,其包括所述系统。
本发明另一实施例提供一种半导体器件,包括:芯片载体;以及多个发光二极管(LED),形成在所述芯片载体上或键合到所述芯片载体并且串联连接,其中,所述LED包括夹在p型层与n型层之间的有源层,所述层被横向地构造到串联连接的机械地并且电分离的半导体像素中。所述器件还包括:多个开关,形成在所述芯片载体上或所述芯片载体中,每个开关操作地跨不同的LED子集而耦接,并且被配置为响应于控制信号而对通过所述子集的电流进行调节。所述器件还包括:集成电路封装,其包含包括所述LED和开关的芯片载体。在一些情况下,所述器件还包括以下项中的至少一个:镜层,在所述芯片载体与所述LED中的每一个之间;控制电路,用于提供控制信号,以用于控制所述开关,其中,所述控制电路包括:感测电路,用于感测流过所述LED的电流;和/或整流器电路,被配置为:接收电压源,并且提供跨所述LED的整流电压。在一些情况下,所述LED中的至少一个包括:薄膜LED芯片。在一些情况下,所述LED中的至少一个包括:有源层,夹在p型层与n型层之间;以及触点过孔,被配置为:允许n侧触点和p侧触点两者都位于所述有源层的一侧上。在一些情况下,所述集成电路封装容纳多个芯片载体,每个芯片载体承载一个或更多个LED并且被配置有一个或更多个开关,用于控制LED电流流动。在一些情况下,所述芯片载体仅是在所述集成电路封装中的芯片载体,所述芯片载体包括多个可开关LED电路,并且所述可开关LED电路中的每一个与p触点引线、n触点引线和控制引线关联。
本发明的另一实施例提供一种照明系统,被配置有:集成电路,所述集成电路包括一个或更多个发光二极管(LED)以及开关电路,所述开关电路用于响应于一个或更多个亮度调节控制信号而控制通过所述LED的电流流动,所述系统进一步被配置用于直接耦接到整流电压源。在一些情况下,所述一个或更多个LED包括:薄膜LED芯片,形成在集成电路封装中所容纳的载体芯片上。
已经为了图解和描述的目的而提出本发明实施例的上述描述。并不意图穷举或将本发明限制于所公开的精确形式。根据本公开,很多修改和变化是可能的。意图不由该详细的描述而是由所附的权利要求来限制本发明的范围。
Claims (26)
1. 一种半导体器件,包括:
芯片载体;
发光二极管(LED),形成在所述芯片载体上或键合到所述芯片载体;以及
开关,形成在所述芯片载体上或形成在所述芯片载体中,并且操作地跨所述LED而耦接,并且被配置为:响应于控制信号而对通过所述LED的电流进行调节。
2. 如权利要求1所述的器件,还包括:控制电路,用于提供控制信号,以用于控制所述开关。
3. 如权利要求2所述的器件,其中,所述控制电路包括:感测电路,用于感测流过所述LED的电流。
4. 如权利要求1所述的器件,还包括:整流器电路,被配置为:接收电压源,并且提供跨所述LED的整流电压。
5. 如权利要求1所述的器件,其中,所述LED包括在串联连接的LED串中,并且所述开关跨所述串中的多个LED而连接。
6. 如权利要求5所述的器件,还包括:多个附加开关,每个附加开关跨所述串中的多个LED的不同集合而连接。
7. 如权利要求1所述的器件,其中,所述LED包括:薄膜LED芯片。
8. 如权利要求1所述的器件,其中,所述LED包括:蓝宝石倒装芯片。
9. 如权利要求1所述的器件,其中,所述LED包括:
有源层,夹在p型层与n型层之间;以及
触点过孔,被配置为:允许n侧触点和p侧触点两者都位于所述有源层的一侧上。
10. 如权利要求1所述的器件,还包括:镜层,在所述芯片载体与所述LED之间。
11. 如权利要求1所述的器件,还包括:集成电路封装,其包含包括所述LED和开关的所述芯片载体。
12. 如权利要求11所述的器件,其中,所述集成电路封装具有三个或更多个引线,并且是小外形晶体管(SOT)封装、表面安装封装(SMP)或径向LED器件封装之一。
13. 如权利要求11所述的器件,其中,所述集成电路封装容纳多个芯片载体,每个芯片载体承载一个或更多个LED并且被配置有一个或更多个开关,以用于控制LED电流流动。
14. 如权利要求11所述的器件,其中,所述芯片载体仅是所述集成电路封装中的芯片载体,所述芯片载体包括多个可开关LED电路。
15. 如权利要求14所述的器件,其中,所述可开关LED电路之一与p触点引线、n触点引线和控制引线关联。
16. 一种系统,包括在权利要求1中所限定的半导体器件中的两个或更多个,所述半导体器件中的两个或更多个被操作地耦接以提供串联连接的LED串。
17. 如权利要求16所述的系统,其中,所述两个或更多个器件布居在印刷电路板上。
18. 一种光引擎,包括如权利要求16所述的系统。
19. 一种半导体器件,包括:
芯片载体;
多个发光二极管(LED),形成在所述芯片载体上或键合到所述芯片载体并且被串联连接,其中,所述LED包括夹在p型层与n型层之间的有源层,所述层被横向地构造到串联连接的机械地和电分离的半导体像素中;
多个开关,形成在所述芯片载体上或形成在所述芯片载体中,每个开关操作地跨不同的LED子集而耦接,并且被配置为:响应于控制信号而对通过所述子集的电流进行调节;以及
集成电路封装,其包含包括所述LED和开关的所述芯片载体。
20. 如权利要求19所述的器件,还包括以下中的至少一个:
镜层,在所述芯片载体与所述LED中的每一个之间;
控制电路,用于提供控制信号,以用于控制所述开关,其中,所述控制电路包括:感测电路,用于感测流过所述LED的电流;以及
整流器电路,被配置为:接收电压源,并且提供跨所述LED的整流电压。
21. 如权利要求19所述的器件,其中,所述LED中的至少一个包括薄膜LED芯片。
22. 如权利要求19所述的器件,其中,所述LED中的至少一个包括:
有源层,夹在p型层与n型层之间;以及
触点过孔,被配置为:允许n侧触点和p侧触点这两者都位于所述有源层的一侧上。
23. 如权利要求19所述的器件,其中,所述集成电路封装容纳多个芯片载体,每个芯片载体承载一个或更多个LED并且被配置有一个或更多个开关,以用于控制LED电流流动。
24. 如权利要求19所述的器件,其中,所述芯片载体仅是在所述集成电路封装中的芯片载体,所述芯片载体包括多个可开关LED电路,并且所述可开关LED电路中的每一个与p触点引线、n触点引线和控制引线关联。
25. 一种照明系统,包括:集成电路,所述集成电路包括一个或更多个发光二极管(LED)以及开关电路,所述开关电路用于响应于一个或更多个亮度调节控制信号而控制通过所述LED的电流流动,所述系统进一步被配置用于直接耦接到整流电压源。
26. 如权利要求25所述的系统,其中,所述一个或更多个LED包括:薄膜LED芯片,形成在集成电路封装中所容纳的载体芯片上。
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US201261588838P | 2012-01-20 | 2012-01-20 | |
US61/588838 | 2012-01-20 | ||
PCT/US2013/022390 WO2013110029A1 (en) | 2012-01-20 | 2013-01-21 | Zero energy storage driver integrated in led chip carrier |
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CN104365178B CN104365178B (zh) | 2018-01-12 |
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US (1) | US20150028754A1 (zh) |
EP (1) | EP2903396A1 (zh) |
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WO (1) | WO2013110029A1 (zh) |
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CN109716863A (zh) * | 2016-05-02 | 2019-05-03 | 亮锐有限责任公司 | 具有带分接头的线性驱动器的多焊盘多接点led封装 |
CN109937480A (zh) * | 2016-11-18 | 2019-06-25 | 奥斯兰姆奥普托半导体有限责任公司 | 多像素led部件和用于运行多像素led部件的方法 |
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CN104159372A (zh) * | 2014-08-12 | 2014-11-19 | 无锡中科新能源股份有限公司 | 一种高压led光引擎 |
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US20150028754A1 (en) | 2015-01-29 |
EP2903396A1 (en) | 2015-08-05 |
DE112013000619T5 (de) | 2014-11-06 |
CN104365178B (zh) | 2018-01-12 |
WO2013110029A1 (en) | 2013-07-25 |
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