CN104362172A - Semiconductor chip structure with terminal ring and manufacturing method thereof - Google Patents
Semiconductor chip structure with terminal ring and manufacturing method thereof Download PDFInfo
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- CN104362172A CN104362172A CN201410545270.0A CN201410545270A CN104362172A CN 104362172 A CN104362172 A CN 104362172A CN 201410545270 A CN201410545270 A CN 201410545270A CN 104362172 A CN104362172 A CN 104362172A
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- end ring
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- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229920000642 polymer Polymers 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 9
- -1 polytetrafluoroethylene Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- CMLFRMDBDNHMRA-UHFFFAOYSA-N 2h-1,2-benzoxazine Chemical compound C1=CC=C2C=CNOC2=C1 CMLFRMDBDNHMRA-UHFFFAOYSA-N 0.000 claims description 4
- 239000004952 Polyamide Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920000292 Polyquinoline Polymers 0.000 claims description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229920000090 poly(aryl ether) Polymers 0.000 claims description 4
- 229920002647 polyamide Polymers 0.000 claims description 4
- 229920006260 polyaryletherketone Polymers 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 4
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000006698 induction Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor chip structure with a terminal ring and a manufacturing method thereof. The structure comprises a semiconductor substrate; a first surface of the semiconductor substrate is provided with a main chip region and a terminal ring surrounding the main chip region; the surfaces of the main chip region and terminal ring are provided with polymer protecting layers; the main chip region comprises a well region in the semiconductor substrate and a stacking structure of a metal layer and medium layer between the well region and the surface of the semiconductor substrate; the terminal ring is of a groove formed by etching the stacking structure and the semiconductor substrate, the depth of the groove is larger than the total thickness of the stacking structure and well region, and the side of the well region of the main chip region is exposed by the groove. Since most of the well region material is removed by the groove, the surface conductive electric field of the edge of the main chip region is reduced greatly, and the edge of the main chip region is not prone to breaking through; the width of the terminal ring can be shortened by one third, and the area of the terminal ring is reduced greatly.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of semiconductor chip structure and the manufacture method thereof with end ring.
Background technology
At present in the manufacture process of high-voltage chip, the discrete device of high pressure can stay the terminal protection ring (also claiming buffering ring) of one fixed width around master chip, for withstand voltage and reduction induction field.For the design of the discrete device of middle low-voltage, the area shared by terminal protection ring can not be very large, and the device of parasitism, the reliability affecting master chip that can't be too many.High-pressure separator part high pressure port is drawn usually overleaf, and can produce certain induction field on surface, in order to reduce surface field intensity, requires that the terminal suspending region of non-constant width is to meet direct current and the requirement of withstand voltage exchanged.Its buffering area of the high tension apparatus of 500V has exceeded 120um usually, and the ratio that cushion area accounts for overall chip area is usually very high.
The isolation of terminal protection ring; traditional handicraft adopts field oxide isolation, injects isolation; and Metal field plate or polysilicon field plate isolation; its object be exactly in order to withstand voltage and lower induction field on the impact of device effective coverage; but all can introduce parasitic components, such as, introduce parasitic capacitance and have influence on the AC characteristic of device.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor chip structure and the manufacture method thereof with end ring, can ensure the area reducing end ring under withstand voltage prerequisite, and parasitic capacitance is less.
For solving the problem, the invention provides a kind of semiconductor chip structure with end ring, it is characterized in that, comprise: semiconductor base, described semiconductor base comprises first surface and relative second surface, the first surface of described semiconductor base has master chip district and the end ring around master chip district, described master chip district and end ring surface have polymer protective layer, described master chip district comprises the well region in Semiconductor substrate, be positioned at the interlayer metal layer of well region and semiconductor substrate surface and the stacked structure of dielectric layer, described end ring is to stacked structure, Semiconductor substrate carries out etching the groove formed, the degree of depth of described groove is greater than the gross thickness of stacked structure and well region, and described groove exposes the well region sidewall in described master chip district.
Optionally, described master chip district is discrete device or chip.
Optionally, described polymer protective layer, across above groove, forms air insulated formula groove completely in groove.
Optionally, the dielectric constant of the material of described polymer protective layer is less than or equal to 3.
Optionally, the material of described polymer protective layer is polyamide, polyimides, polytetrafluoroethylene, polyaryl ether, PAEK, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, poly quinoline one wherein.
Optionally, the second surface of described semiconductor base has interconnection metal layer again.
Optionally, the dicing lane of chip is positioned at described groove.
The embodiment of the present invention additionally provides a kind of manufacture method with the semiconductor chip structure of end ring, comprising:
There is provided semiconductor base, the stacked structure that described semiconductor base comprises Semiconductor substrate, is positioned at the well region of Semiconductor substrate, is positioned at the interlayer metal layer of well region and semiconductor substrate surface and dielectric layer, the position that described well region is corresponding is master chip district;
Stacked structure around semiconductor base master chip district is etched, until expose the Semiconductor substrate bottom stacked structure, form groove, the degree of depth of described groove is greater than the gross thickness of stacked structure and well region, and described groove exposes the well region sidewall in described master chip district, described groove is as the end ring in master chip district;
Polymer protective layer is formed at described stacked structure and end ring surface.
Optionally, the technique forming described groove is dry etch process, wet-etching technology or both combinations.
Optionally, also comprise, form interconnection metal layer again at the second surface of described semiconductor base.
Optionally, the dicing lane of chip is positioned at described groove.
Optionally, after forming described groove, before formation polymer protective layer, carry out Passivation Treatment at described trench interiors.
Compared with prior art, the technical program has the following advantages:
Because the present invention is owing to completing after silicon chip postchannel process makes, around master chip district, etching forms groove, does not follow-uply have further process filling dielectric layer or interlayer metal layer, namely using air as the isolation of master chip district and neighboring area.Because groove eliminates most of well region material, significantly reduce the surface induction electric field of master chip area edge, master chip area edge is not easy breakdown, and the width of end ring can be reduced into original more than 1/3, greatly reduces the area of end ring.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the cross-sectional view with the manufacture process of the semiconductor chip structure of end ring of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, clear, complete description is carried out to technical scheme of the present invention.
Please refer to Fig. 5; for the cross-sectional view with the semiconductor chip structure of end ring of first embodiment of the invention; comprise: semiconductor base 10; described semiconductor base 10 comprises first surface 11 and relative second surface 12; the first surface 11 of described semiconductor base 10 has master chip district 13 and the end ring 14 around master chip district I; described master chip district 13 and end ring 14 surface have polymer protective layer 21, and the second surface of described semiconductor base 10 has interconnection metal layer 22 again.
Described semiconductor base 10 comprises Semiconductor substrate 15 and is positioned at the stacked structure 16 on Semiconductor substrate 15 surface, wherein in master chip district 13, well region 17 is formed in described Semiconductor substrate 15, on the surface of described well region 17, there is stacked structure 16, described stacked structure 16 is the stacked structure of dielectric layer 18 and interlayer metal layer 19, in this Fig. 5, illustrate only one deck dielectric layer 18 and from level to level between metal level 19.In other embodiments, described stacked structure can also comprise metal level between multilayer dielectricity layer and multilayer layer and intersect stacking multilayer lamination structure, is connected between multilayer layer between metal level by conductive plunger.
Described Semiconductor substrate is the one wherein such as silicon substrate, germanium substrate, gallium nitride substrate, described dielectric layer is silicon oxide layer or low-K dielectric material layer, described master chip district 13 is discrete device or the chip of high pressure or low pressure, such as power device or high-voltage driving circuit chip etc.
In the present embodiment, the foreign ion doping type of described well region 17 is contrary with the foreign ion doping type of Semiconductor substrate, and when well region is P type trap zone, described Semiconductor substrate is N-type substrate, when well region is N-type well region, described Semiconductor substrate is P type substrate.
Described end ring 14 is carry out etching the groove 20 formed to stacked structure 16, Semiconductor substrate 15, and the degree of depth of described groove 20 is greater than the gross thickness of stacked structure 16 and well region 17, and described groove 20 exposes well region 17 sidewall in described master chip district 13.Sidewall due to described groove 20 exposes well region sidewall and is positioned at the Semiconductor substrate bottom well region, and described end ring 14 still can provide enough withstand voltages.The etching groove degree of depth and width adjust according to different process and the requirement of circuit voltage, the withstand voltage of product, and the degree of depth can from 1 ~ 50um, or darker.Width makes the appropriate adjustments according to the pressure drop difference of groove both sides (near chip side and the side that keeps to the side).
Described groove 20 carries out etching formed stacked structure 16, Semiconductor substrate 15 after formation stacked structure 16.Owing to completing after silicon chip postchannel process makes, directly around master chip district, form groove, follow-uply do not have further process filling dielectric layer or interlayer metal layer, namely using air as the isolation of master chip district and neighboring area.Because air is relative to silicon and the lower relative dielectric constant of silica, be not easy breakdown, the width of end ring can be reduced into original more than 1/3, greatly reduces the area of end ring.
If the technique that etching forms groove is placed on front-end process, groove due to sky likely makes silicon chip produce warpage in the front-end process relating to pyroprocess, affect the processing of silicon chip and the reliability of chip, and also can insert metal, silicon dioxide etc. inside groove in follow-up technique, greatly lower the effect of trench termination.The terminal trenches of this technique is formed after road technique in the completed, on former technique for processing silicon chip without impact, only need add one mask and etching technics after silicon wafer to manufacture completes.
In the present embodiment; in described master chip district 13 and end ring 14 surface, also there is polymer protective layer 21; the first surface of described polymer protective layer 21 pairs of semiconductor bases 10 carries out passivation protection; because the width of described groove 20 diminishes; the polymer protective layer 21 formed by deposit can, across on described groove 20, make described groove form air insulated formula groove completely.If master chip district is high tension apparatus, the width of groove can be wider, and polymer can be partially filled in groove, can improve the withstand voltage of groove further.
In the present embodiment; the dielectric constant of the material of described polymer protective layer 21 is less than or equal to 3; for low-K dielectric material, the such as one wherein such as polyamide, polyimides, polytetrafluoroethylene, polyaryl ether, PAEK, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, poly quinoline.Because the dielectric constant of air is close to 1, the parasitic capacitance utilizing described air insulated formula groove to produce as isolation structure is less, can not affect AC characteristic.Even if polymer can be partially filled into groove, because the dielectric constant of described polymer is lower, compared with prior art, also parasitic capacitance can be reduced.
In the present embodiment, the second surface of described semiconductor base 10 is also formed with interconnection metal layer 22 again, and described interconnection metal layer again 22 is as the voltage leading-out ends of the Semiconductor substrate in master chip district.
In other embodiments, the voltage leading-out ends in described master chip district can also be positioned on the first surface of semiconductor base.
In other embodiments, please refer to Fig. 4, the dicing lane 30 of chip is positioned at described groove 20.When although the dicing lane 30 of chip is positioned at described groove 20, the width of groove can become large, but follow-up scribing cutting is carried out to chip after, resin is utilized to wrap the sidewall of chip, namely the well region utilizing resin to wrap groove to expose, the sidewall of stacked structure, can eliminate the impact of electric field on chip internal at chip edge place completely.
The embodiment of the present invention additionally provides a kind of manufacture method with the semiconductor chip structure of end ring, comprising:
Step S101, semiconductor base is provided, the stacked structure that described semiconductor base comprises Semiconductor substrate, is positioned at the well region of Semiconductor substrate, is positioned at the interlayer metal layer of well region and semiconductor substrate surface and dielectric layer, the position that described well region is corresponding is master chip district;
Step S102, forms interconnection metal layer again at the second surface of described semiconductor base;
Step S103, stacked structure around semiconductor base master chip district is etched, until expose the Semiconductor substrate bottom stacked structure, form groove, the degree of depth of described groove is greater than the gross thickness of stacked structure and well region, and described groove exposes the well region sidewall in described master chip district, described groove is as the end ring in master chip district;
Step S104, forms polymer protective layer at described stacked structure and end ring surface.
Concrete, please refer to Fig. 1, semiconductor base 10 is provided, described semiconductor base 10 comprises Semiconductor substrate 15, is positioned at the well region 17 of Semiconductor substrate, is positioned at the interlayer metal layer 19 on well region 17 and Semiconductor substrate 15 surface and the stacked structure 16 of dielectric layer 18, and the position of described well region 17 correspondence is master chip district 13.Described well region is contrary with the Doped ions type of Semiconductor substrate.Due to discrete device or chip that described master chip district 13 is high pressure or low pressure, those skilled in the art can select suitable technique to be formed as required, do not describe in detail at this.
Please refer to Fig. 2, form interconnection metal layer 22 at the second surface 12 of described semiconductor base 10 again, described interconnection metal layer again 22 is as the voltage leading-out ends of the Semiconductor substrate in master chip district.In other embodiments, the voltage leading-out ends in described master chip district can also be positioned on the first surface of semiconductor base, does not need to form interconnection metal layer again at the second surface of described semiconductor base.
Please refer to Fig. 3, stacked structure 16 around semiconductor base 10 master chip district 13 is etched, until expose the Semiconductor substrate 15 bottom stacked structure 16, form groove 20, the degree of depth of described groove 20 is greater than the gross thickness of stacked structure 16 and well region 17, and described groove 20 exposes well region 17 sidewall in described master chip district 13, described groove 20 is as the end ring 14 around master chip district 13.
In the present embodiment, described etching technics is dry etch process, wet-etching technology or both combinations.In the present embodiment, by first carrying out wet-etching technology, then carry out dry etch process, because the degree of depth of described groove is very large, width is also comparatively large, can save etch period and etching cost on the one hand, also can realize satisfied sidewall profile on the other hand.
In other embodiments, after completing etching technics, Passivation Treatment can also be carried out to described groove, the defects count of trenched side-wall and bottom can be reduced.
In other embodiments, please refer to Fig. 4, the dicing lane 30 of chip is positioned at described groove 20.When although the dicing lane 30 of chip is positioned at described groove 20, the width of groove can become large, but follow-up scribing cutting is carried out to chip after, resin is utilized to wrap the sidewall of chip, namely the well region utilizing resin to wrap groove to expose, the sidewall of stacked structure, can eliminate the impact of electric field on chip internal at chip edge place completely.
Please refer to Fig. 5, form polymer protective layer at described stacked structure 16 and end ring 14 surface.
The dielectric constant of the material of described polymer protective layer 21 is less than or equal to 3; for low-K dielectric material, the such as one wherein such as polyamide, polyimides, polytetrafluoroethylene, polyaryl ether, PAEK, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, poly quinoline.Because the dielectric constant of air is close to 1, the parasitic capacitance utilizing described air insulated formula groove to produce as isolation structure is less, can not affect AC characteristic.Even if polymer can be partially filled into groove, because the dielectric constant of described polymer is lower, compared with prior art, also parasitic capacitance can be reduced.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. one kind has the semiconductor chip structure of end ring, it is characterized in that, comprise: semiconductor base, described semiconductor base comprises first surface and relative second surface, the first surface of described semiconductor base has master chip district and the end ring around master chip district, described master chip district and end ring surface have polymer protective layer, described master chip district comprises the well region in Semiconductor substrate, be positioned at the interlayer metal layer of well region and semiconductor substrate surface and the stacked structure of dielectric layer, described end ring is to stacked structure, Semiconductor substrate carries out etching the groove formed, the degree of depth of described groove is greater than the gross thickness of stacked structure and well region, and described groove exposes the well region sidewall in described master chip district.
2. have the semiconductor chip structure of end ring as claimed in claim 1, it is characterized in that, described master chip district is discrete device or chip.
3. have the semiconductor chip structure of end ring as claimed in claim 1, it is characterized in that, described polymer protective layer, across above groove, forms air insulated formula groove completely in groove.
4. have the semiconductor chip structure of end ring as claimed in claim 3, it is characterized in that, the dielectric constant of the material of described polymer protective layer is less than or equal to 3.
5. there is the semiconductor chip structure of end ring as claimed in claim 1; it is characterized in that, the material of described polymer protective layer is polyamide, polyimides, polytetrafluoroethylene, polyaryl ether, PAEK, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, poly quinoline one wherein.
6. have the semiconductor chip structure of end ring as claimed in claim 1, it is characterized in that, the second surface of described semiconductor base has interconnection metal layer again.
7. have the semiconductor chip structure of end ring as claimed in claim 1, it is characterized in that, the dicing lane of chip is positioned at described groove.
8. there is a manufacture method for the semiconductor chip structure of end ring, it is characterized in that, comprising:
There is provided semiconductor base, the stacked structure that described semiconductor base comprises Semiconductor substrate, is positioned at the well region of Semiconductor substrate, is positioned at the interlayer metal layer of well region and semiconductor substrate surface and dielectric layer, the position that described well region is corresponding is master chip district;
Stacked structure around semiconductor base master chip district is etched, until expose the Semiconductor substrate bottom stacked structure, form groove, the degree of depth of described groove is greater than the gross thickness of stacked structure and well region, and described groove exposes the well region sidewall in described master chip district, described groove is as the end ring in master chip district;
Polymer protective layer is formed at described stacked structure and end ring surface.
9. have the manufacture method of the semiconductor chip structure of end ring as claimed in claim 8, it is characterized in that, the technique forming described groove is dry etch process, wet-etching technology or both combinations.
10. there is the manufacture method of the semiconductor chip structure of end ring as claimed in claim 8, it is characterized in that, also comprise, form interconnection metal layer again at the second surface of described semiconductor base.
11. manufacture methods as claimed in claim 8 with the semiconductor chip structure of end ring, it is characterized in that, the dicing lane of chip is positioned at described groove.
12. manufacture methods as claimed in claim 8 with the semiconductor chip structure of end ring, is characterized in that, after forming described groove, before formation polymer protective layer, carry out Passivation Treatment at described trench interiors.
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| CN201410545270.0A CN104362172B (en) | 2014-10-15 | 2014-10-15 | Semiconductor chip structure with end ring and its manufacturing method |
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| CN201410545270.0A CN104362172B (en) | 2014-10-15 | 2014-10-15 | Semiconductor chip structure with end ring and its manufacturing method |
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| CN104362172B CN104362172B (en) | 2018-09-11 |
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Cited By (4)
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| CN110690202A (en) * | 2019-10-09 | 2020-01-14 | 长江存储科技有限责任公司 | Integrated circuit device and method of making the same |
| CN112201685A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and dielectric combined terminal |
| CN113437136A (en) * | 2021-06-28 | 2021-09-24 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN114005733A (en) * | 2021-10-19 | 2022-02-01 | 深圳辰达行电子有限公司 | Method for manufacturing vehicle-gauge-level rectification chip |
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| CN112201685B (en) * | 2020-09-08 | 2022-02-11 | 浙江大学 | Super junction device and dielectric combined terminal |
| CN113437136A (en) * | 2021-06-28 | 2021-09-24 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN114005733A (en) * | 2021-10-19 | 2022-02-01 | 深圳辰达行电子有限公司 | Method for manufacturing vehicle-gauge-level rectification chip |
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