CN104362161B - A kind of imageing sensor preparation technology - Google Patents
A kind of imageing sensor preparation technology Download PDFInfo
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- CN104362161B CN104362161B CN201410524224.2A CN201410524224A CN104362161B CN 104362161 B CN104362161 B CN 104362161B CN 201410524224 A CN201410524224 A CN 201410524224A CN 104362161 B CN104362161 B CN 104362161B
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- 238000005516 engineering process Methods 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000000227 grinding Methods 0.000 description 15
- 230000008901 benefit Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
The present invention relates to semiconductor applications, and in particular to a kind of imageing sensor preparation technology, comprise the following steps：Step S1, offer semiconductor structure, groove is provided with the top of the semiconductor structure, form leaded in the groove, the semiconductor structure top and the exposed surface of the groove are coated with and one layer of barrier layer are coated with the first dielectric layer at the top of the first dielectric layer, and the semiconductor structure；Step S2：Depositing second dielectric layer is covered in the surface on the barrier layer and the lead and is filled the groove；Step S3：Planarization process is carried out to second dielectric layer, the top surface of second dielectric layer is flushed with the top surface on the barrier layer, the surface smoothness after the planarized treatment of the second dielectric layer is improved by the barrier layer.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of imageing sensor preparation technology.
Background technology
Cmos image sensor belongs to photoelectric component, and cmos image sensor is due to its manufacturing process and existing integrated electricity
Road manufacturing process is compatible, while its performance has many good qualities than original charge-coupled image sensor (CCD) imageing sensor, and gradually
Main flow as imageing sensor.Cmos image sensor can integrate drive circuit and pixel, simplify hardware
Design, while also reducing the power consumption of system.Cmos image sensor while optical signal is gathered due to can just take out electricity
Signal, moreover it is possible to which real time processed images information, speed is faster than ccd image sensor, while cmos image sensor also has price
Cheaply, bandwidth is larger, blur prevention, the advantage of the flexibility of access and larger fill factor and obtained it is substantial amounts of use, extensively
It is general to be applied in the multiple products such as industry automatic control and consumer electronics, such as monitor, video communication, toy etc..In view of CMOS
The plurality of advantages of imageing sensor, the research and development of present CIS be to be realized using the advantage of its system integration it is multi-functional
And intellectuality；There is the flexible advantage of access using it, can be realized by only reading zonule interested on photosurface
Frame rate CMOS high；While cmos image sensor wide dynamic range, high-resolution and low noise audio technology are also evolving.
The preparation part preparation flow of imageing sensor can refer to shown in Fig. 1 a~1b in the prior art, one is provided first and is wrapped
The semiconductor structure of the first wafer 1 and the second wafer 2 is included, the first wafer includes substrate 1a and oxide layer 1b, and same second is brilliant
Circle 2 includes substrate 2a and oxide layer 2b；Additionally, being additionally provided with a groove at the top of the second wafer 2, one is provided with the trench
Electrode 4, the first dielectric layer 3 is all covered with the top of substrate 2a with the exposed surface of groove, and structure is as shown in Figure 1；Deposit afterwards
One layer thicker of the second dielectric layer 5 is covered on the first dielectric layer 3 and is filled the remaining part of groove, such as Fig. 2 institutes
Show, planarization process is carried out to the second dielectric layer 5 afterwards.But those skilled in the art have found, are carried out to the second dielectric layer 5
After planarization process, remaining second dielectric layer 5 is very big in the thickness difference opposite sex of various location.This is to deposit the second dielectric
During layer 5, the dielectric layer at the top of groove can accordingly form fluted, therefore when being ground, the second dielectric near groove
In general 5 grinding rate of layer can be more than the grinding rate at other positions, and then be easy to produce butterfly defect (Dishing)
6.This is that those skilled in the art do not expect to see.
The content of the invention
The present invention provides a kind of preparation method of imageing sensor according to the deficiencies in the prior art, comprises the following steps：
Step S1, offer semiconductor structure, are provided with groove at the top of the semiconductor structure, formed in the groove
Leaded, the semiconductor structure top and the exposed surface of the groove are coated with the first dielectric layer, and second wafer
One layer of barrier layer is also covered with first dielectric layer at top；
Step S2：Depositing second dielectric layer is covered in the surface on the barrier layer and the lead and carries out the groove
Filling；
Step S3：Planarization process is carried out to second dielectric layer, makes the top surface of second dielectric layer and the resistance
The top surface of barrier is flushed, and the surface smoothness after the planarized treatment of the second dielectric layer is improved by the barrier layer.
Above-mentioned preparation technology, wherein, the semiconductor structure includes one first wafer and is bonded on the first wafer
The second wafer；
First wafer and second wafer include a substrate and an oxide layer, and first wafer and described
The contact surface of the oxide layer that the second wafer each includes is bonding face.
Above-mentioned preparation technology, wherein, it is all provided with the oxide layer that first wafer and second wafer each include
The first metal layer being equipped with an at least the first metal layer, and first wafer and second wafer is one-to-onely upper and lower
Overlap and contact.
Above-mentioned preparation technology, wherein, it is additionally provided with the second metal in a predetermined depth in the substrate of second wafer
Layer, and the second metal layer and the wire contacts.
Above-mentioned preparation technology, wherein, the lead is T-shaped metal, and lead top offers a groove.
Above-mentioned preparation technology, wherein, after deposition second dielectric layer and before treatment is ground, also include
One technique for anti-carving erosion, to reduce the thickness of second dielectric layer, and the second dielectric layer surface above groove forms convex
Shape structure.
Above-mentioned preparation technology, wherein, the barrier layer is silicon nitride.
Above-mentioned preparation technology, wherein, second dielectric layer is silica.
Above-mentioned preparation technology, wherein, it is additionally provided with an intermediate layer between the barrier layer and first dielectric layer.
Above-mentioned preparation technology, wherein, the intermediate layer is identical with the material of second dielectric layer.
Present invention introduces barrier layer in CMP or " CMP+ anti-carves erosion " technique, using between barrier layer and film to be removed
Grinding selectivity ratio difference high, carry out the accurate terminal for controlling flatening process, uniformity of film and reduces cost are improved, so as to transport
For mass producing.
Brief description of the drawings
By the detailed description made to non-limiting example with reference to the following drawings of reading, the present invention and its feature, outward
Shape and advantage will become more apparent upon.Identical mark indicates identical part in whole accompanying drawings.Not deliberately proportionally
Draw accompanying drawing, it is preferred that emphasis is purport of the invention is shown.
Fig. 1 a~1d is some processes flow chart for preparing imageing sensor in the prior art.
Fig. 2 a are the semiconductor structure schematic diagram that surface provided by the present invention has barrier layer；
Fig. 2 b are the schematic diagram after depositing second dielectric layer of the present invention；
Fig. 2 c (1) and Fig. 2 c (2) for the present invention anti-carve latter two implementation illustration of etching technique；
Fig. 2 d are the schematic diagram after the present invention is ground treatment.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions,
The present invention can also have other embodiment.
It is specific as follows the invention provides a kind of imageing sensor preparation technology.
Step S1：Semiconductor structure 100 is provided first, and it is used to prepare cmos image sensor.Can refer to Fig. 2 a institutes
Show, the top of the semiconductor structure 100 is provided with groove, form leaded 14 in the trench, the top of semiconductor structure 100 and ditch
The exposed surface of groove is coated with the first dielectric layer 13, and first dielectric layer 13 will also be located in the lead 14 and half on channel bottom
Conductor structure 100 is spaced apart, and a fixed gap is remained between the both sides of lead 14 and trenched side-wall.
One layer of barrier layer 17 is also covered with the first dielectric layer at the top of second wafer.As option, the barrier layer
17 can select the stronger silicon nitride layer of compactness.
One it is exemplary but be not intended as limitation embodiment in, the above-mentioned dielectric layer 13 of barrier layer 17 and first it
Between, it is additionally provided with an intermediate layer 16, it is preferred that the material in the intermediate layer 16 and the follow-up material phase of the second dielectric layer 18 for preparing
Together.
Semiconductor structure 100 is described below：With continued reference to Fig. 2 a, the semiconductor structure 100 includes the first wafer
10 and second wafer 11.First wafer 10 includes the substrate 10a and oxide layer 10b on substrate 10a；Second wafer 11 includes
The substrate 11a and oxide layer 11b below substrate 11a.In each self-contained oxidation of the first wafer 10 and the institute of the second wafer 11
The metal level that layer is provided with an at least the first metal layer, and the first wafer 10 and the second wafer 11 is weighed up and down one-to-onely
Fold and contact.The first metal layer 10c is provided with oxide layer 10b, the first metal layer 11c is provided with oxide layer 11b, the
One metal level 10c and the first metal layer 11c forms contact.Meanwhile, in a predetermined depth in the substrate 11a of the second wafer 11 also
Second metal layer 15 is provided with, the top surface of the second metal layer 15 is located at below the upper surface of substrate 11a, and is connect with lead 14
Touch, for the extraction of electrode.The top of second wafer 11 is provided with an at least groove, electrode 14, electrode are formed with the trench
14 bottom forms with second metal layer 15 and contacts.
Said structure is formed using prepared by the usual process meanses in this area, therefore not detailed is in the present invention chatted
State, but this has no effect on protection scope of the present invention.
Step S2：Depositing second dielectric layer 18 is covered in the surface on barrier layer 17 and lead 14 and is filled groove,
As shown in Figure 2 b.
Used as option, second dielectric layer 17 is silicon oxide film, and its thickness first dielectric layer 13 that compares is thick very
It is many.After depositing second dielectric layer 17 is completed, due to the presence of the second wafer groove, therefore cause the second dielectric layer 17 of deposition
Position at the top of groove is formed with depression 30.
One as exemplary but simultaneously in embodiment without limiting, after depositing second dielectric layer 17 and carry out it is next
Before the planarization process of step, also including the technique for anti-carving erosion, to reduce the thickness of the second dielectric layer 18, and above groove
The second dielectric layer 18 surface formed convex architecture 20, reduced using the convex architecture 20 and subsequently the second dielectric layer 18 entered
During row planarization process, due at groove grinding rate it is larger so as to the flatness of the second dielectric layer 18 compared with the unfavorable shadow for causing
Ring.Wherein, this anti-carves etching technique including photoetching and dry etch process, i.e., first with optical graving it is standby go out the light with patterns of openings
Photoresist, is afterwards that etching grinding etching removes the second dielectric layer 18 below being open with photoresist, to form convex architecture.Enter one
Step is optional, and the convex architecture of formation can have variform, for example in one embodiment, the second dielectric layer 18 be anti-carved
After erosion, the surface of the second dielectric layer 18 above groove forms some convex architectures 20, can refer to shown in Fig. 2 c (1)；Another
In one embodiment, then the surface of the second dielectric layer 18 above groove forms holistic convex architecture 20, can refer to Fig. 2 c
(2) shown in.It will be appreciated by those skilled in the art that the above-mentioned convex architecture 20 that includes does not constitute limitation of the invention, at it
Can also possess other shapes in his some embodiments, it is only necessary to ensure at the top of groove or near top position at formed projection knot
Structure.
Step S3：Planarization process is carried out to the second dielectric layer 18, makes the top surface of the second dielectric layer 18 and barrier layer 17
Top surface is flushed, and the surface smoothness after the planarized treatment of the second dielectric layer 18 is improved by the barrier effect on barrier layer 17.
Treatment is ground to the second dielectric layer 18, the top surface of the second dielectric layer 18 is flushed with the top surface of barrier layer 17, by
Barrier layer 17 come improve grinding after the second dielectric layer 18 surface smoothness.
As option, CMP (Chemical Mechanical Polishing), cmp can be used) come right
Second dielectric layer 18 carries out planarization process, and using barrier layer 17 as grinding terminal.In the conventional technology, because second is situated between
Electric layer 17 can be formed with depression 20 at the top of groove, therefore the grinding rate at the position can be caused to compare at other positions
Grinding rate is larger, it is easy to produced the phenomenon of grinding, forms the situation shown in Fig. 1 d.And the present invention is in the second dielectric layer 18
Lower section prepares a barrier layer 17, in continuous process of lapping, because the grinding rate on barrier layer 17 compares the second dielectric layer
18 grinding rate is smaller, can be at the position being ground at the top of groove after, play a part of a buffering, it is to avoid groove top
The neighbouring grinding rate of the second dielectric layer 18 is excessive so as to form butterfly defect, after effective improvement the second dielectric layer 18 grinds
Surface smoothness.Meanwhile, can also be further functioned as in the convex architecture for being formed before improves the table after the second dielectric layer 18 grinds
The effect of surface evenness.
Enter row metal isolated gate afterwards, lead PAD etchings and colored filter such as insert at the subsequent technique, refuse herein
Repeat.
In sum, the present invention discloses a kind of technique of new filling type colored filter combined leads, can answer extensively
For field of semiconductor devices such as imageing sensors (preceding illuminated, back-illuminated type, stacking-type), in the dielectric to wire lead slot position is filled
Before layer carries out planarization process, one layer of barrier layer is first prepared, nationality is avoided by the barrier layer because dielectric layer is in groove
Grinding rate is excessive, and then the butterfly groove for occurring.Process variations of the present invention are small, and cost of implementation is relatively low, and can be effectively improved Jie
The flatness on the surface after electric layer grinding, for the image quality for lifting imageing sensor provides guarantee.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (10)
1. a kind of imageing sensor preparation technology, it is characterised in that comprise the following steps：
Step S1, offer semiconductor structure, are provided with groove at the top of the semiconductor structure, be formed with the groove and drawn
Line, the semiconductor structure top and the exposed surface of the groove are coated with the first dielectric layer, and the semiconductor structure top
One layer of barrier layer is coated with first dielectric layer in portion；
Step S2：Depositing second dielectric layer is covered in the surface on the barrier layer and the lead and is filled out the groove
Fill；
Step S3：Planarization process is carried out to second dielectric layer, makes the top surface of second dielectric layer and the barrier layer
Top surface flush, the surface smoothness after the planarized treatment of the second dielectric layer is improved by the barrier layer.
2. preparation technology as claimed in claim 1, it is characterised in that the semiconductor structure includes one first wafer and bonding
The second wafer on the first wafer；
First wafer and second wafer include a substrate and an oxide layer, and first wafer and described second
The contact surface of the oxide layer that wafer each includes is bonding face.
3. preparation technology as claimed in claim 2, it is characterised in that first wafer and second wafer each include
Oxide layer in be provided with the first metal layer in an at least the first metal layer, and first wafer and second wafer
Overlap up and down one-to-onely and contact.
4. preparation technology as claimed in claim 2, it is characterised in that in the substrate of second wafer in a predetermined depth also
It is provided with second metal layer, and the second metal layer and the wire contacts.
5. preparation technology as claimed in claim 1, it is characterised in that the lead is T-shaped metal, and lead top opens up
There is a groove.
6. preparation technology as claimed in claim 1, it is characterised in that after deposition second dielectric layer and be ground
Before treatment, also including the technique for anti-carving erosion, to reduce the thickness of second dielectric layer, and second Jie above groove
Electric layer surface forms convex architecture.
7. preparation technology as claimed in claim 1, it is characterised in that the barrier layer is silicon nitride.
8. preparation technology as claimed in claim 1, it is characterised in that second dielectric layer is silica.
9. preparation technology as claimed in claim 1, it is characterised in that also set between the barrier layer and first dielectric layer
It is equipped with an intermediate layer.
10. preparation technology as claimed in claim 9, it is characterised in that the material of the intermediate layer and second dielectric layer
It is identical.
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| CN201410524224.2A CN104362161B (en) | 2014-09-30 | 2014-09-30 | A kind of imageing sensor preparation technology |
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| CN104362161B true CN104362161B (en) | 2017-05-31 |
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| CN104867865B (en) * | 2015-03-31 | 2018-08-03 | 武汉新芯集成电路制造有限公司 | A kind of wafer three-dimensional integration lead technique |
| US9536810B1 (en) * | 2015-06-12 | 2017-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes |
| US10017377B2 (en) * | 2016-06-29 | 2018-07-10 | Robert Bosch Gmbh | Protective coating on trench features of a wafer and method of fabrication thereof |
| CN108281437B (en) * | 2018-01-18 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The backside structure and preparation method of back side illumination image sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN102148181A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
| CN103022062A (en) * | 2011-07-19 | 2013-04-03 | 索尼公司 | Solid-state imaging device and semiconductor device, manufacturing method of solid-state imaging device and semiconductor device, and electronic device |
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| US7029591B2 (en) * | 2003-04-23 | 2006-04-18 | Lsi Logic Corporation | Planarization with reduced dishing |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN102148181A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
| CN103022062A (en) * | 2011-07-19 | 2013-04-03 | 索尼公司 | Solid-state imaging device and semiconductor device, manufacturing method of solid-state imaging device and semiconductor device, and electronic device |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |