CN104348467B - A kind of output time holding circuit and method - Google Patents
A kind of output time holding circuit and method Download PDFInfo
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- CN104348467B CN104348467B CN201310317197.7A CN201310317197A CN104348467B CN 104348467 B CN104348467 B CN 104348467B CN 201310317197 A CN201310317197 A CN 201310317197A CN 104348467 B CN104348467 B CN 104348467B
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Abstract
The invention provides a kind of output time holding circuit and method, wherein, described device includes：Voltage comparison unit, for compared with preset reference voltage, operating voltage to be obtained at least two comparative result signals；Enabling unit, for producing at least two enable signals according at least two comparative results signal；Clock driver cell, for receiving reference clock；And the chain of inverters of at least two-way different length is respectively adopted according at least two enable signal, the reference clock is adjusted to the correspondingly sized work clock of at least two-way.The present invention can be such that the delay of work clock maintains in a relatively stable scope, so cause output data retention time be also metastable, facilitate output data to be sampled, and do not increase output data transmission delay.
Description
Technical field
The present invention relates to electronic circuit technology field, more particularly to a kind of output time holding circuit and it is a kind of export when
Between keeping method.
Background technology
The output data retention time is an important parameter for weighing output design, using the output number of prior art design
According to circuit, the delay of circuit is had a great influence by operating voltage change, and with the change of operating voltage, the work speed of circuit
Degree also has a large-scale variation, and the variation of operating rate can expand the excursion of output data retention time window, and one
The denier output data retention time mobility scale of window is excessive, will cause the increase of output data sampling difficulty.Therefore, in order to
Enough facilitate the sampling of output data, it is necessary to maintaining the retention time of output data in a less scope, and together
When do not interfere with data output speed so as in a disguised form increase output data transmission delay.
Therefore, one of the problem of those skilled in the art are in the urgent need to address is, proposes that a kind of output time keeps electricity
Road so that the delay of work clock is maintained in a relatively stable scope, and then causes the retention time of output data
It is metastable, facilitates output data to be sampled, and does not increase output data transmission delay.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of output time holding circuit and a kind of output time is kept
Method, to cause the delay of work clock to maintain in a relatively stable scope, and then cause the holding of output data
Time is also metastable, facilitates output data to be sampled, and does not increase data transfer delay.
In order to solve the above problems, the invention discloses a kind of output time holding circuit, including：
Voltage comparison unit, compare for operating voltage compared with preset reference voltage, to be obtained at least two
Consequential signal；
Enabling unit, for producing at least two enable signals according at least two comparative results signal；
Clock driver cell, for receiving reference clock；And according at least two enable signal be respectively adopted to
The chain of inverters of few two-way different length, the correspondingly sized work clock of at least two-way is adjusted to by the reference clock.
Preferably, at least two comparative results signal include the first comparative result signal, the second comparative result signal,
3rd comparative result signal, wherein, the first comparative result signal is to enter operating voltage and preset minimum reference voltage
Row relatively obtains；The second comparative result signal is to obtain operating voltage compared with preset intermediate reference voltage；
The 3rd comparative result signal is to obtain operating voltage compared with preset highest reference voltage.
Preferably, the voltage comparison unit includes first voltage comparator, second voltage comparator and tertiary voltage
Comparator, the first voltage comparator, second voltage comparator and tertiary voltage comparator positive input terminal connection work electricity
Pressure；The negative input end of the first voltage comparator connects minimum reference voltage, the negative input end of the second voltage comparator
Connect intermediate reference voltage, the negative input end connection highest reference voltage of the tertiary voltage comparator；The first voltage ratio
Compared with device the first comparative result signal is exported according to the minimum reference voltage from output end；The second voltage comparator is according to institute
State intermediate reference voltage and export the second comparative result signal from output end；The tertiary voltage comparator refers to according to the highest
Voltage exports the 3rd comparative result signal from output end, and the voltage comparison unit includes：
When operating voltage is less than the minimum reference voltage, the first comparative result signal is 0, the second comparative result
Signal is 0, and the 3rd comparative result signal is 0；
When operating voltage is more than the minimum reference voltage, during less than the intermediate reference voltage, described first compares knot
Fruit signal is 1, and the second comparative result signal is 0, and the 3rd comparative result signal is 0；
When operating voltage is more than the intermediate reference voltage, during less than the highest reference voltage, described first compares knot
Fruit signal is 1, and the second comparative result signal is 1, and the 3rd comparative result signal is 0；
When operating voltage is more than the highest reference voltage, the first comparative result signal is 1, the second comparative result
Signal is 1, and the 3rd comparative result signal is 1.
Preferably, at least two enable signal includes the first enable signal, the second enable signal, the 3rd enabled letter
Number, the 4th enable signal；The enabling unit includes the first phase inverter, the second phase inverter, the 3rd phase inverter, first and logic basis
Part, second and logic element, the 3rd and logic element and the 4th and logic element, the connection first of the first comparative result signal are anti-
The input of phase device, second are with the first input end of logic element, the 3rd with the first input end of logic element and the 4th with patrolling
The first input end of volume element, the second comparative result signal connect the input of the second phase inverter, the 3rd and the of logic element
Two inputs and the 4th with the second input of logic element, the 3rd comparative result signal connect the 3rd phase inverter input and
4th with the 3rd input of logic element；The enabling unit includes：
When the first comparative result signal is 0, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The first enable signal that output end output from described first and logic element is 1；
When the first comparative result signal is 1, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The second enable signal that output end output from described second and logic element is 1；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 0,
The 3rd enable signal that output end output from the described 3rd and logic element is 1；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 1,
The 4th enable signal that output end output from the described 4th and logic element is 1.
Preferably, at least two-way work clock includes the first work clock, the second work clock, the 3rd work clock
And the 4th work clock；First work clock is according to the first enable signal, using described in the adjustment of the first chain of inverters
Reference clock is formed；Second work clock is according to the second enable signal, and the benchmark is adjusted using the second chain of inverters
Clock is formed；3rd work clock is according to the 3rd enable signal, and the reference clock is adjusted using the 3rd chain of inverters
Formed；4th work clock is according to the 4th enable signal, adjusts the reference clock using the 4th chain of inverters and is formed；
Wherein, first chain of inverters is most short chain of inverters, and second chain of inverters is for described most short anti-
The chain of inverters that phase device chain increase first-level buffer device is formed, the 3rd chain of inverters are to increase for the most short chain of inverters
The chain of inverters for adding two-stage buffer to be formed, the 4th chain of inverters are to increase three-level for the most short chain of inverters to delay
Rush the chain of inverters that device is formed.
Preferably, the clock driver cell includes the first buffer, the second buffer, the 3rd buffer, the 4th buffering
Device, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the first multiplier, the second multiplication
Device, the 3rd multiplier and the 4th multiplier, wherein, first multiplier, the second multiplier, the 3rd multiplier and the 4th
The output end of multiplier is connected to the 9th inverter input；
The input of first buffer receives reference clock；The output end of first buffer connects the first multiplication
The input of the first input end of device and the second buffer；The output end of second buffer connects the first of the second multiplier
The input of input and the 3rd buffer；The output end of 3rd buffer connect the 3rd multiplier first input end and
The input of 4th buffer；The output end of 4th buffer connects the first input end of the 4th multiplier；
First enable signal connects the second input of the first multiplier, and first enable signal also passes through the 5th
Phase inverter connects the 3rd input of the first multiplier；Second enable signal connects the second input of the second multiplier,
Second enable signal also connects the 3rd input of the second multiplier by hex inverter；3rd enable signal connects
The second input of the 3rd multiplier is connect, the 3rd enable signal also connects the 3rd of the 3rd multiplier the by the 7th phase inverter
Input；4th enable signal connects the second input of the 4th multiplier, and the 4th enable signal also passes through the 8th
Phase inverter connects the 3rd input of the 4th multiplier；The clock driver cell includes：
When first enable signal is 1, the first multiplier conducting, the reference clock passes through the first buffer
The first work clock is exported from the output end of the 9th phase inverter；
When second enable signal is 1, the second multiplier conducting, the reference clock is by the first buffering
Device, the second buffer export the second work clock from the output end of the 9th phase inverter；
When the 3rd enable signal is 1, the 3rd multiplier conducting, the reference clock is by the first buffering
Device, the second buffer, the 3rd buffer export the 3rd work clock from the output end of the 9th phase inverter；
When the 4th enable signal is 1, the 4th multiplier conducting, the reference clock is by the first buffering
Device, the second buffer, the 3rd buffer, the 4th buffer export the 4th work clock from the output end of the 9th phase inverter.
Preferably, the output time holding circuit is used in chip.
The embodiment of the present invention additionally provides a kind of method that output time is kept, including：
By operating voltage compared with preset reference voltage, at least two comparative result signals are obtained；
At least two enable signals are produced according at least two comparative results signal；
Receive reference clock；And at least two-way different length is respectively adopted according at least two enable signal
Chain of inverters, the reference clock is adjusted to the correspondingly sized work clock of at least two-way.
Preferably, at least two-way work clock includes the first work clock, the second work clock, the 3rd work clock
And the 4th work clock；First work clock is according to the first enable signal, using described in the adjustment of the first chain of inverters
Reference clock is formed；Second work clock is according to the second enable signal, and the benchmark is adjusted using the second chain of inverters
Clock is formed；3rd work clock is according to the 3rd enable signal, and the reference clock is adjusted using the 3rd chain of inverters
Formed；4th work clock is according to the 4th enable signal, adjusts the reference clock using the 4th chain of inverters and is formed；
Wherein, first chain of inverters is most short chain of inverters, and second chain of inverters is for described most short anti-
The chain of inverters that phase device chain increase first-level buffer device is formed, the 3rd chain of inverters are to increase for the most short chain of inverters
The chain of inverters for adding two-stage buffer to be formed, the 4th chain of inverters are to increase three-level for the most short chain of inverters to delay
Rush the chain of inverters that device is formed.
Preferably, at least two enable signal is used to drive clock driver cell, and the clock driver cell includes
First buffer, the second buffer, the 3rd buffer, the 4th buffer, the 5th phase inverter, hex inverter, the 7th phase inverter,
8th phase inverter, the 9th phase inverter, the first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier, wherein, institute
The output end for stating the first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier is connected to the input of the 9th phase inverter
End；
The input of first buffer receives reference clock；The output end of first buffer connects the first multiplication
The input of the first input end of device and the second buffer；The output end of second buffer connects the first of the second multiplier
The input of input and the 3rd buffer；The output end of 3rd buffer connect the 3rd multiplier first input end and
The input of 4th buffer；The output end of 4th buffer connects the first input end of the 4th multiplier；
First enable signal connects the second input of the first multiplier, and first enable signal also passes through the 5th
Phase inverter connects the 3rd input of the first multiplier；Second enable signal connects the second input of the second multiplier,
Second enable signal also connects the 3rd input of the second multiplier by hex inverter；3rd enable signal connects
The second input of the 3rd multiplier is connect, the 3rd enable signal also connects the 3rd of the 3rd multiplier the by the 7th phase inverter
Input；4th enable signal connects the second input of the 4th multiplier, and the 4th enable signal also passes through the 8th
Phase inverter connects the 3rd input of the 4th multiplier；Methods described includes：
When first enable signal is 1, the first multiplier conducting, the reference clock passes through the first buffer
The first work clock is exported from the output end of the 9th phase inverter；
When second enable signal is 1, the second multiplier conducting, the reference clock is by the first buffering
Device, the second buffer export the second work clock from the output end of the 9th phase inverter；
When the 3rd enable signal is 1, the 3rd multiplier conducting, the reference clock is by the first buffering
Device, the second buffer, the 3rd buffer export the 3rd work clock from the output end of the 9th phase inverter；
When the 4th enable signal is 1, the 4th multiplier conducting, the reference clock is by the first buffering
Device, the second buffer, the 3rd buffer, the 4th buffer export the 4th work clock from the output end of the 9th phase inverter.
Compared with prior art, the present invention includes advantages below：
The embodiment of the present invention selects appropriate clock driving chain of inverters according to the change of operating voltage, because clock driving is anti-
Phase device chain is variable, is no longer a fixed value so that delay of the chain of inverters of work clock under different operating voltage
In a less scope, so as to reduce the retention time window of output data, facilitate data sampling, while will not increase again
The transmission delay of output data.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram based on work clock output data of prior art；
Fig. 2 is a kind of work schedule circuit of prior art；
Fig. 3 is a kind of output data retention time of prior art with the curve map of voltage change；
Fig. 4 is a kind of structured flowchart of output time holding circuit embodiment 1 of the present invention；
Fig. 5 is a kind of structured flowchart of output time holding circuit embodiment 2 of the present invention；
Fig. 6 is a kind of circuit diagram of voltage comparison unit of the present invention；
Fig. 7 is a kind of circuit diagram of enabling unit of the present invention；
Fig. 8 is a kind of circuit diagram of clock driver cell of the present invention；
Fig. 9 is a kind of output data retention time of the present invention with the curve map of voltage change；
Figure 10 is a kind of step flow chart of output time keeping method embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
A kind of circuit diagram based on work clock output data of prior art shown in reference picture 1, specifically include anti-
Phase device chain, the chain of inverters include buffer and phase inverter.Data at work clock trailing edge when trigger, transfer data to
On output port, in order to increase the driving force of clock, work clock is needed by a chain of inverters.Work clock trailing edge
To the retention time that data variation is output data, work clock trailing edge to data stabilization is the transmission delay of data.Data
Sampling window be：Tclk–Tdelay+Tholdtime(TclkFor operating clock cycle, TdelayFor transmission delay, TholdtimeDuring to keep
Between), when the window ranges of retention time are bigger, the sampling window of data also increases therewith, and Fig. 1 sampling window can specifically join
According to a kind of work schedule circuit of the prior art shown in Fig. 2, Fig. 1 output data retention time is referring in particular to shown in Fig. 3
A kind of output data retention time of prior art with voltage change curve map, it will therefore be readily appreciated that with the rise of operating voltage,
The retention time of output data constantly reduces, and result in the expansion of the retention time window of output data.
In order to solve the above problems, one of the core concepts of the embodiments of the present invention is, is selected according to the change of operating voltage
Select appropriate clock driving chain of inverters so that work clock is using the chain of inverters of different length, under different operating voltage
Time delay be able to maintain that in a less scope, so as to reduce the change model of the retention time window of output data
Enclose, facilitate output data to sample, while do not increase the transmission delay of output data.
Reference picture 4, a kind of structured flowchart of output time holding circuit embodiment 1 of the present invention is shown, can specifically be wrapped
Include such as lower unit：
Voltage comparison unit 101, for operating voltage compared with preset reference voltage, to be obtained at least two ratios
Compared with consequential signal；
Enabling unit 102, for producing at least two enable signals according at least two comparative results signal；
Clock driver cell 103, for receiving reference clock；And adopted respectively according at least two enable signal
With the chain of inverters of at least two-way different length, the reference clock is adjusted to the correspondingly sized work clock of at least two-way.
First by voltage comparison unit 101, by operating voltage compared with preset reference voltage, to obtain at least
Two comparative result signals, judge the threshold range of the operating voltage, enabling unit 102 is according at least two comparative result signals
At least two enable signals are produced, to the chain of inverters in clock driver cell 103 using suitable length, clock driving is single
After member 103 receives reference clock, the chain of inverters of at least two-way different length is respectively adopted according at least two enable signals,
Reference clock is adjusted to the correspondingly sized work clock of at least two-way.
The driving chain of inverters of proper operation clock is selected according to the change of operating voltage in embodiments of the present invention so that
Delay of the chain of inverters of work clock under different operating voltage is in a less scope, so as to reduce output data
Retention time window, facilitate data sampling, while the transmission delay of data will not be increased again.
Reference picture 5, a kind of structured flowchart of output time holding circuit embodiment 2 of the present invention is shown, can specifically be wrapped
Include such as lower unit：
Voltage comparison unit 201, for operating voltage compared with preset reference voltage, to be obtained at least two ratios
Compared with consequential signal；
In one preferred embodiment of the invention, at least two comparative results signal can compare knot including first
Fruit signal, the second comparative result signal, the 3rd comparative result signal, wherein, the first comparative result signal can be by work
Make voltage to obtain compared with preset minimum reference voltage；The second comparative result signal can be by operating voltage with
Preset intermediate reference voltage is compared acquisition；The 3rd comparative result signal can be by operating voltage with it is preset most
High reference voltage is compared acquisition.
A kind of circuit diagram of voltage comparison unit of the invention shown in reference picture 6, the voltage comparison unit 201 can be with
Including first voltage comparator, second voltage comparator and tertiary voltage comparator, the first voltage comparator, the second electricity
Pressure comparator and tertiary voltage comparator positive input terminal can connect operating voltage；The negative input of the first voltage comparator
End can connect minimum reference voltage, and the negative input end of the second voltage comparator can connect intermediate reference voltage, described
The negative input end of tertiary voltage comparator can connect highest reference voltage；The first voltage comparator can according to it is described most
Low reference voltage exports the first comparative result signal from output end；The second voltage comparator can be according to the middle reference
Voltage exports the second comparative result signal from output end；The tertiary voltage comparator can according to the highest reference voltage from
Output end exports the 3rd comparative result signal, and the voltage comparison unit can include：
When operating voltage is less than the minimum reference voltage, the first comparative result signal can be 0, and second compares
Consequential signal can be 0, and the 3rd comparative result signal can be 0；
When operating voltage is more than the minimum reference voltage, during less than the intermediate reference voltage, described first compares knot
Fruit signal can be 1, and the second comparative result signal can be 0, and the 3rd comparative result signal can be 0；
When operating voltage is more than the intermediate reference voltage, during less than the highest reference voltage, described first compares knot
Fruit signal can be 1, and the second comparative result signal can be 1, and the 3rd comparative result signal can be 0；
When operating voltage is more than the highest reference voltage, the first comparative result signal can be 1, and second compares
Consequential signal can be 1, and the 3rd comparative result signal can be 1.
Operating voltage is divided into fourth gear, respectively 0~V in embodiments of the present inventionl, Vl~Vm, Vm~Vh, Vh~+∞, its
In, VlRepresent minimum reference voltage, VmRepresent intermediate reference voltage, VhRepresent highest reference voltage.In the specific implementation, outl
The first consequential signal exported for the output end of first voltage comparator, outmFor second voltage comparator output end export
Second consequential signal, outhThe 3rd consequential signal exported for the output end of tertiary voltage comparator, when operating voltage is less than Vl
When, the first comparative result signal is 0, i.e. outl=" 0 ", the second comparative result signal are 0, i.e. outm=" 0 ", the 3rd compares knot
Fruit signal is 0, i.e. outh=" 0 "；When operating voltage is in Vl~VmBetween when, the first comparative result signal be 1, i.e. outl=" 1 ",
Second comparative result signal is 0, i.e. outm=" 0 ", the 3rd comparative result signal are 0, i.e. outh=" 0 "；When operating voltage is in Vm
~VhBetween when, the first comparative result signal be 1, i.e. outl=" 1 ", the second comparative result signal 1, i.e. outm=" 1 ", the 3rd ratio
Be 0 compared with consequential signal, i.e. outh=" 0 "；When voltage is higher than VhWhen, the first comparative result signal is 1, i.e. outl=" 1 ", second
Comparative result signal is 1, i.e. outm=" 1 ", the 3rd comparative result signal are 1, i.e. outh=" 1 ".
Certainly, the circuit of above-mentioned voltage comparison unit is solely for example, and those skilled in the art can accordingly increase work
Make division and the voltage comparator of voltage gear, or the division of voltage gear and operating voltage are operated using other modes
Compare, the present invention need not be any limitation as to this.
Enabling unit 202, for producing at least two enable signals according at least two comparative results signal；
In one preferred embodiment of the invention, at least two enable signal can include the first enable signal,
Second enable signal, the 3rd enable signal, the 4th enable signal；A kind of electricity of enabling unit of the invention shown in reference picture 7
Lu Tu, the enabling unit 202 can include the first phase inverter, the second phase inverter, the 3rd phase inverter, first with logic element,
Second can connect first with logic element, the 3rd with logic element and the 4th and logic element, the first comparative result signal
The input of phase inverter, second with the first input end of logic element, the 3rd with the first input end of logic element and the 4th with
The first input end of logic element, the second comparative result signal can connect the input of the second phase inverter, the 3rd and logic basis
Second input of part and the 4th it can connect the 3rd phase inverter with the second input of logic element, the 3rd comparative result signal
Input and the 4th with the 3rd input of logic element；The enabling unit includes：
When the first comparative result signal is 0, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The first enable signal for 1 can be exported from the output end of described first and logic element；
When the first comparative result signal is 1, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The second enable signal for 1 can be exported from the output end of described second and logic element；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 0,
The 3rd enable signal for 1 can be exported from the output end of the described 3rd and logic element；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 1,
The 4th enable signal for 1 can be exported from the output end of the described 4th and logic element.
In embodiments of the present invention, en0 is first the first enable signal with the output end output of logic element, and en1 is
Second the second enable signal exported with the output end of logic element, en2 be the 3rd exported with the output end of logic element the
Three enable signals, en3 is the 4th the 4th enable signal with the output end output of logic element, when the first comparative result signal is
0, i.e. outl=" 0 ", the second comparative result signal are 0, i.e. outm=" 0 ", the 3rd comparative result signal are 0, i.e. outh=" 0 "
When, export the first enable signal, i.e. en0=" 1 "；When the first comparative result signal be 1, i.e. outl=" 1 ", the second comparative result
Signal is 0, i.e. outm=" 0 ", the 3rd comparative result signal are 0, i.e. outhDuring=" 0 ", the second enable signal, i.e. en1=are exported
“1”；When the first comparative result signal be 1, i.e. outl=" 1 ", the second comparative result signal are 1, i.e. outm=" 1 ", the 3rd compares
Consequential signal is 1, i.e. outhDuring=" 0 ", the 3rd enable signal, i.e. en2=" 1 " are exported；When the first comparative result signal be 1,
That is outl=" 1 ", the second comparative result signal are 1, i.e. outm=" 1 ", the 3rd comparative result signal are 1, i.e. outhDuring=" 1 ",
Export the 4th enable signal, i.e. en3=" 1 ".
Certainly, the above-mentioned circuit for enabling unit is solely for example, and those skilled in the art can accordingly increase defeated
The enable signal gone out, or enabling unit is realized using other logic combination circuits, the embodiment of the present invention is not limited this
System.
Clock driver cell 203, for receiving reference clock；And adopted respectively according at least two enable signal
With the chain of inverters of at least two-way different length, the reference clock is adjusted to the correspondingly sized work clock of at least two-way.
In one preferred embodiment of the invention, at least two-way work clock can include the first work clock,
Second work clock, the 3rd work clock and the 4th work clock；First work clock can be enabled according to first
Signal, the reference clock is adjusted using the first chain of inverters and formed；Second work clock can be enabled according to second
Signal, the reference clock is adjusted using the second chain of inverters and formed；3rd work clock can be enabled according to the 3rd
Signal, the reference clock is adjusted using the 3rd chain of inverters and formed；4th work clock can be enabled according to the 4th
Signal, the reference clock is adjusted using the 4th chain of inverters and formed；
Wherein, first chain of inverters can be most short chain of inverters, and second chain of inverters can be for for institute
State the chain of inverters that most short chain of inverters increase first-level buffer device is formed, the 3rd chain of inverters can be for it is described most
The chain of inverters that short chain of inverters increase two-stage buffer is formed, the 4th chain of inverters can be for described most short anti-
The chain of inverters that phase device chain increase three-level buffer is formed.
A kind of circuit diagram of clock driver cell of the invention shown in reference picture 8, the clock driver cell 203 can be with
Including the first buffer, the second buffer, the 3rd buffer, the 4th buffer, the 5th phase inverter, hex inverter, the 7th anti-
Phase device, the 8th phase inverter, the 9th phase inverter, the first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier, its
In, first multiplier, the second multiplier, the output end of the 3rd multiplier and the 4th multiplier are connected to the 9th phase inverter
Input；
The input of first buffer can receive reference clock；The output end of first buffer can connect
The input of the first input end of first multiplier and the second buffer；The output end of second buffer can connect second
The input of the first input end of multiplier and the 3rd buffer；The output end of 3rd buffer can connect the 3rd multiplication
The input of the first input end of device and the 4th buffer；The output end of 4th buffer can connect the 4th multiplier
First input end；
First enable signal can connect the second input of the first multiplier, and first enable signal can be with
The 3rd input of the first multiplier is connected by the 5th phase inverter；Second enable signal can connect the second multiplier
Second input, second enable signal can also connect the 3rd input of the second multiplier by hex inverter；Institute
The second input of the 3rd multiplier can be connected by stating the 3rd enable signal, and the 3rd enable signal can also be anti-by the 7th
Phase device connects the 3rd input of the 3rd multiplier；4th enable signal can connect the second input of the 4th multiplier
End, the 4th enable signal can also connect the 3rd input of the 4th multiplier by the 8th phase inverter；Methods described bag
Include：
When first enable signal is 1, the first multiplier conducting, it is slow that the reference clock can pass through first
Rush device and export the first work clock from the output end of the 9th phase inverter；
When second enable signal is 1, the second multiplier conducting, it is slow that the reference clock can pass through first
Device is rushed, the second buffer exports the second work clock from the output end of the 9th phase inverter；
When the 3rd enable signal is 1, the 3rd multiplier conducting, it is slow that the reference clock can pass through first
Device, the second buffer are rushed, the 3rd buffer exports the 3rd work clock from the output end of the 9th phase inverter；
When the 4th enable signal is 1, the 4th multiplier conducting, it is slow that the reference clock can pass through first
Rush device, the second buffer, the 3rd buffer, output end output fourth work clock of the 4th buffer from the 9th phase inverter.
In the specific implementation, with the rise of operating voltage, the operating rate of chain of inverters also has a greater change.Scheming
In 8, when operating voltage is less than VlWhen, the operating rate of chain of inverters is slower, the most short chain of inverters of use, i.e., slow using first
Rush device and the 9th phase inverter forms most short chain of inverters (clk0, clkb0)；When operating voltage is in Vl~VmBetween when, chain of inverters
Operating rate is accelerated, and this when of increase one-level chain of inverters, increases working time of phase inverter, using the first buffer, the
Two buffers and the 9th phase inverter form two level chain of inverters (clk1, clkb1)；When operating voltage is in Vm~VhBetween when, phase inverter
The operating rate of chain is further speeded up, and is further added by one-level chain of inverters this when, is increased the working time of phase inverter, that is, is used
First buffer, the second buffer, the 3rd buffer and the 9th phase inverter form three-level chain of inverters (clk2, clkb2)；Work as work
It is V to make voltagehWhen, the most long chain of inverters of use, i.e., using the first buffer, the second buffer, the 3rd buffer, the 4th is slow
Rush device and the 9th phase inverter forms level Four chain of inverters (clk3, clkb3).It is so anti-according to the rise of operating voltage, corresponding increase
The length of phase device chain, the working time of chain of inverters is set to be unlikely to be influenceed to reduce excessively by operating voltage.That is in scheme
When it is implemented, i.e. when the first enable signal of input, i.e. en0=" 1 ", chain of inverters (clk1, clkb1), (clk2,
clkb2), (clk3, clkb3) be not selected；When inputting the second enable signal, i.e. during en1=" 1 ", chain of inverters (clk0,
clkb0), (clk2, clkb2), (clk3, clkb3) be not selected；When the 3rd enable signal of input, i.e. en2=" 1 ", phase inverter
Chain (clk0, clkb0), (clk1, clkb1), (clk3, clkb3) be not selected；As the 4th enable signal of input, i.e. en3=" 1 "
When, chain of inverters (clk0, clkb0), (clk1, clkb1), (clk2, clkb2) be not selected.
Using the voltage comparison unit of the embodiment of the present invention, enabling unit, the output time of clock driver cell composition is protected
Circuit is held, the window control of output data retention time can be made in a less scope.Using Fig. 6, Fig. 7, Fig. 8 circuits
A kind of output data retention time of the invention that the output data retention time afterwards is specifically referred to shown in Fig. 9 becomes with voltage
The curve map of change, it can be seen that with the increase of operating voltage, the window of the retention time of output data will not drastically expand,
And be held in one it is relatively stable within the scope of, so facilitate data sampling, while the transmission delay of data will not be increased again.
Certainly, the above-mentioned circuit for clock driver cell is solely for example, and those skilled in the art can accordingly increase
Add the chain of inverters of output, the embodiment of the present invention is not restricted to this.
Reference picture 10, the step flow chart for the embodiment of the method that a kind of output time of the present invention is kept is shown, specifically may be used
To comprise the following steps：
Step 301, by operating voltage compared with preset reference voltage, at least two comparative result signals are obtained；
In one preferred embodiment of the invention, at least two comparative results signal can compare knot including first
Fruit signal, the second comparative result signal, the 3rd comparative result signal, wherein, the first comparative result signal can be by work
Make voltage to obtain compared with preset minimum reference voltage；The second comparative result signal can be by operating voltage with
Preset intermediate reference voltage is compared acquisition；The 3rd comparative result signal can be by operating voltage with it is preset most
High reference voltage is compared acquisition.
In one preferred embodiment of the invention, the comparative result signal is generated by voltage comparison unit, the electricity
Pressure comparing unit can include first voltage comparator, second voltage comparator and tertiary voltage comparator, first electricity
Pressure comparator, second voltage comparator and tertiary voltage comparator positive input terminal can connect operating voltage；First electricity
The negative input end of pressure comparator can connect minimum reference voltage, during the negative input end of the second voltage comparator can connect
Between reference voltage, the negative input end of the tertiary voltage comparator can connect highest reference voltage；The first voltage compares
Device can export the first comparative result signal according to the minimum reference voltage from output end；The second voltage comparator can be with
According to the intermediate reference voltage the second comparative result signal is exported from output end；The tertiary voltage comparator can be according to institute
State highest reference voltage and export the 3rd comparative result signal from output end, methods described can include：
When operating voltage is less than the minimum reference voltage, the first comparative result signal can be 0, and second compares
Consequential signal can be 0, and the 3rd comparative result signal can be 0；
When operating voltage is more than the minimum reference voltage, during less than the intermediate reference voltage, described first compares knot
Fruit signal can be 1, and the second comparative result signal can be 0, and the 3rd comparative result signal can be 0；
When operating voltage is more than the intermediate reference voltage, during less than the highest reference voltage, described first compares knot
Fruit signal can be 1, and the second comparative result signal can be 1, and the 3rd comparative result signal can be 0；
When operating voltage is more than the highest reference voltage, the first comparative result signal can be 1, and second compares
Consequential signal can be 1, and the 3rd comparative result signal can be 1.
Step 302, at least two enable signals are produced according at least two comparative results signal；
In one preferred embodiment of the invention, at least two enable signal can include the first enable signal,
Second enable signal, the 3rd enable signal, the 4th enable signal；The enable signal is generated by enabling unit, the enabled list
Member can be including the first phase inverter, the second phase inverter, the 3rd phase inverter, first and logic element, second and logic element, the 3rd
With logic element and the 4th and logic element, the first comparative result signal can connect the input of the first phase inverter, second
First input end with logic element, the 3rd with the first input end of logic element and the 4th with the first input of logic element
End, the second comparative result signal can connect the input of the second phase inverter, the 3rd with the second input of logic element and the
Four can connect the input and the 4th of the 3rd phase inverter with patrolling with the second input of logic element, the 3rd comparative result signal
Collect the 3rd input of element；The enabling unit includes：
When the first comparative result signal is 0, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The first enable signal for 1 can be exported from the output end of described first and logic element；
When the first comparative result signal is 1, the second comparative result signal is 0, when the 3rd comparative result signal is 0,
The second enable signal for 1 can be exported from the output end of described second and logic element；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 0,
The 3rd enable signal for 1 can be exported from the output end of the described 3rd and logic element；
When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 1,
The 4th enable signal for 1 can be exported from the output end of the described 4th and logic element.
Step 303, reference clock is received；And it is respectively adopted at least that two-way is not according at least two enable signal
With the chain of inverters of length, the reference clock is adjusted to the correspondingly sized work clock of at least two-way.
In one preferred embodiment of the invention, at least two-way work clock can include the first work clock,
Second work clock, the 3rd work clock and the 4th work clock；First work clock can be enabled according to first
Signal, the reference clock is adjusted using the first chain of inverters and formed；Second work clock can be enabled according to second
Signal, the reference clock is adjusted using the second chain of inverters and formed；3rd work clock can be enabled according to the 3rd
Signal, the reference clock is adjusted using the 3rd chain of inverters and formed；4th work clock can be enabled according to the 4th
Signal, the reference clock is adjusted using the 4th chain of inverters and formed；
Wherein, first chain of inverters can be most short chain of inverters, and second chain of inverters can be for for institute
State the chain of inverters that most short chain of inverters increase first-level buffer device is formed, the 3rd chain of inverters can be for it is described most
The chain of inverters that short chain of inverters increase two-stage buffer is formed, the 4th chain of inverters can be for described most short anti-
The chain of inverters that phase device chain increase three-level buffer is formed.
In one preferred embodiment of the invention, the drive signal is used to drive clock driver cell, the clock
Driver element can include the first buffer, the second buffer, the 3rd buffer, the 4th buffer, the 5th phase inverter, the 6th anti-
Phase device, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the first multiplier, the second multiplier, the 3rd multiplier and
Four multipliers, wherein, the output end connection of first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier
To the 9th inverter input；
The input of first buffer can receive reference clock；The output end of first buffer can connect
The input of the first input end of first multiplier and the second buffer；The output end of second buffer can connect second
The input of the first input end of multiplier and the 3rd buffer；The output end of 3rd buffer can connect the 3rd multiplication
The input of the first input end of device and the 4th buffer；The output end of 4th buffer can connect the 4th multiplier
First input end；
First enable signal can connect the second input of the first multiplier, and first enable signal can be with
The 3rd input of the first multiplier is connected by the 5th phase inverter；Second enable signal can connect the second multiplier
Second input, second enable signal can also connect the 3rd input of the second multiplier by hex inverter；Institute
The second input of the 3rd multiplier can be connected by stating the 3rd enable signal, and the 3rd enable signal can also be anti-by the 7th
Phase device connects the 3rd input of the 3rd multiplier；4th enable signal can connect the second input of the 4th multiplier
End, the 4th enable signal can also connect the 3rd input of the 4th multiplier by the 8th phase inverter；The clock drives
Moving cell can include：
When first enable signal is 1, the first multiplier conducting, it is slow that the reference clock can pass through first
Rush device and export the first work clock from the output end of the 9th phase inverter；
When second enable signal is 1, the second multiplier conducting, it is slow that the reference clock can pass through first
Device is rushed, the second buffer exports the second work clock from the output end of the 9th phase inverter；
When the 3rd enable signal is 1, the 3rd multiplier conducting, it is slow that the reference clock can pass through first
Device, the second buffer are rushed, the 3rd buffer exports the 3rd work clock from the output end of the 9th phase inverter；
When the 4th enable signal is 1, the 4th multiplier conducting, it is slow that the reference clock can pass through first
Rush device, the second buffer, the 3rd buffer, output end output fourth work clock of the 4th buffer from the 9th phase inverter.
It should be noted that for embodiment of the method, in order to be briefly described, therefore it is all expressed as to a series of action group
Close, but those skilled in the art should know, the present invention is not limited by described sequence of movement, because according to this hair
Bright, some steps can use other orders or carry out simultaneously.Secondly, those skilled in the art should also know, specification
Described in embodiment belong to preferred embodiment, necessary to involved action and the unit not necessarily present invention.
Each embodiment in this specification is described by the way of progressive, what each embodiment stressed be with
The difference of other embodiment, between each embodiment identical similar part mutually referring to.
Above to a kind of output time holding circuit provided by the present invention and method, it is described in detail, herein
Apply specific case to be set forth the principle and embodiment of the present invention, the explanation of above example is only intended to help
Understand the method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention,
There will be changes in specific embodiments and applications, in summary, this specification content should not be construed as to this
The limitation of invention.
Claims (10)
- A kind of 1. output time holding circuit, it is characterised in that including：Voltage comparison unit, for compared with preset reference voltage, operating voltage to be obtained at least two comparative results Signal；Enabling unit, for producing at least two enable signals according at least two comparative results signal；Clock driver cell, for receiving reference clock；And it is respectively adopted at least two according at least two enable signal The chain of inverters of road different length, the reference clock is adjusted to the correspondingly sized work clock of at least two-way；The correspondingly sized work clock of at least two-way includes the first work clock, the second work clock, the 3rd work clock And the 4th work clock；First work clock is according to the first enable signal, using described in the adjustment of the first chain of inverters Reference clock is formed；Second work clock is according to the second enable signal, and the benchmark is adjusted using the second chain of inverters Clock is formed；3rd work clock is according to the 3rd enable signal, and the reference clock is adjusted using the 3rd chain of inverters Formed；4th work clock is according to the 4th enable signal, adjusts the reference clock using the 4th chain of inverters and is formed.
- 2. output time holding circuit according to claim 1, it is characterised in that at least two comparative results signal Including the first comparative result signal, the second comparative result signal, the 3rd comparative result signal, wherein, first comparative result Signal is to obtain operating voltage compared with preset minimum reference voltage；The second comparative result signal is by work Voltage obtains compared with preset intermediate reference voltage；The 3rd comparative result signal be by operating voltage with it is preset Highest reference voltage is compared acquisition.
- 3. output time holding circuit according to claim 2, it is characterised in that the voltage comparison unit includes first Voltage comparator, second voltage comparator and tertiary voltage comparator, the first voltage comparator, second voltage comparator And tertiary voltage comparator positive input terminal connection operating voltage；The negative input end of the first voltage comparator connects minimum ginseng Examine voltage, the negative input end connection intermediate reference voltage of the second voltage comparator, the tertiary voltage comparator it is negative defeated Enter end connection highest reference voltage；The first voltage comparator compares according to the minimum reference voltage from output end output first Compared with consequential signal；The second voltage comparator exports the second comparative result letter according to the intermediate reference voltage from output end Number；The tertiary voltage comparator exports the 3rd comparative result signal, the electricity according to the highest reference voltage from output end Pressure comparing unit includes：When operating voltage is less than the minimum reference voltage, the first comparative result signal is 0, the second comparative result signal For 0, the 3rd comparative result signal is 0；When operating voltage is more than the minimum reference voltage, during less than the intermediate reference voltage, the first comparative result letter Number be 1, the second comparative result signal be 0, the 3rd comparative result signal be 0；When operating voltage is more than the intermediate reference voltage, during less than the highest reference voltage, the first comparative result letter Number be 1, the second comparative result signal be 1, the 3rd comparative result signal be 0；When operating voltage is more than the highest reference voltage, the first comparative result signal is 1, the second comparative result signal For 1, the 3rd comparative result signal is 1.
- 4. output time holding circuit according to claim 1, it is characterised in that at least two enable signal includes First enable signal, the second enable signal, the 3rd enable signal, the 4th enable signal；It is anti-phase that the enabling unit includes first Device, the second phase inverter, the 3rd phase inverter, first and logic element, second and logic element, the 3rd and logic element and the 4th With logic element, the first comparative result signal connect the input of the first phase inverter, second with the first input end of logic element, 3rd with the first input end of logic element and the 4th with the first input end of logic element, the second comparative result signal connection the The input of two phase inverters, the 3rd with the second input of logic element and the 4th with the second input of logic element, the 3rd Comparative result signal connect the 3rd phase inverter input and the 4th with the 3rd input of logic element；The enabling unit bag Include：When the first comparative result signal is 0, the second comparative result signal is 0, when the 3rd comparative result signal is 0, from institute State first with the output of the output end of logic element for 1 the first enable signal；When the first comparative result signal is 1, the second comparative result signal is 0, when the 3rd comparative result signal is 0, from institute State second with the output of the output end of logic element for 1 the second enable signal；When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 0, from institute State the 3rd with the output of the output end of logic element for 1 the 3rd enable signal；When the first comparative result signal is 1, the second comparative result signal is 1, when the 3rd comparative result signal is 1, from institute State the 4th with the output of the output end of logic element for 1 the 4th enable signal.
- 5. output time holding circuit according to claim 1, it is characterised in that first chain of inverters is most short anti- Phase device chain, second chain of inverters to increase the chain of inverters that first-level buffer device formed for the most short chain of inverters, 3rd chain of inverters is increases the chain of inverters that two-stage buffer formed for the most short chain of inverters, and the described 4th Chain of inverters is increases the chain of inverters that three-level buffer formed for the most short chain of inverters.
- 6. output time holding circuit according to claim 5, it is characterised in that the clock driver cell includes first Buffer, the second buffer, the 3rd buffer, the 4th buffer, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th Phase inverter, the 9th phase inverter, the first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier, wherein, described One multiplier, the second multiplier, the output end of the 3rd multiplier and the 4th multiplier are connected to the 9th inverter input；The input of first buffer receives reference clock；The output end of first buffer connects the first multiplier The input of first input end and the second buffer；The output end of second buffer connects the first input of the second multiplier End and the input of the 3rd buffer；The output end of 3rd buffer connects the first input end and the 4th of the 3rd multiplier The input of buffer；The output end of 4th buffer connects the first input end of the 4th multiplier；First enable signal connects the second input of the first multiplier, and first enable signal is also anti-phase by the 5th Device connects the 3rd input of the first multiplier；Second enable signal connects the second input of the second multiplier, described Second enable signal also connects the 3rd input of the second multiplier by hex inverter；3rd enable signal connection the Second input of three multipliers, the 3rd enable signal also connect the 3rd input of the 3rd multiplier by the 7th phase inverter End；4th enable signal connects the second input of the 4th multiplier, and the 4th enable signal is also anti-phase by the 8th Device connects the 3rd input of the 4th multiplier；The clock driver cell includes：When first enable signal is 1, first multiplier conducting, the reference clock is by the first buffer from the The output end of nine phase inverters exports the first work clock；When second enable signal is 1, the second multiplier conducting, the reference clock passes through the first buffer, the Two buffers export the second work clock from the output end of the 9th phase inverter；When the 3rd enable signal is 1, the 3rd multiplier conducting, the reference clock passes through the first buffer, the Two buffers, the 3rd buffer export the 3rd work clock from the output end of the 9th phase inverter；When the 4th enable signal is 1, the 4th multiplier conducting, the reference clock passes through the first buffer, the Two buffers, the 3rd buffer, the 4th buffer export the 4th work clock from the output end of the 9th phase inverter.
- 7. output time holding circuit according to claim 1, it is characterised in that the output time holding circuit is used for In chip.
- 8. a kind of method that output time is kept, it is characterised in that including：By operating voltage compared with preset reference voltage, at least two comparative result signals are obtained；At least two enable signals are produced according at least two comparative results signal；Receive reference clock；And the anti-phase of at least two-way different length is respectively adopted according at least two enable signal Device chain, the reference clock is adjusted to the correspondingly sized work clock of at least two-way；The correspondingly sized work clock of at least two-way includes the first work clock, the second work clock, the 3rd work clock And the 4th work clock；First work clock is according to the first enable signal, using described in the adjustment of the first chain of inverters Reference clock is formed；Second work clock is according to the second enable signal, and the benchmark is adjusted using the second chain of inverters Clock is formed；3rd work clock is according to the 3rd enable signal, and the reference clock is adjusted using the 3rd chain of inverters Formed；4th work clock is according to the 4th enable signal, adjusts the reference clock using the 4th chain of inverters and is formed.
- 9. according to the method for claim 8, it is characterised in that first chain of inverters is most short chain of inverters, described Second chain of inverters is the chain of inverters formed for the most short chain of inverters increase first-level buffer device, and the described 3rd is anti-phase Device chain is the chain of inverters formed for the most short chain of inverters increase two-stage buffer, and the 4th chain of inverters is pin The chain of inverters formed to the most short chain of inverters increase three-level buffer.
- 10. according to the method for claim 9, it is characterised in that at least two enable signal is used to drive clock to drive Moving cell, the clock driver cell include the first buffer, the second buffer, the 3rd buffer, the 4th buffer, the 5th anti- Phase device, hex inverter, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the first multiplier, the second multiplier, the 3rd multiply Musical instruments used in a Buddhist or Taoist mass and the 4th multiplier, wherein, first multiplier, the second multiplier, the 3rd multiplier and the 4th multiplier Output end is connected to the 9th inverter input；The input of first buffer receives reference clock；The output end of first buffer connects the first multiplier The input of first input end and the second buffer；The output end of second buffer connects the first input of the second multiplier End and the input of the 3rd buffer；The output end of 3rd buffer connects the first input end and the 4th of the 3rd multiplier The input of buffer；The output end of 4th buffer connects the first input end of the 4th multiplier；First enable signal connects the second input of the first multiplier, and first enable signal is also anti-phase by the 5th Device connects the 3rd input of the first multiplier；Second enable signal connects the second input of the second multiplier, described Second enable signal also connects the 3rd input of the second multiplier by hex inverter；3rd enable signal connection the Second input of three multipliers, the 3rd enable signal also connect the 3rd input of the 3rd multiplier by the 7th phase inverter End；4th enable signal connects the second input of the 4th multiplier, and the 4th enable signal is also anti-phase by the 8th Device connects the 3rd input of the 4th multiplier；Methods described includes：When first enable signal is 1, first multiplier conducting, the reference clock is by the first buffer from the The output end of nine phase inverters exports the first work clock；When second enable signal is 1, the second multiplier conducting, the reference clock passes through the first buffer, the Two buffers export the second work clock from the output end of the 9th phase inverter；When the 3rd enable signal is 1, the 3rd multiplier conducting, the reference clock passes through the first buffer, the Two buffers, the 3rd buffer export the 3rd work clock from the output end of the 9th phase inverter；When the 4th enable signal is 1, the 4th multiplier conducting, the reference clock passes through the first buffer, the Two buffers, the 3rd buffer, the 4th buffer export the 4th work clock from the output end of the 9th phase inverter.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490784A (en) * | 2002-08-28 | 2004-04-21 | 松下电器产业株式会社 | Data driver |
| CN101517898A (en) * | 2006-08-18 | 2009-08-26 | 松下电器产业株式会社 | A/D converter |
| CN102386925A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Flash type analog to digital converter based on digital front desk correction and analog to digital conversion method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01103016A (en) * | 1987-10-16 | 1989-04-20 | Tdk Corp | Semiconductor integrated circuit for voltage comparison |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490784A (en) * | 2002-08-28 | 2004-04-21 | 松下电器产业株式会社 | Data driver |
| CN101517898A (en) * | 2006-08-18 | 2009-08-26 | 松下电器产业株式会社 | A/D converter |
| CN102386925A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Flash type analog to digital converter based on digital front desk correction and analog to digital conversion method |
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