CN104347703A - Metal-oxide-semiconductor (MOS) device and manufacturing method thereof - Google Patents
Metal-oxide-semiconductor (MOS) device and manufacturing method thereof Download PDFInfo
- Publication number
- CN104347703A CN104347703A CN201310311598.1A CN201310311598A CN104347703A CN 104347703 A CN104347703 A CN 104347703A CN 201310311598 A CN201310311598 A CN 201310311598A CN 104347703 A CN104347703 A CN 104347703A
- Authority
- CN
- China
- Prior art keywords
- ring
- shaped
- source electrode
- drain electrode
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a metal-oxide-semiconductor (MOS) device and a manufacturing method thereof. The device includes: a substrate on which cylindrical source electrode and drain electrode are arranged; an annular cylinder is arranged and surrounds the exteriors of the source electrode and the drain electrode, and the cylinder whose section is annular is not in contact with the source electrode and the drain electrode; the conductivity type of the cylinder whose section is annular is opposite to the conductivity of the source electrode and the drain electrode; a first insulating medium layer is arranged on the surface of the substrate in a middle area between the drain electrode and the drain electrode; and a gate conducting layer is arranged on the surface of the first insulating medium layer. The MOS device provided by the embodiment of the invention effectively solves the technical problem of poor Guard band isolation effect of MOS devices in the prior art.
Description
Technical field
The present invention relates to field of semiconductor device preparation, particularly relate to a kind of Metal-oxide-semicondutor MOS device and its manufacture method.
Background technology
Metal-oxide layer-semiconductor-field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) is a kind of field-effect transistor (field-effect transistor) that can be widely used in analog circuit and digital circuit.MOSFET is different according to the polarity of its " passage ", can be divided into the MOSFET of n-type and p-type, is called for short NMOS and PMOS.
In prior art, for ensureing that NMOS and PMOS works alone separately, when prepared by device, usually adopt boundary belt (Guard band) isolate, namely in the source of device, the peripheral formation in a drain region straight-flanked ring, size is just by source, drain region encirclement.Adulterate with source, impurity that drain region conduction type is contrary because Guard band adopts, structure forms PN junction with source, drain region, therefore Guard band isolation also title PN junction isolate.
But, in low-voltage aluminum gate MOS technique preparation process, the concentration of P+ impurity and the concentration of N+ impurity all very high, the Guard band formed thus is isolated into the Zener diode that structure is P+N+.This structure due to doping content high, PN junction is very narrow, little reverse voltage, just can produce strong electric field in space charge region, causes the charge carrier that in space charge region, generation is a large amount of, and forms electric current, Guard band isolation effect is deteriorated.
Summary of the invention
The invention provides a kind of Metal-oxide-semicondutor MOS device and its manufacture method, in order to solve prior art when manufacturing MOS device, the technical problem of Guard band isolation effect difference.
On the one hand, the embodiment of the present invention provides a kind of Metal-oxide-semicondutor MOS device, comprising:
Substrate, described substrate is provided with the source electrode in cylinder and drain electrode;
On described substrate, the outer peripheral of described source electrode and described drain electrode is provided with the cylinder of ring-shaped section and ring-shaped, and the cylinder of described ring-shaped section and ring-shaped does not contact with described drain electrode with described source electrode;
The conduction type of the cylinder of described ring-shaped section and ring-shaped is contrary with the electric conductivity of described source electrode and described drain electrode;
Described substrate surface, the zone line of described source electrode and described drain electrode is provided with the first insulating medium layer;
Described first insulating medium layer is provided with grid conducting layer on the surface.
On the other hand, the embodiment of the present invention provides a kind of manufacture method of Metal-oxide-semicondutor MOS device, comprising:
The first insulating medium layer is formed at substrate surface;
Described first insulating medium layer forms grid conducting layer;
Described first insulating medium layer and described grid conducting layer are etched, to retain described first insulating medium layer and described grid conducting layer in described substrate surface fixed area;
At substrate surface, source electrode and the drain electrode that Impurity Diffusion formation is cylinder is carried out in corresponding region, described grid conducting layer both sides;
Enclose described source electrode and the outside of described drain electrode over the substrate to carry out Impurity Diffusion and formed and do not contact and the cylinder of ring-shaped section and ring-shaped with described drain electrode with described source electrode, the conduction type of the cylinder of described ring-shaped section and ring-shaped is contrary with the electric conductivity of described source electrode and described drain electrode.
Metal-oxide-semicondutor MOS device provided by the invention and its manufacture method, by enclose on substrate source electrode and the outside of drain electrode carry out Impurity Diffusion formed do not contact and the cylinder of ring-shaped section and ring-shaped with draining with source electrode, the conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode, the Guard band of this structure, can improve the isolation effect to device.
Accompanying drawing explanation
Fig. 1 is the structural representation of a Metal-oxide-semicondutor MOS device provided by the invention embodiment;
Fig. 2 is the flow chart of a kind of Metal-oxide-semicondutor MOS device manufacture method provided by the invention embodiment.
Embodiment
The invention provides a kind of structure of Metal-oxide-semicondutor MOS device, this MOS device structure specifically comprises: substrate, source electrode, drain electrode, cylinder, the first insulating medium layer and grid conducting layer.
This MOS device structure is as follows.
Substrate is provided with the source electrode in cylinder and drain electrode; Should in the source electrode of cylinder and cylinder one end of drain electrode near or flush in substrate surface, the cylinder other end extends to substrate interior; The shapes such as the cross section of this cylinder can be rectangle, circular;
On substrate, the cylinder of a ring-shaped section and ring-shaped is provided with at above-mentioned source electrode and the outer peripheral of drain electrode region, the ring section, one end of this cylinder is close or flush in substrate surface, cylinder other end ring section extends to substrate interior, and the cylinder of this ring-shaped section and ring-shaped does not contact with draining with above-mentioned source electrode, namely there is certain distance with the source electrode comprised in it and side corresponding in draining in the inner ring side of the cylinder of this ring-shaped section and ring-shaped; The ring section of this cylinder can be the ring section of the shape such as rectangle, circle;
The conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode; That is, when the conduction type of source electrode and drain electrode is N-type (electron conduction), then the conduction type of the cylinder of this ring-shaped section and ring-shaped is P type (hole conduction); Or when the conduction type of source electrode and drain electrode is P type (hole conduction), then the conduction type of the cylinder of this ring-shaped section and ring-shaped is N-type (electron conduction);
At substrate surface, the zone line (zone line that the adjacent fringe region as source electrode and drain electrode surrounds at substrate surface) between above-mentioned source electrode and drain electrode is provided with the first insulating medium layer; This first insulating medium layer can be silicon dioxide, silicon nitride etc.;
Be provided with grid conducting layer on the surface at the first insulating medium layer, this grid conducting layer can be polysilicon, various metal; This grid conducting layer and above-mentioned first insulating medium layer cooperatively constitute the grid structure of this MOS device.
Optionally, on the basis in conjunction with the MOS device foundation structure in the present invention described above, Fig. 1 then set forth in detail the structural representation of a specific embodiment of Metal-oxide-semicondutor MOS device in the present invention.As shown in Figure 1, this MOS device structure specifically comprises: substrate 101, source electrode 102, drain electrode 103, cylinder 104, first insulating medium layer 105 and grid conducting layer 106.
MOS device shown in Fig. 1 is on the basis of above-mentioned basic MOS structure, and concrete structure can be as follows.
Be provided with the source electrode 102 in cylinder and drain electrode 103 on the substrate 101; Should source electrode 102 in cylinder and drain electrode 103 cylinder one end near or flush in substrate 101 surface, it is inner that the other end extends to substrate 101; Its cylinder cross section of sectional cylinder of this source electrode 102 and drain electrode 103 specifically can be rectangle.
On substrate 101, the cylinder 104 of a ring-shaped section and ring-shaped is provided with at above-mentioned source electrode 102 and the outer peripheral of drain electrode 103 regions, the ring section, one end of this cylinder 104 is close or flush in substrate 101 surface, it is inner that cylinder 104 other end ring section extends to substrate 101, and the cylinder 104 of this ring-shaped section and ring-shaped and above-mentioned source electrode 102 103 not to contact with draining, namely there is certain distance in inner ring side and the source electrode 102 comprised in it of the cylinder 104 of this ring-shaped section and ring-shaped and the corresponding side in 103 that drains; The ring section of this cylinder 104 is specially rectangular ring section; And the inner ring side of the cylinder 104 of this ring-shaped section and ring-shaped and above-mentioned source electrode 102 are parallel with the side corresponding in 103 that drains.
The conduction type of the cylinder 104 of this ring-shaped section and ring-shaped and source electrode 102 and drain 103 electric conductivity contrary (can see the above-mentioned description to basic MOS device structure);
In embodiment illustrated in fig. 1, if this MOS device is PMOS device, then, in the cylinder 104 of this ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud can be 1.5 microns;
It is 2.5 microns that the cross section of source electrode 102 and drain electrode 103 all can be length, and wide is the rectangle of 2.0 microns, and source electrode 102 and drain 103 the corresponding side in cross section parallel and apart 3.0 microns; The inner ring side of the cylinder 104 of ring-shaped section and ring-shaped and source electrode 102 and the distance drained between side corresponding in 103 are 0.6 micron.
If this MOS device is nmos device, then, in the cylinder 104 of this ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud can be 1.3 microns;
It is 2.3 microns that the cross section of source electrode 102 and drain electrode 103 all can be length, and wide is the rectangle of 1.8 microns, and source electrode 102 and drain 103 the corresponding side in cross section parallel and apart 3.2 microns; The inner ring side of the cylinder 104 of ring-shaped section and ring-shaped and source electrode 102 and the distance drained between side corresponding in 103 are 0.6 micron.
On substrate 101 surface, the zone line (as the zone line that source electrode 102 surrounds on substrate 101 surface with the adjacent fringe region of drain electrode 103) of above-mentioned source electrode 102 and drain electrode 103 is provided with the first insulating medium layer 105; This first insulating medium layer 105 can be silicon dioxide, silicon nitride etc.
Be provided with grid conducting layer 106 on the surface at the first insulating medium layer 105, this grid conducting layer 106 can be polysilicon, various metal; This grid conducting layer 106 and above-mentioned first insulating medium layer 105 cooperatively constitute the grid structure of this MOS device.
Metal-oxide-semicondutor MOS device provided by the invention, be provided with and the cylinder of this source electrode with the discontiguous ring-shaped section and ring-shaped that drains in the outer peripheral of source electrode and drain electrode, and the conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode, the Guard band of this structure, can improve the isolation effect to device.
Fig. 2 is the flow chart of a manufacture method embodiment of a kind of Metal-oxide-semicondutor MOS device provided by the invention.The method can manufacture the above-mentioned MOS device comprising Fig. 1.As shown in Figure 2, the method specifically comprises:
S201, forms the first insulating medium layer at substrate surface;
This substrate can for having lightly doped semi-conducting material, as silicon, gallium nitride, GaAs etc.Have lightly doped semiconductor substrate surface generate the first insulating medium layer at this, this first insulating medium layer can be silicon dioxide, silicon nitride etc.
S202, the first insulating medium layer forms grid conducting layer; This grid conducting layer can be polysilicon, various metal.
S203, etches above-mentioned first insulating medium layer and grid conducting layer, to retain the first insulating medium layer and grid conducting layer in substrate surface fixed area (this fixed area surface can be rectangle, circular etc. shape); The first insulating medium layer be retained and grid conducting layer constitute the grid structure of this MOS device.
S204, at substrate surface, source electrode and the drain electrode that Impurity Diffusion formation is cylinder is carried out in corresponding region, grid conducting layer both sides;
At substrate surface, and the impurity identical with substrate conduction type is injected in the position corresponding near grid conducting layer both sides, and (this doping is generally heavy doping, impurity concentration is higher) to form source electrode and the drain electrode (for source electrode, a cylinder is drain electrode to a cylinder) that two are cylinder.The cross sectional shape of these two cylinders can be, but not limited to as rectangle.
S205, substrate encloses source electrode and the outside of drain electrode and carries out Impurity Diffusion and formed and do not contact and the cylinder of ring-shaped section and ring-shaped with draining with source electrode, the conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode;
On substrate, enclose source electrode and drain electrode to carry out Impurity Diffusion in the perimeter of interior overall region and form one and do not contact and the cylinder of ring-shaped section and ring-shaped with draining with source electrode, the conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode, and dopant concentration level quite (heavy doping).Optionally, the cross section of the cylinder of this ring-shaped section and ring-shaped can be but be not limited to rectangular ring section, and the inner ring side of the cylinder of this ring-shaped section and ring-shaped can be with source electrode and side corresponding in draining but be not limited to parallel relation.
Optionally, concrete manufacture MOS device time, according to MOS type, its corresponding physical dimension can also be set, and size, specifically see in embodiment as shown in Figure 1, the structure of PMOS device or nmos device can be described, do not repeat at this.
The manufacture method of Metal-oxide-semicondutor MOS device provided by the invention, be provided with and the cylinder of this source electrode with the discontiguous ring-shaped section and ring-shaped that drains in the outer peripheral of source electrode and drain electrode, and the conduction type of the cylinder of this ring-shaped section and ring-shaped is contrary with the electric conductivity of source electrode and drain electrode, the Guard band of this structure, can improve the isolation effect to device.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that program command is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a Metal-oxide-semicondutor MOS device, is characterized in that, comprising:
Substrate, described substrate is provided with the source electrode in cylinder and drain electrode;
On described substrate, the outer peripheral of described source electrode and described drain electrode is provided with the cylinder of ring-shaped section and ring-shaped, and the cylinder of described ring-shaped section and ring-shaped does not contact with described drain electrode with described source electrode;
The conduction type of the cylinder of described ring-shaped section and ring-shaped is contrary with the electric conductivity of described source electrode and described drain electrode;
Described substrate surface, the zone line of described source electrode and described drain electrode is provided with the first insulating medium layer;
Described first insulating medium layer is provided with grid conducting layer on the surface.
2. MOS device according to claim 1, it is characterized in that, the cross section of described source electrode and drain electrode is rectangle, and the cross section of the cylinder of described ring-shaped section and ring-shaped is rectangle, and the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped and described source electrode are corresponding with in described drain electrode is parallel.
3. MOS device according to claim 2, is characterized in that, if described MOS device is PMOS device, then, in the cylinder of described ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud are 1.5 microns;
It is 2.5 microns that the cross section of described source electrode and described drain electrode is length, wide is the rectangle of 2.0 microns, and described source electrode is parallel with the corresponding side in the cross section of described drain electrode and at a distance of 3.0 microns, the distance between the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped is corresponding with described source electrode and described drain electrode is 0.6 micron.
4. semiconductor device according to claim 2, is characterized in that, if described MOS device is nmos device, then, in the cylinder of described ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud are 1.3 microns;
It is 2.3 microns that the cross section of described source electrode and described drain electrode is length, wide is the rectangle of 1.8 microns, and described source electrode is parallel with the corresponding side in the cross section of described drain electrode and at a distance of 3.2 microns, the distance between the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped is corresponding with described source electrode and described drain electrode is 0.6 micron.
5. a manufacture method for Metal-oxide-semicondutor MOS device, is characterized in that, comprising:
The first insulating medium layer is formed at substrate surface;
Described first insulating medium layer forms grid conducting layer;
Described first insulating medium layer and described grid conducting layer are etched, to retain described first insulating medium layer and described grid conducting layer in described substrate surface fixed area;
At substrate surface, source electrode and the drain electrode that Impurity Diffusion formation is cylinder is carried out in corresponding region, described grid conducting layer both sides;
Enclose described source electrode and the outside of described drain electrode over the substrate to carry out Impurity Diffusion and formed and do not contact and the cylinder of ring-shaped section and ring-shaped with described drain electrode with described source electrode, the conduction type of the cylinder of described ring-shaped section and ring-shaped is contrary with the electric conductivity of described source electrode and described drain electrode.
6. manufacture method according to claim 5, it is characterized in that, the cross section of described source electrode and drain electrode is rectangle, and the cross section of the cylinder of described ring-shaped section and ring-shaped is rectangle, and the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped and described source electrode are corresponding with in described drain electrode is parallel.
7. manufacture method according to claim 6, is characterized in that, if described MOS device is PMOS device, then, in the cylinder of described ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud are 1.5 microns;
It is 2.5 microns that the cross section of described source electrode and described drain electrode is length, wide is the rectangle of 2.0 microns, and described source electrode is parallel with the corresponding side in the cross section of described drain electrode and at a distance of 3.0 microns, the distance between the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped is corresponding with described source electrode and described drain electrode is 0.6 micron.
8. manufacture method according to claim 6, is characterized in that, if described MOS device is nmos device, then, in the cylinder of described ring-shaped section and ring-shaped, the inner ring in cross section and the spacing of outer shroud are 1.3 microns;
It is 2.3 microns that the cross section of described source electrode and described drain electrode is length, wide is the rectangle of 1.8 microns, and described source electrode is parallel with the corresponding side in the cross section of described drain electrode and at a distance of 3.2 microns, the distance between the side that the inner ring side of the cylinder of described ring-shaped section and ring-shaped is corresponding with described source electrode and described drain electrode is 0.6 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311598.1A CN104347703B (en) | 2013-07-23 | 2013-07-23 | Metal-oxide semiconductor (MOS) MOS device and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311598.1A CN104347703B (en) | 2013-07-23 | 2013-07-23 | Metal-oxide semiconductor (MOS) MOS device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104347703A true CN104347703A (en) | 2015-02-11 |
| CN104347703B CN104347703B (en) | 2016-12-28 |
Family
ID=52502912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310311598.1A Active CN104347703B (en) | 2013-07-23 | 2013-07-23 | Metal-oxide semiconductor (MOS) MOS device and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104347703B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299440A (en) * | 1999-04-15 | 2000-10-24 | Hitachi Ltd | Field effect transistor and integrated voltage generating circuit using the same |
| CN101819947A (en) * | 2009-02-27 | 2010-09-01 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| US20100323487A1 (en) * | 2008-08-13 | 2010-12-23 | Intersil Americas Inc. | Radiation hardened device |
-
2013
- 2013-07-23 CN CN201310311598.1A patent/CN104347703B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299440A (en) * | 1999-04-15 | 2000-10-24 | Hitachi Ltd | Field effect transistor and integrated voltage generating circuit using the same |
| US20100323487A1 (en) * | 2008-08-13 | 2010-12-23 | Intersil Americas Inc. | Radiation hardened device |
| CN101819947A (en) * | 2009-02-27 | 2010-09-01 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104347703B (en) | 2016-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103151391B (en) | The short grid tunneling field-effect transistor of vertical non-uniform doped channel and preparation method | |
| CN103515422A (en) | FinFET with high mobility and strain channel | |
| US8643135B2 (en) | Edge termination configurations for high voltage semiconductor power devices | |
| US9570630B2 (en) | Schottky diode structure | |
| CN103594376B (en) | A kind of knot modulation type tunneling field-effect transistor and preparation method thereof | |
| US9276088B1 (en) | Method for making high voltage integrated circuit devices in a fin-type process and resulting devices | |
| CN105633147A (en) | Tunneling field effect transistor and manufacturing method thereof | |
| CN104409487A (en) | Bidirectional breakdown protection double-gate insulation tunneling enhancement transistor on bulk silicon and manufacture method of transistor | |
| CN102157559B (en) | Low-power consumption tunneling field effect transistor (TFET) of fork-structure grid structure | |
| KR101928629B1 (en) | Two-terminal vertical 1-t dram and manufacturing method thereof | |
| US11309406B2 (en) | Method of manufacturing an LDMOS device having a well region below a groove | |
| CN104409334A (en) | Method for preparing super junction device | |
| CN102723278A (en) | Semiconductor structure formation method | |
| CN110600552B (en) | Power semiconductor device with fast reverse recovery characteristic and manufacturing method thereof | |
| CN107994067B (en) | Semiconductor power device, terminal structure of semiconductor power device and manufacturing method of terminal structure | |
| CN103456773A (en) | Schottky diode and production method thereof | |
| CN112071909A (en) | Three-dimensional metal-oxide field effect transistor and preparation method thereof | |
| CN104347703A (en) | Metal-oxide-semiconductor (MOS) device and manufacturing method thereof | |
| CN104409508A (en) | SOI substrate two-way breakdown protection and double-gate insulated tunneling enhanced transistor and making method thereof | |
| CN104425606A (en) | TFET (Tunneling Field Effect Transistor) and forming method thereof | |
| CN109817711B (en) | Gallium nitride transverse transistor with AlGaN/GaN heterojunction and manufacturing method thereof | |
| CN203179885U (en) | Trench MOSFET power rectification device | |
| US9780171B2 (en) | Fabricating method of lateral-diffused metal oxide semiconductor device | |
| CN104599969A (en) | Method for reducing electric leakage of trench gate structure semi-floating gate device | |
| CN103400860B (en) | N type longitudinal silicon carbide MOS (metal oxide semiconductor) tube with high breakdown voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |