CN104347412A - Manufacture method of VVMOS tube, and VVMOS tube - Google Patents
Manufacture method of VVMOS tube, and VVMOS tube Download PDFInfo
- Publication number
- CN104347412A CN104347412A CN201310331656.7A CN201310331656A CN104347412A CN 104347412 A CN104347412 A CN 104347412A CN 201310331656 A CN201310331656 A CN 201310331656A CN 104347412 A CN104347412 A CN 104347412A
- Authority
- CN
- China
- Prior art keywords
- grid
- layer
- type
- vvmos
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 128
- 239000011241 protective layer Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 10
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 33
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- 150000002500 ions Chemical class 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- -1 boron ion Chemical class 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a manufacture method of a vertical V-type metal oxide semiconductor (VVMOS) tube, and a VVMOS tube. The method comprises a process of forming V-type grooves on the epitaxial layer of a substrate and forming grid oxide layers and grids in the V-type grooves, wherein the process for forming the grid oxide layers in the V-type grooves comprises: forming first grid oxide layers on the surfaces of the epitaxial layers with the V-type grooves formed therein; depositing protective layers on the surfaces of the first grid oxide layers, and employing an etching process on the protective layers to remove the protective layers at the bottom portions of the V-type grooves; forming second grid oxide layers at the bottom portions of the V-type grooves; and removing the residual protective layers. The manufacture method of the VVMOS tube provided by the invention can enable breakdown of the grids of the manufactured VVMOS tube to be difficult, switch loss is difficult, and the service life of a switch is prolonged.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of manufacture method and VVMOS pipe of VVMOS pipe.
Background technology
First vertical V-type groove metal-oxide semiconductor (MOS) (Vertical V-type Metal Oxide Semiconductor is in the world succeeded in developing in June, 1975 from Siliconix company of the U.S., be called for short VVMOS) since power transistor, power metal-oxide semiconductor (Metal Oxide Semiconductor) transistor, be called for short metal-oxide-semiconductor, technology obtains swift and violent development, increasing metal-oxide-semiconductor puts goods on the market, and is widely used in the aspects such as high power switch, linear method, direct current conversion, radio-frequency (RF) power amplification.The particularly metal-oxide-semiconductor of high power switch, the loss problem of switch is especially important.
Fig. 1 is the structural representation of VVMOS pipe in prior art.In prior art, after the surface of epitaxial loayer 101 forms V-type groove, growth grid oxic horizon 103, and carry out the deposition of polysilicon 104.Adopt the VVMOS made by existing manufacture method to manage, as shown in Figure 1, the curvature of its V-type trench bottom 102 is comparatively large, when applying voltage to transistor, concentrates at V-type trench bottom 102 power line, and electric field is comparatively large, easily punctures, the easy loss of switch.
Summary of the invention
The invention provides a kind of manufacture method and VVMOS pipe of VVMOS pipe, to solve the problem that existing VVMOS pipe easily punctures loss.
First aspect, the invention provides a kind of manufacture method of vertical V-type groove metal-oxide semiconductor (MOS) VVMOS pipe, the epitaxial loayer being included in substrate forms V-type groove, and form the flow process of grid oxic horizon and grid in V-type groove, the described flow process forming grid oxic horizon in V-type groove comprises:
The first grid oxic horizon is grown in the epi-layer surface being formed with V-type groove;
Carry out the deposit of protective layer on the surface of described first grid oxide layer, and etching technics is adopted to described protective layer, remove the protective layer of described V-type trench bottom;
Second grid oxide layer is formed at described V-type trench bottom;
Remove remaining protective layer.
Second aspect, the present invention also provides a kind of vertical V-type groove metal-oxide semiconductor (MOS) VVMOS to manage, comprise substrate, epitaxial loayer, be formed in gate oxide in V-type groove and grid, the gate oxide be formed in described V-type groove covers the surface of V-type groove, and forms the triangle gate oxide covering V-type wedge angle at described V-type trench bottom.
The manufacture method of the VVMOS pipe that the present embodiment provides, by being divided into multistep to perform the flow process forming grid oxic horizon, the final grid oxic horizon formed is made to be the thickness of first grid oxide layer and the thickness sum of the second oxide layer at the thickness of V-type trench bottom, namely, the bottom of the groove of the surface of this grid oxic horizon formation grid is moved, thus reduce the curvature of V-type trench bottom, decrease the electric field of V-type trench bottom when grid applies voltage.The grid of the VVMOS pipe adopting the method to make not easily punctures, and switch is loss not easily, thus improves the useful life of switch.
Accompanying drawing explanation
Fig. 1 is the structural representation of VVMOS pipe in prior art;
The flow chart of the manufacture method of the VVMOS pipe that Fig. 2 provides for the embodiment of the present invention one;
The flow chart of the manufacture method of the VVMOS pipe that Fig. 3 provides for the embodiment of the present invention three;
Fig. 4 is the structural representation of grown epitaxial layer in the embodiment of the present invention three
Fig. 5 is the structural representation growing pad oxide in the embodiment of the present invention three;
Fig. 6 is the structural representation forming the epitaxial loayer with V-type groove in the embodiment of the present invention three;
Fig. 7 is the structural representation forming first grid oxide layer in the embodiment of the present invention three;
Fig. 8 is the structural representation of the silicon nitride layer removing V-type trench bottom in the embodiment of the present invention three;
Fig. 9 is the structural representation removing remaining silicon nitride layer in the embodiment of the present invention three;
Figure 10 is the structural representation forming grid polycrystalline silicon in the embodiment of the present invention three;
Figure 11 is the structural representation forming source electrode base in the embodiment of the present invention three;
Figure 12 is the structural representation forming source electrode in the embodiment of the present invention three;
Figure 13 is the structural representation forming lead-in wire figure in the embodiment of the present invention three;
Figure 14 is the structural representation forming metal wiring layer in the embodiment of the present invention three;
Figure 15 is the structural representation of the VVMOS pipe made in the embodiment of the present invention three;
The structural representation of the VVMOS pipe that Figure 16 provides for the embodiment of the present invention four;
Description of reference numerals:
101,402,602,1101,1602: epitaxial wafer;
102:V type trench bottom;
103: grid oxic horizon;
104: polysilicon;
401: silicon substrate;
501,601: pad oxide;
701,1303,1605: first grid oxide layer;
801: silicon nitride layer;
901,1604: second grid oxide layer;
1001: grid polycrystalline silicon;
1102: source electrode base;
1201: source electrode;
1301: first medium layer;
1302: second dielectric layer;
1401: the first metal wiring layer;
1402: the second metal wiring layer;
1502: the three metal lead wires;
1601: substrate;
1603: grid.
Embodiment
Embodiment one
The embodiment of the present invention one provides a kind of manufacture method of VVMOS pipe.The flow chart of the manufacture method of the VVMOS pipe that Fig. 2 provides for the embodiment of the present invention one.The method, the epitaxial loayer being included in substrate forms V-type groove, and form the flow process of grid oxic horizon and grid in V-type groove.As shown in Figure 2, the flow process forming grid oxic horizon in V-type groove comprises:
Step 201, grow the first grid oxic horizon in the epi-layer surface being formed with V-type groove.
The method of thermal oxidation can be adopted in epitaxial loayer superficial growth first grid oxide layer.The method growth oxide layer adopting thermal oxidation can be this had the epitaxial loayer of V-type groove to insert in oxidation furnace to heat certain hour, forms specific fixing oxide layer.Thermal oxidation process is divided into dry oxidation and wet oxidation.If be full of oxygen in oxidation furnace, being then dry method thermal oxidation, if be full of steam and oxygen in oxidation furnace, is then wet oxidation.Because dry oxidation easily controls, by dry oxidation growth grid oxic horizon.
Step 202, carry out the deposit of protective layer on the surface of described first grid oxide layer, and etching technics is adopted to described protective layer, remove the protective layer of described V-type trench bottom.
Should be different from the material of first grid oxide layer at the material of the protective layer of first grid oxide layer surface deposition; when etching removes the protective layer of V-type trench bottom, because the etching gas that adopts or solvent cause damage less or do not have to the grid oxic horizon be positioned at below V-type trench bottom protective layer.
Step 203, form second grid oxide layer at described V-type trench bottom.
The method growing the second grid oxic horizon can be the method growing the first grid oxic horizon in similar above-mentioned steps 201.
Step 204, remove remaining protective layer.
Removing remaining protective layer can be adopt dry etching, also can be adopt wet etching, as long as etch away all remaining protective layers.In technique scheme, the material of described protective layer is preferably silicon nitride.
Considering the factors such as the complexity of subsequent manufacturing processes on the cost of substrate and substrate, is silicon at the material making the conventional substrate of VVMOS pipe.
Consider whether ripe perfect, the etching technics that whether this protective layer is stable and follow-up of the technique of the deposit protective layer whether factor such as degree, in the present embodiment, the material of the protective layer of deposit is silicon nitride.Silicon nitride layer depositing technics is ripe simple, and the etching technics of later stage silicon nitride layer is also more ripe, be that etching gas or the etching solution of wet etching employing of the dry etching employing of silicon nitride layer is all more common, and cost is lower.Select silicon nitride to do cost of manufacture that protective layer can reduce VVMOS pipe.
So far, the grid oxic horizon of VVMOS pipe is formed, and this grid oxic horizon comprises first grid oxide layer and second grid oxide layer.Grid oxic horizon also comprises formation grid after being formed, and source electrode injects, metal level deposit, and etching forms the technological processes such as metal lead wire, does not repeat them here.
The manufacture method of the VVMOS pipe that the present embodiment provides, by being divided into multistep to perform the flow process forming grid oxic horizon, the final grid oxic horizon formed is made to be the thickness of first grid oxide layer and the thickness sum of the second oxide layer at the thickness of V-type trench bottom, namely, the bottom of the groove of the surface of this grid oxic horizon formation grid is moved, thus reduce the curvature of V-type trench bottom, decrease the electric field of V-type trench bottom when grid applies voltage.The grid of the VVMOS pipe adopting the method to make not easily punctures, and switch is loss not easily, thus improves the useful life of switch.
Embodiment two
On the basis of above-described embodiment, the embodiment of the present invention two also provides a kind of manufacture method of VVMOS pipe.
In technique scheme, described substrate is N-type heavy doping substrate; Described epitaxial loayer is N-type light dope epitaxial loayer, and the crystal orientation of described epitaxial loayer is 100, and resistivity is 0.9 Ω .cm, and thickness is 8um.
Specifically, N-type heavy doping substrate, refers to the N-type ion of the surface imp lantation high concentration at silicon substrate.N-type ion is III race's element ion, as boron, aluminium, gallium etc.Heavily doped silicon substrate film monocrystalline body zone lattice structure is complete, shortcoming density is low, and can meet the resistivity of semiconductor device and the requirement of resistive layer thickness, cost performance is high simultaneously.
Heavy doping and light dope are distinguished different with the concentration of Doped ions.Due to the doping content of epitaxial loayer, comparatively heavy doping is low, and make lightly doped epitaxial loayer electric field strength low, resistivity is high, can improve the voltage born of VVMOS pipe.The channel length of the thickness effect VVMOS pipe of epitaxial loayer simultaneously, epitaxial loayer is thicker, raceway groove is longer, the speed that raceway groove is got through is slower, otherwise epitaxial loayer is thinner, it is faster that raceway groove gets through speed, but in subsequent handling source ion injection produce diffusion, make the thickness of epitaxial loayer can not ether little.
At the epitaxial loayer of Grown, need the surface characteristics of reappearing substrate better, consider that in the process of Grown epitaxial loayer, the end in the sunken district of substrate and the constraint on limit easily cause epitaxial loayer pattern drifting, distortion.For reducing distortion and the drift of epitaxial loayer figure, the present embodiment specifically selects the substrate in crystal orientation 100.
To sum up, the present embodiment specifically selects crystal orientation to be 100, and resistivity is 0.9 Ω .cm, and thickness is the N-type light dope epitaxial loayer of 8um.
In such scheme, the material of described first grid oxide layer and described second grid oxide layer is all silicon dioxide;
The thickness of described first grid oxide layer is preferably
The thickness of described second grid oxide layer is preferably
Based on the selection reason similar with above-mentioned protective layer, first grid oxide layer and second grid oxide layer are silicon dioxide.The words that grid second grid oxide layer is too thin, although manage compared with existing VVMOS, anti-dielectric force slightly strengthens, but due to must the varied in thickness of grid oxic horizon little, the curvature of V-type trench bottom is still very large, the probability punctured is also comparatively large, and simultaneously for ensureing the vertical conduction of V-type groove, therefore the present embodiment selection thickness is
first grid oxide layer and thickness be
second grid oxide layer.
Further, the deposit of protective layer is carried out on the surface in first grid oxide layer in such scheme step 202, specifically comprises:
Adopt chemical gas-phase deposition method on the surface of described first grid oxide layer, carry out the deposit of silicon nitride layer.
Chemical gas-phase deposition method, physical vapor deposition methods all belong to the method that the film growth in semiconductor fabrication process is commonly used; the spreadability of the film obtained owing to adopting chemical vapor deposition is better; adopt chemical gas-phase deposition method in the present embodiment; deposit obtains silicon nitride layer; as protective layer, can better protect the first grid oxide layer below it not contaminated.
Further, in such scheme step 202, etching technics is adopted to described protective layer, removes the protective layer of described V-type trench bottom, specifically comprise:
Photoresist mask exposure is carried out to described protective layer, adopts dry etching method, remove the silicon nitride layer of described V-type trench bottom.
Specifically, all uniform application photoresist on the surface of whole protective layer, by the band of position of mask exposure positioning V-shaped trench bottom, etching removes silicon nitride in institute's locating area then.Dry etching can be complete mask exposure location V-type trench bottom silicon nitride remove, and wet etching is due to the mobility of etching solution, the silicon nitride outside locating area may be etched away, thus affect the second grid oxide layer of subsequent growth, and then affect the stability of device parameters of VVMOS pipe.
To the dry etching of silicon nitride layer, can be adopt the gases such as fluoroform, carbon tetrafluoride, sulphur hexafluoride, Nitrogen trifluoride to etch, but the present invention limit at this.
Further, remove remaining protective layer in the step 204 of technique scheme to comprise:
Wet etching etching is adopted to remove remaining silicon nitride layer.
Specifically, different from the silicon nitride layer of above-mentioned etching V-type trench bottom, all get rid of remaining silicon nitride layer at this, thus select easy and simple to handle, the wet etching that cost is lower.To the wet etching of silicon nitride layer, can be adopt hot phosphoric acid as etching solution.
The manufacture method that the present embodiment provides, ensure make obtain VVMOS pipe not easily puncture, basis on, by select specific material protective layer, epitaxial loayer, lithographic method etc. guarantee device parameters stability while, also can reduce cost of manufacture.
Embodiment three
On the basis of above-described embodiment, the embodiment of the present invention three also provides a kind of manufacture method of VVMOS pipe.The present embodiment is specifically described by example.The flow chart of the manufacture method of the VVMOS pipe that Fig. 3 provides for the embodiment of the present invention three.The method, concrete steps are as follows:
Step 301, be 100 in N-type heavily doped surface of silicon growth crystal orientation, resistivity is 0.9 Ω .cm, thickness is the epitaxial loayer of 8um.
Fig. 4 is the structural representation of grown epitaxial layer in the embodiment of the present invention three.As shown in Figure 4, silicon substrate 401 is N-type heavily doped silicon substrate, and epitaxial loayer 402 is the epitaxial loayer of crystal orientation 100, resistivity 0.9 Ω .cm, thickness 8um.
Step 302, superficial growth at above-mentioned epitaxial loayer
silicon dioxide as pad oxide.
Fig. 5 is the structural representation growing pad oxide in the embodiment of the present invention three.As shown in Figure 5, method epitaxial loayer 402 growing pad oxide silicon dioxide can be adopt dry method thermal oxide growth silicon dioxide.
Step 303, photoresist mask exposure technique is adopted to pad oxide and epitaxial loayer, adopt wet etching to be formed with the epitaxial loayer of V-type groove, and remove photoresist and pad oxide.
Fig. 6 is the structural representation forming the epitaxial loayer with V-type groove in the embodiment of the present invention three.Adopt photoresist to expose etching to the pad oxide 501 in above-mentioned Fig. 5 and epitaxial loayer 402, and etch, form pad oxide 601 as shown in Figure 6 and epitaxial loayer 602.This step 303, first photoresist mask exposure is carried out to pad oxide, and with etching two breach, pad oxide 501 is made to become pad oxide 601, then specific in horizontal with vertical incorgruous etching based on wet etching, wet etching is adopted to epitaxial loayer 402, forms the V-type groove as shown in epitaxial loayer 602.Finally, photoresist and pad oxide is removed successively.
Step 304, be formed V-type groove epi-layer surface growth
silicon dioxide, as first grid oxide layer.
Fig. 7 is the structural representation forming first grid oxide layer in the embodiment of the present invention three.In the method that the method for epitaxial loayer superficial growth first grid oxide layer can be similar above-mentioned growth pad oxide, difference is only that thickness is different.This step grows at the surface uniform of epitaxial loayer 602
silicon dioxide using as first grid oxide layer 701.
Step 305, carry out the deposit of silicon nitride layer on the surface of first grid oxide layer, and adopt photo etched mask to etch the silicon nitride layer removing V-type trench bottom.
Fig. 8 is the structural representation of the silicon nitride layer removing V-type trench bottom in the embodiment of the present invention three.On the surface of first grid oxide layer 701, deposit
silicon nitride, as protective layer, and the silicon nitride layer that photo etched mask etching removes V-type trench bottom is carried out to it, forms silicon nitride layer 801 as shown in Figure 8.
Step 306, to grow at V-type trench bottom
silicon dioxide as second grid oxide layer, and remove remaining silicon nitride layer.
Fig. 9 is the structural representation removing remaining silicon nitride layer in the embodiment of the present invention three.At the bottom grown of V-type groove as shown in Figure 8
silicon dioxide as second grid oxide layer 901, and adopt wet etching remove silicon nitride layer 801.
Step 307, surface deposition polysilicon in first grid oxide layer and second grid oxide layer, and carry out polysilicon and return quarter, form grid polycrystalline silicon.
Figure 10 is the structural representation forming grid polycrystalline silicon in the embodiment of the present invention three.Particularly, at the surface deposition of first grid oxide layer and second grid oxide layer
polysilicon, and return to carve and form grid polycrystalline silicon 1001 as shown in Figure 10.
The position of step 308, employing photolithographic masking process determination source electrode base, implanting p-type ion, and carry out knot deeply, form source electrode base.
Figure 11 is the structural representation forming source electrode base in the embodiment of the present invention three.P type ion is group Ⅴ element ion, as phosphorus, antimony, arsenic etc.In the present embodiment, be 180 kilo electron volts with energy, 3.2E13 every cubic centimetre injects boron ion.Wherein energy size determines the degree of depth directly injecting ion, because the boron ion directly injected is more concentrated, therefore adopt and inject in advance, then knot is dark, the uniform ion of injection is diffused to the predetermined degree of depth, instead of directly adopts large energy that it is directly injected the predetermined degree of depth.This step is on the surface of the semiconductor of above-mentioned making, and by the position of photolithographic masking process determination source electrode base, then implanting p-type ion, dark by knot, formation source electrode base 1102 as shown in figure 11, makes epitaxial loayer 602 become epitaxial loayer 1101 simultaneously.
The position of step 309, employing photolithographic masking process determination source electrode, injects N-type ion, and carries out knot deeply, form source electrode.
Figure 12 is the structural representation forming source electrode in the embodiment of the present invention three.In the present embodiment, be 80 kilo electron volts with energy, 4E15 every cubic centimetre injects boron ion.With form the similar reason in source electrode base 1102 in above-mentioned steps 308, this step also adopts first to be injected, then knot is dark, is spread by N-type uniform ion.This step, on the surface of the semiconductor of above-mentioned making, by the position of photolithographic masking process determination source electrode, then injects N-type ion, dark by knot, forms source electrode 1201 as shown in figure 12.
Step 310, after the unadulterated silicon dioxide of the surface sputtering of above-mentioned device, the silicon dioxide of sputtering doping, and by photo etched mask etching technics, form fairlead figure.
Figure 13 is the structural representation forming lead-in wire figure in the embodiment of the present invention three.Unadulterated at the surface sputtering of the device of above-mentioned steps making
silicon dioxide, on this basis, sputtering boron phosphorus doped silicon dioxide
adopt photo etched mask etching technics, etching removes the silicon dioxide layer of the device surface outside gate location.The dielectric layer of grid comprises unadulterated silicon dioxide layer, i.e. first medium layer, and the silicon dioxide of doping is the second dielectric layer of grid, first medium layer 1301 as shown in fig. 13 that, second dielectric layer 1302.The etching of dielectric layer is also etched away to the first grid oxide layer of a part simultaneously, make first grid oxide layer 701 become first grid oxide layer 1303.First medium layer 1301 and second dielectric layer 1302 are lead-in wire empty graphic with the depressed area before surface.
It should be noted that, before chemical wet etching, also comprise the backflow of dielectric layer, namely certain temperature is applied to dielectric layer, with make to be entrained in second dielectric layer ion evenly.At chemical wet etching, after forming fairlead figure, also comprise fairlead and inject boron ion, to reduce the contact resistance of the metal level of fairlead and follow-up making, the energy injecting ion is 60 kilo electron volts, and concentration is 2E15 every cubic centimetre.Finally, also need to carry out heat treatment fast, wherein heat treated temperature is 1050C, and the time is 30 seconds, to activate the ion of injection.
The deposit of step 311, metal level, and carry out alloy technique, form metal wiring layer.
Figure 14 is the structural representation forming metal wiring layer in the embodiment of the present invention three.Carry out the sputtering of titanium and titanium nitride on the surface of the device of above-mentioned steps making, wherein titanium is
titanium nitride is
the titanium sputtered and titanium nitride metal layer are the first metal wiring layer 1401 shown in Figure 14, also need to carry out to the first metal layer the rapid thermal treatment that temperature is 800C, the time is 20 seconds, to make titanium better with contacting of titanium nitride.
Metal wiring layer also comprises the second metal wiring layer 1402, second metal wiring layer for sputtering
aluminium lamination obtain.
After metal wiring layer has sputtered, also need to carry out alloy technique, namely the metal wiring layer sputtered is heated, to make the first metal wiring layer better with contacting of the second metal wiring layer, the temperature of this alloy technique heating is 450C, and the time is 30 minutes.
It should be noted that, this metal wiring layer is source lead layer.
Step 312, carry out thinning overleaf, and deposited metal overleaf, completes the making of VVMOS pipe.
Figure 15 is the structural representation of the VVMOS pipe made in the embodiment of the present invention three.This step, carry out thinning at the back side of the device of such scheme making, namely etch from the back side at silicon substrate 401, thickness becomes 250um, even if silicon substrate 401 becomes silicon substrate 1501, with the direction of growth of grid for front.Deposit respectively overleaf
titanium,
nickel,
silver, deposit generate the metal level comprising titanium bazar metal be the lead-in wire of grid, the 3rd metal lead wire 1502 namely in Figure 15.Finally, also need to test the parameters of the VVMOS pipe made, when parameters all meets the requirements, completed the whole Making programme of VVMOS pipe.
Namely the present embodiment is on the basis of above-described embodiment, and specifically make an explanation with concrete example of making process=and to illustrate, its beneficial effect is similar to the above embodiments, does not repeat them here.
Embodiment four
The embodiment of the present invention four also provides a kind of vertical V-type groove metal-oxide semiconductor (MOS) VVMOS to manage, comprise substrate, epitaxial loayer, be formed in gate oxide in V-type groove and grid, the gate oxide be wherein formed in described V-type groove covers the surface of V-type groove, and forms the triangle gate oxide covering V-type wedge angle at described V-type trench bottom.
The structural representation of the VVMOS pipe that Figure 16 provides for the embodiment of the present invention four.As shown in figure 16, adopt the VVMOS of manufacture method provided by the invention to manage, comprise substrate 1601, epitaxial loayer 1602, be formed in the triangle gate oxide of first grid oxide layer 1605 in V-type groove and V-type trench bottom, i.e. second grid oxide layer 1604, and grid 1603.This first grid oxide layer covers the surface of V-type groove.
The manufacture method of the VVMOS pipe that the VVMOS pipe of the embodiment of the present invention can adopt the embodiment of the present invention to provide is formed.The switch that the VVMOS pipe adopting the embodiment of the present invention to provide makes, because the curvature of V-type trench bottom reduces, greatly improves its breakdown characteristics, thus improves the useful life of switch.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. the manufacture method of a vertical V-type groove metal-oxide semiconductor (MOS) VVMOS pipe, the epitaxial loayer being included in substrate forms V-type groove, and in V-type groove, form the flow process of grid oxic horizon and grid, it is characterized in that, the described flow process forming grid oxic horizon in V-type groove comprises:
The first grid oxic horizon is grown in the epi-layer surface being formed with V-type groove;
Carry out the deposit of protective layer on the surface of described first grid oxide layer, and etching technics is adopted to described protective layer, remove the protective layer of described V-type trench bottom;
Second grid oxide layer is formed at described V-type trench bottom;
Remove remaining protective layer.
2. method according to claim 1, is characterized in that: the material of described protective layer is silicon nitride.
3. method according to claim 1, is characterized in that, described substrate is N-type heavy doping substrate; Described epitaxial loayer is N-type light dope epitaxial loayer, and the crystal orientation of described epitaxial loayer is 100, and resistivity is 0.9 Ω .cm, and thickness is 8um.
4. method according to claim 1, is characterized in that, the material of described first grid oxide layer and described second grid oxide layer is all silicon dioxide;
The thickness of described first grid oxide layer is
The thickness of described second grid oxide layer is
5. method according to claim 2, is characterized in that, the deposit of protective layer is carried out on the described surface in described first grid oxide layer, comprising:
Adopt chemical gas-phase deposition method on the surface of described first grid oxide layer, carry out the deposit of silicon nitride layer.
6. method according to claim 2, is characterized in that, described to described protective layer employing etching technics, removes the protective layer of described V-type trench bottom, comprising:
Photoresist mask exposure is carried out to described protective layer, adopts dry etching method, remove the silicon nitride layer of described V-type trench bottom.
7. method according to claim 2, is characterized in that, the remaining protective layer of described removal comprises:
Wet etching etching is adopted to remove remaining silicon nitride layer.
8. a vertical V-type groove metal-oxide semiconductor (MOS) VVMOS manages, and comprises substrate, epitaxial loayer, is formed in gate oxide in V-type groove and grid, it is characterized in that:
The gate oxide be formed in described V-type groove covers the surface of V-type groove, and forms the triangle gate oxide covering V-type wedge angle at described V-type trench bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310331656.7A CN104347412A (en) | 2013-08-01 | 2013-08-01 | Manufacture method of VVMOS tube, and VVMOS tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310331656.7A CN104347412A (en) | 2013-08-01 | 2013-08-01 | Manufacture method of VVMOS tube, and VVMOS tube |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104347412A true CN104347412A (en) | 2015-02-11 |
Family
ID=52502772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310331656.7A Pending CN104347412A (en) | 2013-08-01 | 2013-08-01 | Manufacture method of VVMOS tube, and VVMOS tube |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104347412A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275210A (en) * | 2016-04-06 | 2017-10-20 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| CN112466755A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | MOS transistor and manufacturing process thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2803431A1 (en) * | 1978-01-26 | 1979-08-02 | Siemens Ag | METHOD OF MANUFACTURING MOS TRANSISTORS |
| US4503449A (en) * | 1981-09-14 | 1985-03-05 | U.S. Philips Corporation | V-Mos field effect transistor |
| JPS6394687A (en) * | 1986-10-09 | 1988-04-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4814839A (en) * | 1977-01-11 | 1989-03-21 | Zaidan Hojin Handotai Kenkyu Shinkokai | Insulated gate static induction transistor and integrated circuit including same |
| CN1056018A (en) * | 1991-03-19 | 1991-11-06 | 电子科技大学 | Semiconductor power device |
| CN101621031A (en) * | 2008-06-20 | 2010-01-06 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof |
-
2013
- 2013-08-01 CN CN201310331656.7A patent/CN104347412A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814839A (en) * | 1977-01-11 | 1989-03-21 | Zaidan Hojin Handotai Kenkyu Shinkokai | Insulated gate static induction transistor and integrated circuit including same |
| DE2803431A1 (en) * | 1978-01-26 | 1979-08-02 | Siemens Ag | METHOD OF MANUFACTURING MOS TRANSISTORS |
| US4503449A (en) * | 1981-09-14 | 1985-03-05 | U.S. Philips Corporation | V-Mos field effect transistor |
| JPS6394687A (en) * | 1986-10-09 | 1988-04-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN1056018A (en) * | 1991-03-19 | 1991-11-06 | 电子科技大学 | Semiconductor power device |
| CN101621031A (en) * | 2008-06-20 | 2010-01-06 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275210A (en) * | 2016-04-06 | 2017-10-20 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| CN107275210B (en) * | 2016-04-06 | 2023-05-02 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN112466755A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | MOS transistor and manufacturing process thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107331616B (en) | Trench junction barrier Schottky diode and manufacturing method thereof | |
| CN101569015B (en) | Semiconductor device and method for manufacturing the same | |
| JP5424192B2 (en) | Self-aligned trench field effect transistor with regrowth gate and bipolar transistor with regrowth base contact region and fabrication method | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| KR20080040544A (en) | Methods of forming field effect transistors having silicon-germanium source and drain regions | |
| JP2001250947A5 (en) | ||
| CN108346688B (en) | SiC trench junction barrier Schottky diode with CSL transport layer and manufacturing method thereof | |
| CN102142372A (en) | Preparation method of field blocking type bipolar transistor of insulated gate | |
| CN109216276B (en) | MOS (Metal oxide semiconductor) tube and manufacturing method thereof | |
| JP6871562B2 (en) | Silicon carbide semiconductor device and its manufacturing method | |
| US7867882B2 (en) | Method of manufacturing silicon carbide semiconductor device | |
| CN111048580A (en) | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof | |
| CN115377200A (en) | Semiconductor device and preparation method thereof | |
| CN107527811B (en) | Lateral insulated gate bipolar transistor and manufacturing method thereof | |
| CN104347412A (en) | Manufacture method of VVMOS tube, and VVMOS tube | |
| CN111463120B (en) | Channel inclined injection preparation method of silicon carbide MOSFET | |
| CN104637879A (en) | Method for preparing semiconductor device | |
| WO2014102994A1 (en) | Silicon-carbide semiconductor device and manufacturing method therefor | |
| JP4135838B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN107342224B (en) | Manufacturing method of VDMOS device | |
| JP4048856B2 (en) | Manufacturing method of semiconductor device | |
| CN205282480U (en) | FS type IGBT device with double buffering layer | |
| KR20090066488A (en) | Vertical transistor and method of manufacturing the same | |
| CN105551944A (en) | Manufacturing method for power transistor | |
| CN106098767A (en) | P ditch Schottky gate carborundum SITH and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150211 |