CN104331251A - Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit - Google Patents

Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit Download PDF

Info

Publication number
CN104331251A
CN104331251A CN201410522232.3A CN201410522232A CN104331251A CN 104331251 A CN104331251 A CN 104331251A CN 201410522232 A CN201410522232 A CN 201410522232A CN 104331251 A CN104331251 A CN 104331251A
Authority
CN
China
Prior art keywords
data
dram
bit
dbi
mask bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410522232.3A
Other languages
Chinese (zh)
Inventor
亚历山大
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Unilc Semiconductors Co Ltd
Original Assignee
Shandong Sinochip Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Sinochip Semiconductors Co Ltd filed Critical Shandong Sinochip Semiconductors Co Ltd
Priority to CN201410522232.3A priority Critical patent/CN104331251A/en
Publication of CN104331251A publication Critical patent/CN104331251A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614Improving the reliability of storage systems

Abstract

The invention provides a function expansion method of a DRAM (Dynamic Random Access Memory) data mask bit. When DRAM reading operation is carried out, a data mask bit of writing operation is used for generating a data path flipping bit (DBI) in the reading operation process; XOR calculation is carried out on data to be read by the DBI bit and a finally-read data output is formed, so that an output eye pattern of a DRAM is improved by reducing the possibility of data flipping, peak value current is reduced during the DRAM reading operation, and furthermore, the system noises are reduced.

Description

A kind of method for developing functions of DRAM data mask bit
Technical field
The present invention relates to semiconductor memory field, be specifically related to a kind of method for developing functions of DRAM data mask bit.
Background technology
Along with in internal memory operation, data bits is more and more wider, the passage of synchronization system generation Data flipping also can get more and more, this can cause system to need to provide more stable environment to go to guarantee that these high-speed turnovers can successfully complete, and each upset of data channel all can produce peak point current, cause system power consumption large, the high-frequency upset of this data simultaneously can bring very Iarge-scale system noise to system.
As shown in Figure 1, in the write operation of high-speed DRAM, we often need to count by data mask bit (DM) data shielding our partial write, but when read operation, data mask bit (DM) is in idle state, is not fully used.
Summary of the invention
The object of the invention is to overcome prior art defect, a kind of method for developing functions of DRAM data mask bit is provided, produce peak point current when data path flip bit (DBI) reduces DRAM read operation by the multiplexing data mask bit (DM) writing path, thus reduce system noise.
For achieving the above object, the present invention by the following technical solutions:
A kind of method for developing functions of DRAM data mask bit, when carrying out DRAM read operation, utilize the data mask bit of write operation to produce the data path flip bit (DBI) during read operation, carry out XOR calculating by DBI position and the data that will read, export as the final data read.
As further prioritization scheme: judge that the data of the data and final reading will carrying out read operation need to overturn the quantity of passage, when needing the quantity overturning passage to be greater than 1/2 of read operation data channel quantity, it is 1 that data path flip bit (DBI) exports, otherwise output is 0.
As further prioritization scheme: every 8 bit data of read operation data introduce 1 data path flip bit (DBI).
The present invention utilizes the data mask bit of existing write operation to produce DBI position during DRAM read operation, XOR calculating is carried out by DBI position and the data that will read, export as the final data read, with the output eye pattern of the probability thus lifting DRAM that reduce Data flipping generation.
Accompanying drawing explanation
Fig. 1 is the schematic diagram carrying out shielding write data in the write operation of DRAM by data mask bit;
Utilize data mask bit to produce the schematic diagram of data path flip bit when Fig. 2 is read operation of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention done and more at large describe.
When internal memory read operation, utilize the data mask bit of write operation to produce the data path flip bit (DBI) during read operation, carry out XOR by DBI position and the data that will read to calculate and output data are carried out DBI algorithm and transform and export, export as the final data read, DBI information is exported by DM passage simultaneously.
Further, first judge that the data of the data and final reading will carrying out read operation need to overturn the quantity of passage, when needing the quantity overturning passage to be greater than 1/2 of total data number of channels, it is 1 that data path flip bit (DBI) exports, otherwise exporting is 0, undertaken exporting after XOR calculates by DBI position and the data that will read.
As shown in Figure 2, when carrying out read operation, every 8 bit data introduce 1 data path flip bit (DBI), when 8 bit data attempt being turned to 11111111 from 00000000 time, introduce 1 DBI position, carry out XOR calculating by the data that will read and DBI position, all passages all need not overturn, the data needing to export can be obtained, thus upset figure place is reduced.The peak point current reduction 30-40% of read operation can be made, thus reduce system noise.

Claims (3)

1. the method for developing functions of a DRAM data mask bit, it is characterized in that: when carrying out DRAM read operation, utilize the data mask bit of write operation to produce the data path flip bit (DBI) during read operation, carry out XOR calculating by DBI position and the data that will read, export as the final data read.
2. the method for developing functions of DRAM data mask bit according to claim 1, it is characterized in that: the data of the data and final reading that judge to carry out read operation need to overturn the quantity of passage, when needing the quantity overturning passage to be greater than 1/2 of read operation data channel quantity, it is 1 that data path flip bit (DBI) exports, otherwise output is 0.
3. the method for developing functions of DRAM data mask bit according to claim 1, is characterized in that: every 8 bit data of read operation data introduce 1 data path flip bit (DBI).
CN201410522232.3A 2014-09-30 2014-09-30 Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit Pending CN104331251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410522232.3A CN104331251A (en) 2014-09-30 2014-09-30 Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410522232.3A CN104331251A (en) 2014-09-30 2014-09-30 Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit

Publications (1)

Publication Number Publication Date
CN104331251A true CN104331251A (en) 2015-02-04

Family

ID=52405986

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410522232.3A Pending CN104331251A (en) 2014-09-30 2014-09-30 Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit

Country Status (1)

Country Link
CN (1) CN104331251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112099733A (en) * 2020-08-26 2020-12-18 瑞芯微电子股份有限公司 DRAM memory time sequence configuration method and device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577608A (en) * 2003-07-03 2005-02-09 三星电子株式会社 Memory system having data inversion and data inversion method for a memory system
US7522073B1 (en) * 2007-11-30 2009-04-21 Qimonda North America Corp. Self-adapted bus inversion
US20130061006A1 (en) * 2011-09-01 2013-03-07 Elpida Memory, Inc. Data mask encoding in data bit inversion scheme

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577608A (en) * 2003-07-03 2005-02-09 三星电子株式会社 Memory system having data inversion and data inversion method for a memory system
US7522073B1 (en) * 2007-11-30 2009-04-21 Qimonda North America Corp. Self-adapted bus inversion
US20130061006A1 (en) * 2011-09-01 2013-03-07 Elpida Memory, Inc. Data mask encoding in data bit inversion scheme

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李卫等: "SDRAM控制器的FPGA设计与实现", 《电子工程师》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112099733A (en) * 2020-08-26 2020-12-18 瑞芯微电子股份有限公司 DRAM memory time sequence configuration method and device

Similar Documents

Publication Publication Date Title
TW200802373A (en) Semiconductor memory
CN104572781A (en) Method and device for generating transaction log
EP3989099A1 (en) Chip design method and design apparatus, computer device, and storage medium
CN106326145A (en) Control method and device for memory
CN103929642A (en) Method for rapidly calculating deviation value of entropy coding context model of HEVC transformation coefficients
CN103338107B (en) Key generation method and key generating device
CN104331251A (en) Function expansion method of DRAM (Dynamic Random Access Memory) data mask bit
CN104463020A (en) Method for protecting data integrity of memory
CN103020551A (en) Memory architecture
CN106021123B (en) A kind of choosing method and selecting system of 3D flash memory physical block
CN103260154B (en) A kind of integrity protection Enhancement Method based on 128-EIA3
CN105373348A (en) Hardware implementation system and method for hybrid memory
US20210286422A1 (en) Data processing device communicating with memory device and data processing method
CN104317525A (en) Random access memory extension method and device
CN204732166U (en) A kind of storer
CN105242982A (en) Error correction method used for NAND-FLASH-adopted electric power acquisition terminal
CN102103893B (en) Device and method for generating test pattern of memory chip
CN208623681U (en) A kind of simple hyperchaotic circuit
Steiner et al. An LPDDR4 safety model for automotive applications
CN105931660A (en) Data topology converter and conversion method and dynamic memory
Lee CRC (cyclic redundancy check) implementation in high-speed semiconductor memory
CN102081965A (en) Circuit for generating inner write clock of dynamic random access memory (DRAM)
CN203366369U (en) Logical N-dimensional UHF-RFID electronic tag integrated circuit
CN106021536A (en) Data insertion method and system based on storage of FICS objects
CN104658595A (en) Memory and method for keeping constant power consumption of power supply of memory

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20170427

Address after: 710075 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4

Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd.

Address before: 250101 Shandong Province, Ji'nan City hi tech Development Zone, Nga Road No. 1036

Applicant before: Shandong Sinochip Semiconductors Co., Ltd.

WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150204