CN104319316B - Efficient film crystal silicon solar battery and its autonomous power chip integrated technology - Google Patents
Efficient film crystal silicon solar battery and its autonomous power chip integrated technology Download PDFInfo
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- CN104319316B CN104319316B CN201410608127.1A CN201410608127A CN104319316B CN 104319316 B CN104319316 B CN 104319316B CN 201410608127 A CN201410608127 A CN 201410608127A CN 104319316 B CN104319316 B CN 104319316B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 398
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 398
- 239000010703 silicon Substances 0.000 title claims abstract description 398
- 239000013078 crystal Substances 0.000 title claims abstract description 203
- 238000005516 engineering process Methods 0.000 title claims abstract description 43
- 238000000407 epitaxy Methods 0.000 claims abstract description 126
- 238000000034 method Methods 0.000 claims abstract description 84
- 238000000576 coating method Methods 0.000 claims abstract description 75
- 239000011248 coating agent Substances 0.000 claims abstract description 73
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 48
- 238000002360 preparation method Methods 0.000 claims abstract description 45
- 230000008569 process Effects 0.000 claims abstract description 42
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 38
- 230000010354 integration Effects 0.000 claims abstract description 36
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 93
- 238000002955 isolation Methods 0.000 claims description 74
- 239000002019 doping agent Substances 0.000 claims description 55
- 238000000137 annealing Methods 0.000 claims description 50
- 238000005530 etching Methods 0.000 claims description 45
- 230000007704 transition Effects 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 26
- 230000005611 electricity Effects 0.000 claims description 23
- 239000000243 solution Substances 0.000 claims description 20
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 18
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 15
- 230000012010 growth Effects 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 238000010790 dilution Methods 0.000 claims description 5
- 239000012895 dilution Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 174
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 239000002210 silicon-based material Substances 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 4
- 238000009776 industrial production Methods 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 382
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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Abstract
The present invention proposes the preparation method of a kind of efficient film crystal silicon solar battery and its autonomous energy integration chip, the process employs silicon thin film epitaxy technology, overcomes CMOS integrated circuits and solar cell and the contradiction between difference is required to silicon materials doping content；Solar cell adopts intrinsic amorphous silicon layer/N-type non-crystalline silicon layer/nesa coating heterojunction structure, improves open-circuit voltage and conversion efficiency, is conducive to improving chip real estate and integrated level；Passivation and the optical characteristics of oxygen buried layer in SOI materials is make use of, film crystal silicon solar battery performance can be improved.In the integrated technology, ITO technologies twice are employed, overcome impact of the high-temperature heat treatment to solar cell performance, particularly open-circuit voltage.The preparation method of the present invention has compatibility with CMOS technology, it is adaptable to large-scale industrial production.
Description
Technical field
The present invention relates to semiconductor and photovoltaic art, more particularly to a kind of more particularly to a kind of efficient film crystal silicon is too
Positive electricity pond and its autonomous power chip integrated technology.
Background technology
Integrated circuit is the basis of information technology and information industry.In recent years, the microelectronics with silicon integrated circuit as core
Technology has obtained rapid development, and its development substantially follows Moore's Law, has been introduced into 14nm node technology epoch, chip
Energy consumption also substantially reduced.But, in some special applications, such as distributed wireless sensor, Micro-Robot, aviation
The particular application of space flight etc., it is desirable to which the chip for being adopted can realize power self-support, to mitigate device energy resource supply and set
The problem of the aspects such as standby overall weight.
Solar cell is a kind of one of most potential green energy resource approved by everybody, can be special for Aero-Space etc.
Under the conditions of the integrated circuit applied the long-term energy is provided.At present, the silicon solar cell of main flow be develop it is most ripe, and its preparation
Technology is substantially compatible with integrated circuit technique, is approved to realize one of energy demand prediction of most rationality of autonomous power chip.
The paper that Chang-Lee Chen in 2011 et al. are delivered in IEEE SOI meetings《SOI Circuits
powered by Embedded Solar Cel l》In describe a kind of integrated circuit for being integrated with solar cell, the technology is filled
Divide and make use of silicon-on-insulator (SOI) material that there is low-power consumption, high speed, integrated level, high temperature resistant and Flouride-resistani acid phesphatase is improved.But
It is that the technology is suffered from the drawback that：Firstth, crystal silicon solar battery structure of its solar cell based on routine, due to semiconductor silicon
Material is different from the requirement of solar cell silicon materials, is to improve battery performance, needs the substrate silicon materials of selected SOI in addition, special
It is not that its doping content needs adjustment；The emitter stage and base implant of the second, solar cell is all based on CMOS technology preparation
, battery open circuit voltage is usual<630mV, limits battery conversion efficiency, and this is accomplished by more large chip area, is unfavorable for providing
Chip integration and reduces cost；3rd, being generally integrated circuit chip needs before encapsulation to substrate thinning, and this can make preparation
The substrate of solar cell sustains damage, and reduces significantly the performance of solar cell being formed on the substrate.Accordingly, it would be desirable to a kind of
Feasible method, make full use of SOI materials have advantage on the basis of, by realize high-performance solar cell and its based on
Autonomous power chip integrated technology.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of efficient film crystal silicon sun is electric
Pond and its autonomous power chip integrated technology, for solving the overall dimensions that solar cell integrated circuit of the prior art is present
Than larger, it is unfavorable for the problem of the integrated level and reduces cost of chip, and to causing to damage to substrate during substrate thinning, enters
And substantially reduce the problem of solar cell performance.
For achieving the above object and other related purposes, the present invention provides a kind of preparation of efficient film crystal silicon solar battery
Method, the efficient film crystal silicon solar battery are at least comprised the following steps：At least comprise the following steps：
1) SOI substrate is provided, the SOI substrate includes backing bottom, oxygen buried layer and top layer silicon from the bottom to top successively；
2) sequentially form in the top layer silicon outside the silicon of silicon epitaxy layer and p-type low doping concentration of p-type high-dopant concentration
Prolong layer；
3) emitter layer is formed on the silicon epitaxy layer of the p-type low doping concentration；
4) etch areas are defined on the emitter layer, the etch areas is performed etching to form groove, it is described
Groove at least includes base region groove；The groove runs through the emitter layer, and the bottom of the groove is low positioned at the p-type
The silicon epitaxy layer of doping content is interior or extends to the silicon epitaxy layer upper surface of the p-type high-dopant concentration；
5) base electrode is prepared in the base region channel bottom；
6) emitter electrode is prepared on the emitter layer；
7) by step 6) obtained by structure carry out annealing heat-treats.
Preferably, in step 2) in, adopted chemical vapour deposition technique is high in p-type described in the top layer silicon Epitaxial growth
The silicon epitaxy layer of the silicon epitaxy layer and p-type low doping concentration of doping content.
Alternatively, in step 3) in, prepare on the silicon epitaxy layer of the p-type low doping concentration emitter layer include it is following
Step：
31) form highly doped using ion implanting or ion diffusion technique on the silicon epitaxy layer of the p-type low doping concentration
The N-type silicon layer of miscellaneous concentration；Doped chemical is P elements；
32) silicon nitride passivation is formed using pecvd process in the N-type silicon layer of the high-dopant concentration.
Alternatively, in step 3) in, prepare on the silicon epitaxy layer of the p-type low doping concentration emitter layer include it is following
Step：
31) using pecvd process successively on the silicon epitaxy layer of the p-type low doping concentration formed intrinsic amorphous silicon layer and
N-type non-crystalline silicon layer；
32) it is deposited in the N-type non-crystalline silicon layer and forms nesa coating using sputtering or reaction and plasma.
Preferably, in step 4) in, gone using wet-etching technology, electrochemical corrosive process or RIE dry etch process
The nesa coating in except the emitter layer, the etchant solution used in the wet-etching technology are dilution HCl
Solution, the etchant solution used in the electrochemical corrosive process are NaOH solution that mass fraction is 5%～15%.
Preferably, in step 4) in, the etch areas are also included on the outside of the base region of the solar cell
Isolation channel.
Preferably, the base electrode and the emitter electrode are prepared using serigraphy or evaporation coating technique.
Preferably, in step 7) in, the annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, the annealing
The temperature of heat treatment is 150 DEG C～350 DEG C.
The present invention also provides a kind of efficient film crystal silicon solar battery, and the solar cell at least includes：SOI substrate, by
Under it is supreme successively include backing bottom, oxygen buried layer and top layer silicon；Epitaxial layer, including the silicon epitaxy layer and p-type of p-type high-dopant concentration be low
The silicon epitaxy layer of doping content；The silicon epitaxy layer of the p-type high-dopant concentration is located at the upper surface of the top layer silicon, the p-type
The silicon epitaxy layer of low doping concentration is located at the upper surface of the silicon epitaxy layer of the p-type high-dopant concentration；Emitter layer, is convexly equipped in institute
State the upper surface of the silicon epitaxy layer of p-type low doping concentration；Groove, at least including base region groove；The groove is through described
Emitter layer, the bottom of the groove is located in the silicon epitaxy layer of the p-type low doping concentration or to extend to the p-type highly doped
The silicon epitaxy layer upper surface of concentration；Base electrode, positioned at the bottom of the base region groove；Emitter electrode, positioned at described
On emitter layer.
Preferably, the thickness of the top layer silicon is 20nm～200nm, and the thickness of the oxygen buried layer is 200～500nm；Institute
Backing bottom is stated for silicon substrate, ceramic substrate or Sapphire Substrate.
Preferably, the material of the epitaxial layer is monocrystalline silicon and/or polysilicon；The silicon epitaxy of the p-type high-dopant concentration
The thickness of layer is 0.05 μm～2 μm, and the concentration of p-type element doping is 5 × 1017～5 × 1019cm-3；The p-type low doping concentration
The thickness of silicon epitaxy layer be 1 μm～50 μm, the concentration of p-type element doping is 5 × 1015～5 × 1017cm-3。
Preferably, the emitter layer is the N-type silicon layer/silicon nitride passivation Rotating fields for including high-dopant concentration；Or to wrap
Include the heterojunction structure of intrinsic amorphous silicon layer/N-type non-crystalline silicon layer/transparent conductive film structure, the thickness of the intrinsic amorphous silicon layer
For 1nm～10nm, the thickness of the N-type non-crystalline silicon layer is 1nm～10nm, the thickness of the nesa coating be 60nm～
120nm。
Preferably, the base electrode constitutes mesa structure, the base electrode and the boss with the boss structure
Spacing between structure is 5 μm～200 μm.
Preferably, the base electrode constitutes pectinate texture, the base electrode and the boss with the boss structure
Spacing between structure is 0.5 μm～2 μm.
Preferably, the efficient film crystal silicon solar battery also includes isolation channel, and the isolation channel is located at the base region
The boss structure is provided between the outside in domain, and the isolation channel and the adjacent base electrode.
Preferably, the base electrode is aluminium electrode, and the emitter electrode is silver electrode.
The present invention also provides a kind of autonomous energy integration chip based on efficient film crystal silicon solar battery, the autonomous energy
Source integrated chip at least includes：Efficient film crystal silicon solar battery and/or its array described in any one scheme as above,
In the SOI substrate；CMOS integrated circuits, positioned at the efficient film crystal silicon solar battery and/or its array side
In the SOI substrate or epitaxial layer；The CMOS integrated circuits are made up of CMOS transistor and its metal connection；Interconnection structure,
It is adapted to the electrode and solar cell and/or the electrode of its array of the CMOS integrated circuits；And isolation structure, positioned at phase
Between the adjacent CMOS transistor, between the adjacent CMOS transistor and efficient film crystal silicon solar battery and the adjacent height
In the top layer silicon between effect film crystal silicon solar battery, or between the adjacent CMOS transistor, described in adjacent
It is described and the adjacent efficient film crystal silicon solar battery between CMOS transistor and efficient film crystal silicon solar battery
In top layer silicon and the epitaxial layer.
Preferably, the CMOS integrated circuits include high-potential electrode and low-potential electrode；The efficient film crystal silicon is too
The base electrode of positive electricity pond and/or its array is connected with the high-potential electrode of the integrated circuit by the interconnection structure,
The emitter electrode of the efficient film crystal silicon solar battery and/or its array passes through the interconnection structure and the integrated circuit
Low-potential electrode be connected.
Preferably, the isolation structure is LOCOS isolation structures and/or STI isolation structures.
The present invention also provides a kind of preparation method of the autonomous energy integration chip based on efficient film crystal silicon solar battery,
At least comprise the following steps：
1) SOI substrate, the deposition mask layer in the SOI substrate, by photoetching and etching technics in the mask are provided
Extension window is defined on layer, and the silicon epitaxy layer and p-type of selective growth p-type high-dopant concentration are low successively in the extension window
The silicon epitaxy layer of doping content；
2) mask layer is removed, isolation structure is formed in the SOI substrate, the SOI is served as a contrast by the isolation structure
The efficient film crystal silicon solar battery region that bottom is isolated into CMOS integrated circuits region and is made up of the epitaxial layer；Described
CMOS integrated circuits are prepared in CMOS integrated circuits region, and while is formed in the efficient film crystal silicon solar battery region
The base region of battery；The CMOS integrated circuits include the CMOS transistor above the SOI substrate and parcel CMOS
The dielectric layer and the composition institute in the dielectric layer in integrated circuit region and the efficient film crystal silicon solar battery region
The high-potential electrode and low-potential electrode of CMOS integrated circuits are stated, the high-potential electrode and low-potential electrode are positioned at described efficient
Side of the film crystal silicon solar battery region away from the CMOS transistor；
3) etching removes the dielectric layer in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer, N-type non-crystalline silicon layer and transition nesa coating are sequentially depositing and form heterojunction structure；Institute
State, base region of the etch areas at least including solar cell；And etch removal
The intrinsic amorphous silicon layer, N beyond the efficient film crystal silicon solar battery emitter region and above the etch areas
Type amorphous silicon layer and transition nesa coating；
5) etching forms the lead window of the CMOS integrated circuits；
6) prepare base electrode and connect the metal of the base electrode and the high-potential electrode of the CMOS integrated circuits
Lead；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating；Deposition of transparent conductive film, and etch the removal efficient film crystal silicon too
The nesa coating beyond positive electricity pool area and above the etch areas；
9) prepare emitter electrode and connect the gold of the emitter electrode and the CMOS integrated circuits low-potential electrode
Category lead；
10) by step 9) obtained by structure carry out second annealing heat-treats.
Preferably, in step 4) in, the etch areas are also included on the outside of the base region of the solar cell
Isolation channel.
Preferably, the temperature of the first time annealing heat-treats is 350 DEG C～500 DEG C；Second annealing heat-treats
Temperature be 150 DEG C～350 DEG C.
Preferably, the thickness of the intrinsic amorphous silicon layer is 1nm～10nm, the thickness of the N-type non-crystalline silicon layer be 1nm～
10nm, the thickness of the transition nesa coating is 120nm～200nm, the thickness of the nesa coating be 60nm～
120nm。
Preferably, step 6) in the prepared base electrode be aluminium electrode, step 9) in the prepared transmitting
Pole electrode is silver electrode.
The present invention also provides a kind of preparation method of the autonomous energy integration chip based on efficient film crystal silicon solar battery,
At least comprise the following steps：
1) SOI substrate, the silicon epitaxy layer of growing P-type high-dopant concentration and p-type low-mix successively in the SOI substrate are provided
The silicon epitaxy layer of miscellaneous concentration；
2) form isolation structure in the SOI substrate and the epitaxial layer, the isolation structure by the SOI substrate and
The epitaxial layer is isolated into CMOS integrated circuits region and efficient film crystal silicon solar battery region；In the CMOS integrated circuits
CMOS integrated circuits are prepared in region, and while battery base region are formed in the efficient film crystal silicon solar battery region
Domain；The CMOS integrated circuits include CMOS transistor above the epitaxial layer and parcel CMOS integrated circuits region and
The dielectric layer in the efficient film crystal silicon solar battery region and the CMOS integrated circuits of the composition in the dielectric layer
High-potential electrode and low-potential electrode, the high-potential electrode and low-potential electrode are located at efficient film crystal silicon sun electricity
Side of the pool area away from the CMOS transistor；
3) etching removes the dielectric layer in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer, N-type non-crystalline silicon layer and transition nesa coating are sequentially depositing and form heterojunction structure；Institute
State, base region of the etch areas at least including solar cell；And etch removal
The intrinsic amorphous silicon layer, N beyond the efficient film crystal silicon solar battery emitter region and above the etch areas
Type amorphous silicon layer and transition nesa coating；
5) etching forms the lead window of the CMOS integrated circuits；
6) prepare base electrode and connect the metal of the base electrode and the high-potential electrode of the CMOS integrated circuits
Lead；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating；Deposition of transparent conductive film, and etch the removal efficient film crystal silicon too
The nesa coating beyond positive electricity pool area and above the etch areas；
9) prepare emitter electrode and connect the gold of the emitter electrode and the CMOS integrated circuits low-potential electrode
Category lead；
10) by step 9) obtained by structure carry out second annealing heat-treats.
Preferably, in step 4) in, the etch areas are also included on the outside of the base region of the solar cell
Isolation channel.
Preferably, the temperature of the first time annealing heat-treats is 350 DEG C～500 DEG C；Second annealing heat-treats
Temperature be 150 DEG C～350 DEG C.
Preferably, the thickness of the intrinsic amorphous silicon layer is 1nm～10nm, the thickness of the N-type non-crystalline silicon layer be 1nm～
10nm, the thickness of the transition nesa coating is 120nm～200nm, the thickness of the nesa coating be 60nm～
120nm。
Preferably, step 6) in the prepared base electrode be aluminium electrode, step 9) in the prepared transmitting
Pole electrode is silver electrode.
As described above, the efficient film crystal silicon solar battery of the present invention and its autonomous power chip integrated technology, with
Lower beneficial effect：The present invention proposes the preparation side of a kind of efficient film crystal silicon solar battery and its autonomous energy integration chip
Method, the process employs silicon thin film epitaxy technology, and overcoming CMOS integrated circuits and solar cell will to silicon materials doping content
Ask the silicon epitaxy layer of the contradiction between difference, p-type high-dopant concentration play back surface field passivation；Using intrinsic amorphous silicon layer/N
Type amorphous silicon layer/nesa coating heterojunction structure, improves open-circuit voltage and conversion efficiency, is conducive to improving chip significant surface
Product and integrated level；Passivation and the optical characteristics of oxygen buried layer in SOI materials is make use of, film crystal silicon solar battery can be improved
Energy；Meanwhile, it is formed at the solar cell on SOI top material layer silicon and avoids IC chip substrate thinning work in a package
The impact of skill.The efficient film solar cell that the autonomous power chip that the method is realized is prepared based on above-mentioned technology, makes full use of
Between the idle space in integrated circuit layout, particularly metal pad (pad) and metal pad (pad), circuit is to scribing trough rim
Edge location arrangements design some solar cells and/or array, can be that low-power consumption (LP) and super low-power consumption (ULP) provide power supply and supply
Give；The chip make use of the good isolation characteristics of SOI, can avoid crosstalk of the solar cell to integrated circuit (ICs).This is integrated
In technology, ITO technologies twice are employed, overcome impact of the high-temperature heat treatment to solar cell performance, particularly open-circuit voltage.
The preparation method of the present invention has compatibility with CMOS technology, it is adaptable to large-scale industrial production.
Description of the drawings
Fig. 1 is shown as the vertical section structure of the efficient film crystal silicon solar battery provided in embodiments of the invention one and shows
It is intended to.
Fig. 2 is shown as the plan structure of the efficient film crystal silicon solar battery provided in embodiments of the invention one and illustrates
Figure.
Fig. 3 is shown as the flow process of the efficient film crystal silicon solar battery preparation method provided in embodiments of the invention one
Figure.
The efficient film crystal silicon solar battery preparation method that Fig. 4 to Fig. 9 is shown as provided in the embodiment of the present invention one is each
Cross section structure schematic diagram in individual step.
Figure 10 is shown as carving in the efficient film crystal silicon solar battery preparation method provided in embodiments of the invention two
The later vertical section structure schematic diagram of erosion area of isolation.
Figure 11 is shown as the vertical section structure of the efficient film crystal silicon solar battery provided in embodiments of the invention two
Schematic diagram.
Figure 12 is shown as the plan structure of the efficient film crystal silicon solar battery provided in embodiments of the invention two and shows
It is intended to.
Figure 13 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention three
The Longitudinal cross section schematic of source integrated chip.
Figure 14 is shown as in embodiments of the invention three the autonomous energy integration core based on efficient film crystal silicon solar battery
Efficient film crystal silicon solar battery and/or its array and integrated circuit electrode connection diagram in piece.
Figure 15 is shown as in embodiments of the invention three the autonomous energy integration core based on efficient film crystal silicon solar battery
The plane figure schematic diagram of piece.
Figure 16 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention three
The flow chart of source integrated chip preparation method.
Figure 17 to Figure 26 be shown as provided in the embodiment of the present invention three based on efficient film crystal silicon solar battery from
Cross section structure schematic diagram in main source of energy integrated chip each step.
Figure 27 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention four
The later vertical section structure schematic diagram of area of isolation is etched in the integrated chip of source.
Figure 28 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention four
The Longitudinal cross section schematic of source integrated chip.
Figure 29 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention five
The Longitudinal cross section schematic of source integrated chip.
Figure 30 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention five
The flow chart of source integrated chip preparation method.
Figure 31 to Figure 38 be shown as provided in the embodiment of the present invention five based on efficient film crystal silicon solar battery from
Cross section structure schematic diagram in main source of energy integrated chip each step.
Figure 39 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention six
The later vertical section structure schematic diagram of area of isolation is etched in the integrated chip of source.
Figure 40 is shown as the autonomous energy based on efficient film crystal silicon solar battery provided in embodiments of the invention six
The Longitudinal cross section schematic of source integrated chip.
Component label instructions
1 efficient film crystal silicon solar battery
10 SOI substrates
101 backing bottoms
102 oxygen buried layers
103 top layer silicons
The silicon epitaxy layer of 11 p-type high-dopant concentrations
The silicon epitaxy layer of 12 p-type low doping concentrations
13 emitter layers
130 intrinsic amorphous silicon layers
131 N-type non-crystalline silicon layers
132 transition nesa coatings
133 nesa coatings
14 base regions
141 base region grooves
15 isolation channels
16 base electrodes
17 emitter electrodes
2 CMOS transistors
The metal lead wire of 31 CMOS integrated circuit high-potential electrodes
The metal lead wire of 32 CMOS integrated circuit low-potential electrodes
4 isolation structures
The high-potential electrode of 5 CMOS integrated circuits
The low-potential electrode of 6 CMOS integrated circuits
7 mask layers
71 first mask layers
72 second mask layers
73 extension windows
8 dielectric layers
81 first medium layers
82 second dielectric layer
83 lead windows
9 metal pads
The spacing of d base electrodes and boss structure
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Refer to Fig. 1 to Figure 40.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though the component relevant with the present invention is only shown in schema rather than according to package count during actual enforcement
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each component, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
Embodiment one
Fig. 1 is referred to, the present invention provides a kind of efficient film crystal silicon solar battery, the efficient film crystal silicon solar battery
At least include：SOI substrate 10, includes backing bottom 101, oxygen buried layer 102 and top layer silicon 103 from the bottom to top successively；Epitaxial layer, including
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of p-type high-dopant concentration；Outside the silicon of the p-type high-dopant concentration
Prolong layer 11 positioned at the upper surface of the top layer silicon 103, the silicon epitaxy layer 12 of the p-type low doping concentration is highly doped positioned at the p-type
The upper surface of the silicon epitaxy layer 11 of miscellaneous concentration；Emitter layer 13, be convexly equipped in the p-type low doping concentration silicon epitaxy layer 12 it is upper
Surface；Groove, at least including base region groove 141；The groove runs through the emitter layer 13, and the bottom of the groove can
With in the silicon epitaxy layer 12 of the p-type low doping concentration or extend to the p-type high-dopant concentration silicon epitaxy layer 11 on
Surface；The silicon epitaxy layer 12 of the emitter layer 13 and the p-type low doping concentration is divided into low by the p-type by the groove
Outside boss structure that the silicon epitaxy layer 12 of doping content is stacked with the emitter layer 13 or the silicon by the p-type high-dopant concentration
Prolong layer 11, the boss structure that the silicon epitaxy layer 12 of the p-type low doping concentration is stacked with the emitter layer 13；Base electrode
16, positioned at the bottom of the base region groove 141；Emitter electrode 17, positioned at the emitter layer of the boss structure
On 13.Preferably, in the present embodiment, the groove runs through the emitter layer 13, and the bottom of the groove extends to the p-type
11 upper surface of silicon epitaxy layer of high-dopant concentration；The groove is by the emitter layer 13 and the silicon of the p-type low doping concentration
Epitaxial layer 12 be divided into by the silicon epitaxy layer 11 of the p-type high-dopant concentration, the silicon epitaxy layer 12 of the p-type low doping concentration with
The boss structure of the stacking of the emitter layer 13, as shown in Figure 1.
Specifically, the thickness of the top layer silicon 103 is 20nm～200nm, the thickness of the oxygen buried layer 102 is 200～
500nm；The backing bottom 101 is silicon substrate, ceramic substrate or Sapphire Substrate.Preferably, in the present embodiment, the backing bottom
101 is silicon substrate.
Specifically, the material of the epitaxial layer is monocrystalline silicon and/or polysilicon, it is preferable that in the present embodiment, the extension
The material of layer is monocrystalline silicon；The thickness of the silicon epitaxy layer 11 of the p-type high-dopant concentration is 0.05 μm～2 μm, p-type element doping
Concentration be 5 × 1017～5 × 1019cm-3；The thickness of the silicon epitaxy layer 12 of the p-type low doping concentration is 1 μm～50 μm, p-type
The concentration of element doping is 5 × 1015～5 × 1017cm-3。
Specifically, the emitter layer 13 can be the knot of the N-type silicon layer and silicon nitride passivation composition of high-dopant concentration
Structure, or tie including intrinsic amorphous silicon (i_ а-Si) layer 130/N type non-crystalline silicons (N_ а-Si) 131/ nesa coating 133 of layer
The heterojunction structure of structure；Preferably, in the present embodiment, the emitter layer 13 is to include intrinsic amorphous silicon layer 130/N type amorphous
The heterojunction structure of 131/ nesa coating of silicon layer, 133 structure.Wherein, the thickness of the intrinsic amorphous silicon layer 130 be 1nm～
10nm, the thickness of the N-type non-crystalline silicon layer 131 is 1nm～10nm, the thickness of the nesa coating 133 be 60nm～
120nm。
Fig. 2 is referred to, the base electrode 16 constitutes mesa structure, the base electrode 16 and institute with the boss structure
It is 5 μm～200 μm to state spacing d between boss structure.
Fig. 3 to Fig. 9 is referred to, a kind of preparation method of efficient film crystal silicon solar battery, institute are also provided in the present embodiment
State efficient film crystal silicon solar battery at least to comprise the following steps：At least comprise the following steps：
1) SOI substrate 10 is provided, the SOI substrate 10 includes backing bottom 101,102 and of oxygen buried layer from the bottom to top successively
Top layer silicon 103；
2) silicon epitaxy layer 11 and p-type low doping concentration of p-type high-dopant concentration are sequentially formed in the top layer silicon 103
Silicon epitaxy layer 12；
3) the formation emitter layer 13 on the silicon epitaxy layer 12 of the p-type low doping concentration；
4) etch areas are defined on the emitter layer 13, the etch areas is performed etching to form groove, institute
Stating groove at least includes base region groove 141；The groove runs through the emitter layer 13, and the bottom of the groove is located at institute
State in the silicon epitaxy layer 12 of p-type low doping concentration or extend to 11 upper surface of silicon epitaxy layer of the p-type high-dopant concentration；It is described
Groove is divided into the silicon epitaxy layer 12 of the emitter layer 13 and the p-type low doping concentration by the p-type low doping concentration
The boss structure that stacks with the emitter layer 13 of silicon epitaxy layer 12 or the silicon epitaxy layer 11 by the p-type high-dopant concentration,
The boss structure that the silicon epitaxy layer 12 of p-type ground doping content is stacked with the emitter layer 13；
5) base electrode 16 is prepared in the bottom of the base region groove 141；
6) emitter electrode 17 is prepared on the emitter layer 13 of the boss structure；
7) by step 6) obtained by structure carry out annealing heat-treats.
In step 1) in, refer to S1 steps and the Fig. 4 in Fig. 3, there is provided a SOI substrate 10, the SOI substrate 10 is by under
It is supreme to include backing bottom 101, oxygen buried layer 102 and top layer silicon 103 successively.The thickness of the top layer silicon 103 is 20nm～200nm,
The thickness of the oxygen buried layer 102 is 200～500nm；The backing bottom 101 is silicon substrate, ceramic substrate or Sapphire Substrate.It is excellent
Selection of land, in the present embodiment, the backing bottom 101 is silicon substrate.
In step 2) in, the S2 and Fig. 5 in Fig. 3 is referred to, p-type is sequentially formed in the top layer silicon 103 highly doped dense
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of degree.
Specifically, the extension life in the top layer silicon 103 of physical vaporous deposition or chemical vapour deposition technique can be adopted
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of the length p-type high-dopant concentration.Preferably, in the present embodiment,
Using chemical vapour deposition technique p-type high-dopant concentration described in 103 Epitaxial growth of the top layer silicon silicon epitaxy layer 11 and p-type
The silicon epitaxy layer 12 of low doping concentration.The silicon epitaxy layer of the silicon epitaxy layer 11 and p-type low doping concentration of the p-type high-dopant concentration
12 material is monocrystalline silicon and/or polysilicon；The thickness of the silicon epitaxy layer 11 of the p-type high-dopant concentration is 0.05 μm～2 μ
M, the concentration of p-type element doping is 5 × 1017～5 × 1019cm-3；The thickness of the silicon epitaxy layer 12 of the p-type low doping concentration is
1 μm～50 μm, the concentration of p-type element doping is 5 × 1015～5 × 1017cm-3。
In step 3) in, S3 steps and the Fig. 6 in Fig. 3 is referred to, on the silicon epitaxy layer 12 of the p-type low doping concentration
Form emitter layer 13.
Specifically, the emitter layer 13 can be the knot of the N-type silicon layer and silicon nitride passivation composition of high-dopant concentration
Structure.Now, prepare emitter layer 13 on the silicon epitaxy layer 12 of the p-type low doping concentration to comprise the following steps：
31) height is formed on the silicon epitaxy layer 12 of the p-type low doping concentration using ion implanting or ion diffusion technique
The N-type silicon layer of doping content；Doped chemical is P elements；
32) using PECVD (plasma enhanced chemical vapor deposition method) techniques the high-dopant concentration N-type silicon layer
Upper formation silicon nitride passivation.
Specifically, the emitter layer 13 can also be to include that intrinsic amorphous silicon layer 130/N type amorphous silicon layer 131/ is transparent
The heterojunction structure of 133 structure of conducting film.Now, emitter layer is prepared on the silicon epitaxy layer 12 of the p-type low doping concentration
Comprise the following steps：
31) intrinsic amorphous silicon layer is formed successively on the silicon epitaxy layer 12 of the p-type low doping concentration using pecvd process
130 and N-type non-crystalline silicon layer 131；
32) transparent leading is formed in the N-type non-crystalline silicon layer 131 using sputtering or reaction and plasma deposition (RPD) technique
Electrolemma 133, the nesa coating 133 are but are not limited only to ito film.
Specifically, the thickness of the intrinsic amorphous silicon layer 130 be 1nm～10nm, the thickness of the N-type non-crystalline silicon layer 131
For 1nm～10nm, the thickness of the nesa coating 133 is 60nm～120nm.
In step 4) in, S4 steps and the Fig. 7 in Fig. 3 is referred to, etch areas are defined on the emitter layer 13, it is right
The etch areas are performed etching to form groove, and the groove at least includes base region groove 141；The groove runs through institute
Emitter layer 13 is stated, the bottom of the groove is located in the silicon epitaxy layer 12 of the p-type low doping concentration or extends to the p-type
11 upper surface of silicon epitaxy layer of high-dopant concentration；The groove is by the emitter layer 13 and the silicon of the p-type low doping concentration
Epitaxial layer 12 be divided into the boss structure that stacked with the emitter layer 13 by the silicon epitaxy layer 12 of the p-type low doping concentration or
By the silicon epitaxy layer 11 of the p-type high-dopant concentration, the silicon epitaxy layer 12 of p-type ground doping content and the emitter layer 13
The boss structure of stacking.
Specifically, can adopt what wet-etching technology, dry etch process or wet etching and dry etching combined
Technique etches groove in the etch areas.In the present embodiment, using wet-etching technology, electrochemical corrosive process or
RIE dry etch process removes the nesa coating 133 in the emitter layer 13, is made in the wet-etching technology
Etchant solution is dilution HCl solution, and it is 5% that the etchant solution used in the electrochemical corrosive process is mass fraction
～15% NaOH solution.
In step 5) in, S5 steps and the Fig. 8 in Fig. 3 is referred to, and base is prepared in the bottom of the base region groove 141
Pole electrode 16.
Specifically, the base is prepared in the channel bottom of the base region 14 using serigraphy or evaporation process
Pole electrode 16.In the present embodiment, the base electrode 16 is but is not limited only to aluminium electrode.
In step 6) in, S6 steps and the Fig. 9 in Fig. 3 is referred to, on the emitter layer 13 of the boss structure
Prepare emitter electrode 17.
Specifically, prepared on the emitter layer 13 of the boss structure using serigraphy or evaporation process described
Emitter electrode 17.In the present embodiment, the emitter electrode 17 is but is not limited only to silver electrode.
In step 7) in, refer to the S7 steps of Fig. 3, by step 6) obtained by structure carry out annealing heat-treats.
Specifically, the annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, the temperature of the annealing heat-treats
For 150 DEG C～350 DEG C.
Embodiment two
Figure 10 is referred to, a kind of preparation method of efficient film crystal silicon solar battery, the method are also provided in the present embodiment
Essentially identical with the preparation method described in embodiment one, the difference of the two is mainly in step 4) in, in the present embodiment, step 4)
In groove not only include base region groove 141, also including isolation channel 15.Execution step 4) when, while forming the base
Pole region trenches 141 and the isolation channel 15 on the outside of the base region groove 141.
Figure 11 is referred to, a kind of efficient film crystal silicon solar battery is also provided in the present embodiment, it is described in the present embodiment
Efficient film crystal silicon solar battery is roughly the same with the structure of the efficient film crystal silicon solar battery in embodiment one, the two
Difference be, in the present embodiment, to be additionally provided with isolation channel 15, the isolation channel 15 in the outside of the base region groove 141
Positioned at the outside of all base region grooves 141.
Figure 12 is referred to, in the present embodiment, the base electrode 16 constitutes pectinate texture, the base with the boss structure
Spacing d between pole electrode 16 and the boss structure is 0.5 μm～2 μm.
Embodiment three
Figure 13 is referred to, the present embodiment provides a kind of autonomous energy integration core based on efficient film crystal silicon solar battery
Piece, the autonomous energy integration chip at least include：The efficient film crystal silicon sun as described in any one of embodiment one scheme
Battery 1 and/or its array, in the SOI substrate 10；CMOS integrated circuits, positioned at efficient film crystal silicon sun electricity
In the SOI substrate 10 of pond 1 and/or its array side；The CMOS integrated circuits are by the CMOS transistor and its metal
Connection composition；Interconnection structure, is adapted to the electrode and solar cell and/or the electrode of its array of the CMOS integrated circuits；
And isolation structure 4, between the adjacent CMOS integrated circuits, the adjacent CMOS integrated circuits and efficient film crystal silicon
In the top layer silicon 103 between solar cell 1 and between the adjacent efficient film crystal silicon solar battery 1.
Specifically, the CMOS integrated circuits include above the SOI substrate 10 and wrap up CMOS transistor 2 and institute
State the dielectric layer 8 and the high electricity of the CMOS integrated circuits in the dielectric layer 8 in efficient film crystal silicon solar battery region
Position electrode 5 and low-potential electrode 6；The dielectric layer 8 includes first medium layer 81 and second dielectric layer 82, the high-potential electrode
5 and low-potential electrode 6 be located at the efficient film crystal silicon solar battery region away from the CMOS transistor 2 side.
Specifically, the isolation structure 4 can be LOCOD isolation structures and/or STI isolation structures.
The base electrode 16 of Figure 14, the efficient film crystal silicon solar battery 1 and/or its array is referred to by described mutual
Link structure to be connected with the high-potential electrode (GND) of the integrated circuit；The efficient film crystal silicon solar battery 1 and/or its
The emitter electrode 17 of array is connected with the low-potential electrode (VDD) of the integrated circuit by the interconnection structure.It is described
The area and quantity and the voltage for being provided, electric current of efficient film crystal silicon solar battery 1 and/or its array, can be according to integrated
The use needs of chip are designed.
Figure 15 is referred to, the efficient film crystal silicon solar battery 1 and/or its array are arranged in the integrated circuit layout
In idle space in, particularly between adjacent metal weld pad 9, the position of chip to scribing groove edge.
Refer to Figure 16 to Figure 26, the present embodiment also provide it is a kind of based on efficient film crystal silicon solar battery from main source of energy
The preparation method of integrated chip, the preparation method of the autonomous energy integration chip based on efficient film crystal silicon solar battery is extremely
Comprise the following steps less：
1) SOI substrate 10 is provided, mask layer 7 is sequentially depositing in the SOI substrate 10, is existed by photoetching and etching technics
Extension window 73 is defined on the mask layer 7, and in the silicon of 73 interior selective growth p-type high-dopant concentration successively of extension window
The silicon epitaxy layer 12 of epitaxial layer 11 and p-type low doping concentration；
2) mask layer 7 being removed, isolation structure 4 being formed in the SOI substrate 10, the isolation structure 4 will be described
The efficient film crystal silicon solar battery region that SOI substrate 10 is isolated into CMOS integrated circuits region and is made up of the epitaxial layer；
CMOS integrated circuits are prepared in the CMOS integrated circuits region, and while in the efficient film crystal silicon solar battery region
Interior formation base region 14；The CMOS integrated circuits include above the SOI substrate 10 and wrap up 2 He of CMOS transistor
The dielectric layer 8 in the efficient film crystal silicon solar battery region and the CMOS integrated circuits in the dielectric layer 8
High-potential electrode 5 and low-potential electrode 6, the high-potential electrode 5 and low-potential electrode 6 are located at the efficient film crystal silicon sun
Side of the cell area away from the CMOS transistor 2；
3) etching removes the dielectric layer 8 in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132 are sequentially depositing and form hetero-junctions
Structure；Etch areas, base region 14 of the etch areas for solar cell are defined on the heterojunction structure；And etch
The intrinsic amorphous silicon layer 130, N beyond removing the efficient film crystal silicon solar battery region and above the etch areas
Type amorphous silicon layer 131 and transition nesa coating 132；
5) etching forms the lead window 83 of the CMOS integrated circuits；
6) prepare base electrode 16 and connect the base electrode 16 and the high-potential electrode 5 of the CMOS integrated circuits
Metal lead wire 31；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating 132；Deposition of transparent conductive film 133, and etch the removal efficient film
The nesa coating 133 beyond crystal silicon solar battery region and above the etch areas；
9) prepare emitter electrode 17 and connect the electronegative potential electricity of the emitter electrode 17 and the CMOS integrated circuits
The metal lead wire 32 of pole 6；
10) by step 9) obtained by structure carry out second annealing heat-treats.
In step 1) in, refer to the S1 steps and Figure 17 to Figure 19 of Figure 16, there is provided SOI substrate 10, in the SOI substrate
Mask layer 7 is sequentially depositing on 10, extension window 73 is defined on the mask layer 7 by photoetching and etching technics, and outside
Prolong the silicon epitaxy layer 12 of the 73 interior silicon epitaxy layer 11 and p-type low doping concentration of selective growth p-type high-dopant concentration successively of window.
Specifically, refer to Figure 17, there is provided a SOI substrate 10, the SOI substrate 10 includes backing bottom from the bottom to top successively
101st, oxygen buried layer 102 and top layer silicon 103.The thickness of the top layer silicon 103 be 20nm～200nm, the thickness of the oxygen buried layer 102
For 200～500nm；The backing bottom 101 is silicon substrate, ceramic substrate or Sapphire Substrate.Preferably, in the present embodiment, institute
Backing bottom 101 is stated for silicon substrate.
Specifically, Figure 18 is referred to, mask layer 7 is sequentially depositing in the SOI substrate 10, by photoetching and etching technics
Extension window 73 is defined on the mask layer 7.The mask layer 7 can be individual layer, or double-deck or multilayer.It is preferred that
Ground, in the present embodiment, the mask layer 7 is double-decker, including the first mask layer 71 and the second mask layer 72, and described first covers
Film layer 71 is SiO2Layer, second mask layer 72 are SiN layer.Specifically, the extension window 73 is corresponding to described efficiently thin
Film crystal silicon solar battery region.
Specifically, the extension life in the top layer silicon 103 of physical vaporous deposition or chemical vapour deposition technique can be adopted
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of the length p-type high-dopant concentration.Preferably, in the present embodiment,
Using chemical vapour deposition technique p-type high-dopant concentration described in 103 Epitaxial growth of the top layer silicon silicon epitaxy layer 11 and p-type
The silicon epitaxy layer 12 of low doping concentration.The silicon epitaxy layer of the silicon epitaxy layer 11 and p-type low doping concentration of the p-type high-dopant concentration
12 material is monocrystalline silicon and/or polysilicon；The thickness of the silicon epitaxy layer 11 of the p-type high-dopant concentration is 0.05 μm～2 μ
M, the concentration of p-type element doping is 5 × 1017～5 × 1019cm-3；The thickness of the silicon epitaxy layer 12 of the p-type low doping concentration is
1 μm～50 μm, the concentration of p-type element doping is 5 × 1015～5 × 1017cm-3。
In step 2) in, the S2 steps and Figure 20 to Figure 21 of Figure 16 are referred to, the mask layer 7 is removed, is served as a contrast in the SOI
Isolation structure 4 is formed in bottom 10, the SOI substrate 10 is isolated into CMOS integrated circuits region and by institute by the isolation structure 4
State the efficient film crystal silicon solar battery region of epitaxial layer composition；The integrated electricity of CMOS is prepared in the CMOS integrated circuits region
Road, and while base region 14 is formed in the efficient film crystal silicon solar battery region；The CMOS integrated circuits include
Above the SOI substrate 10 and wrap up the dielectric layer 8 in CMOS transistor 2 and the efficient film crystal silicon solar battery region
With the high-potential electrode 5 and low-potential electrode 6 of the CMOS integrated circuits in the dielectric layer 8, the high potential electricity
Pole 5 and low-potential electrode 6 are located at side of the efficient film crystal silicon solar battery region away from the CMOS transistor 2.
Specifically, Figure 20 is referred to, the mask layer 7 is removed.Can using wet-etching technology, dry etch process,
The technique that wet etching and dry etching combine removes the mask layer 7.
Specifically, the isolation structure 4 can be LOCOS isolation structures, or STI isolation structures, can also be
The combination of LOCOS isolation structures and STI isolation structures.
Specifically, Figure 21 being referred to, isolation structure 4 being formed in the SOI substrate 10, the isolation structure 4 will be described
The efficient film crystal silicon solar battery region that SOI substrate 10 is isolated into CMOS integrated circuits region and is made up of the epitaxial layer；
CMOS integrated circuits are prepared in the CMOS integrated circuits region, and while in the efficient film crystal silicon solar battery region
Interior formation base region 14.The CMOS transistor 2 can be PMOS transistor, or nmos pass transistor, can also be same
When include PMOS transistor and nmos pass transistor.
Specifically, the dielectric layer 8 can be single layer structure, or double-deck or sandwich construction.Preferably, this enforcement
In example, the dielectric layer 8 is double-decker, including first medium layer 81 and second dielectric layer 82；81, the first medium layer
In the upper surface of the SOI substrate 10, the second dielectric layer 82 is located at the upper surface of the first medium layer 81；Described first
Dielectric layer 81 is SiO2Layer, the second dielectric layer 82 are SiN layer.The CMOS transistor 2 and the CMOS integrated circuits
High-potential electrode 5 and low-potential electrode 6 are respectively positioned in the first medium layer 81.
Specifically, in the present embodiment, when the source drain region of the PMOS transistor is prepared, while forming the height
The base region 14 in effect film crystal silicon solar battery region.Doped ions in the base region 14 are B+Or BF2 +。
In step 3) in, the S3 steps and Figure 22 of Figure 16 are referred to, etching removes the efficient film crystal silicon solar battery
The dielectric layer 8 in region.
Specifically, the efficient film crystal silicon solar battery area can be removed using existing semiconductor etching process etching
The dielectric layer 8 in domain, specific method are, known to insider, to be not repeated herein.
In step 4) in, the S4 steps and Figure 23 of Figure 16 are referred to, intrinsic amorphous silicon layer 130, N-type non-crystalline silicon is sequentially depositing
Layer 131 and transition nesa coating 132 form heterojunction structure；Etch areas, the quarter are defined on the heterojunction structure
Base region 14 of the erosion region for solar cell；And it is beyond etching the removal efficient film crystal silicon solar battery region and described
The intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132 above etch areas.
Specifically, intrinsic amorphous is formed successively on the silicon epitaxy layer 12 of the p-type low doping concentration using pecvd process
Silicon layer 130 and N-type non-crystalline silicon layer 131；(RPD) technique is deposited in the N-type non-crystalline silicon layer 131 using sputtering or reaction and plasma
Upper formation transition nesa coating 132, the transition nesa coating 132 can be but be not limited only to ito film.It is described intrinsic non-
The thickness of crystal silicon layer 130 is 1nm～10nm, and the thickness of the N-type non-crystalline silicon layer 131 is 1nm～10nm, and the transition is transparent to be led
The thickness of electrolemma 132 is 120nm～200nm.
Specifically, can adopt what wet-etching technology, dry etch process or wet etching and dry etching combined
Technique etches groove in the etch areas.In the present embodiment, using wet-etching technology, electrochemical corrosive process or
RIE dry etch process removes the nesa coating 133 in the etch areas, used in the wet-etching technology
Etchant solution for dilution HCl solution, the etchant solution used in the electrochemical corrosive process be mass fraction be 5%～
15% NaOH solution.
Specifically, beyond etching removes the efficient film crystal silicon solar battery region and above the etch areas
During the intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132, to remove covering completely
The intrinsic amorphous silicon layer 130, N-type beyond the efficient film crystal silicon solar battery region and above the etch areas
Amorphous silicon layer 131 and transition nesa coating 132 terminate for etching, after the completion of etching, completely reveal the base region 14.
In step 5) in, the S5 steps and Figure 24 of Figure 16 are referred to, in the high potential electricity of the CMOS integrated circuits
Pole 5 and 6 corresponding position of the low-potential electrode perform etching, to form the lead window 83 of the CMOS integrated circuits.
Specifically, in etching process, while to the high-potential electrode 5 and electronegative potential by the CMOS integrated circuits
The region that electrode 6 is located performs etching, while formed completely revealing the described of the high-potential electrode 5 and low-potential electrode 6
Lead window 83.
In step 6) in, the S6 steps and Figure 25 of Figure 16 are referred to, base electrode 16 and the connection base electrode is prepared
16 with the metal lead wire 31 of the high-potential electrode 5 of the CMOS integrated circuits.
Specifically, institute is prepared using serigraphy or evaporation process in the base region 14 of the base region 14
Base electrode 16 is stated, and while forms the gold of the connection base electrode 16 and the high-potential electrode 5 of the CMOS integrated circuits
Category lead 31.In the present embodiment, the metal lead wire 31 of the high-potential electrode 5 of the base electrode 16 and the CMOS integrated circuits
Material be but be not limited only to aluminium.
In step 7) in, refer to the S7 steps of Figure 16, by step 6) obtained by structure carry out annealing for the first time at heat
Reason.
Specifically, the first time annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, the first time annealing
The temperature of heat treatment is 350 DEG C～500 DEG C.By the first time annealing heat-treats, the CMOS integrated circuits can be completed
With the electrode metal of the base electrode 16.
In step 8) in, the S8 steps of Figure 16 are referred to, the transition nesa coating 132 is removed；Deposition electrically conducting transparent
Film 133, and it is described transparent beyond etching the removal efficient film crystal silicon solar battery region and above the etch areas
Conducting film 133.
As, after the first time annealing heat-treats are completed, the first time annealing heat-treats can be saturating to the transition
The performance of bright conducting film 132 has undesirable effect, and then can affect the performance of the efficient film crystal silicon solar battery.Therefore,
After the first time annealing heat-treats are completed, need to remove the transition nesa coating 132；Redeposited electrically conducting transparent
Film 133, and it is described beyond etching the removal efficient film crystal silicon solar battery region and above the base region 14
Bright conducting film 133.The nesa coating 133 is but is not limited only to ito film.The thickness of the nesa coating 133 is 60nm
～120nm.
In step 9) in, the S9 steps and Figure 26 of Figure 16 are referred to, emitter electrode 17 and the connection emitter stage is prepared
The metal lead wire 32 of electrode 17 and the low-potential electrode 6 of the CMOS integrated circuits.
Specifically, the emitter electrode 17 is prepared on the emitter layer 13 using serigraphy or evaporation process,
And while form the metal lead wire 32 of the connection emitter electrode 17 and the low-potential electrode 6 of the CMOS integrated circuits.This
In embodiment, the material of the metal lead wire 32 of the low-potential electrode 6 of the emitter electrode 17 and the CMOS integrated circuits is equal
For but be not limited only to silver.
In step 10) in, refer to the S10 steps of Figure 16, by step 9) obtained by structure carry out second annealing heat
Process.
Specifically, second annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, anneal for described second
The temperature of heat treatment is 150 DEG C～350 DEG C.By second annealing heat-treats, it is possible to achieve the emitter electrode 17
With the good contact of the emitter layer 13.
Example IV
Figure 27 is referred to, a kind of autonomous energy integration based on efficient film crystal silicon solar battery is also provided in the present embodiment
The preparation method of chip, the method are essentially identical with the preparation method described in embodiment three, and the difference of the two is mainly in step
4) in, in the present embodiment, step 4) in etch areas not only include base region 14, also including 15 region of isolation channel.In step
It is rapid 4) complete after, while forming the base region 14 and the isolation channel 15 on the outside of the base region 14.
Figure 28 is referred to, a kind of autonomous energy integration based on efficient film crystal silicon solar battery is also provided in the present embodiment
In chip, the autonomous energy integration chip based on efficient film crystal silicon solar battery in the present embodiment and embodiment three
The structure of the autonomous energy integration chip based on efficient film crystal silicon solar battery is roughly the same, and the difference of the two is,
In the present embodiment, the efficient film crystal silicon solar battery be the efficient film crystal silicon of any one of embodiment two described in scheme too
Positive electricity pond；Isolation channel 15 is additionally provided with the outside of the base region groove 141 of the efficient film crystal silicon solar battery,
The isolation channel 15 is located at the outside of all base region grooves 141.
Embodiment five
Figure 29 is referred to, the present embodiment provides a kind of autonomous energy integration core based on efficient film crystal silicon solar battery
Piece, the autonomous energy integration chip at least include：The efficient film crystal silicon sun as described in any one of embodiment one scheme
Battery 1 and/or its array, in the SOI substrate 10；CMOS integrated circuits, positioned at efficient film crystal silicon sun electricity
On the epitaxial layer of pond 1 and/or its array side；The CMOS integrated circuits are connected by the CMOS transistor and its metal
Composition；Interconnection structure, is adapted to the electrode and solar cell and/or the electrode of its array of the CMOS integrated circuits；And
Isolation structure 4, between the adjacent CMOS integrated circuits, the adjacent CMOS integrated circuits and the efficient film crystal silicon sun
In the top layer silicon 103 between battery 1 and between the adjacent efficient film crystal silicon solar battery 1 and the epitaxial layer.
Specifically, the CMOS integrated circuits include above the epitaxial layer and wrap up CMOS transistor 2 and described
The height electricity of the dielectric layer 8 in efficient film crystal silicon solar battery region and the CMOS integrated circuits in the dielectric layer 8
Position electrode 5 and low-potential electrode 6；The dielectric layer 8 includes first medium layer 81 and second dielectric layer 82, the high-potential electrode
5 and low-potential electrode 6 be located at the efficient film crystal silicon solar battery region away from the CMOS transistor 2 side.
Specifically, the isolation structure 4 can be LOCOD isolation structures and/or STI isolation structures.
Pass through institute please continue to refer to the base electrode 16 of Figure 14, the efficient film crystal silicon solar battery 1 and/or its array
State interconnection structure to be connected with the high-potential electrode (GND) of the integrated circuit；The efficient film crystal silicon solar battery 1 and/
Or the emitter electrode 17 of its array is connected with the low-potential electrode (VDD) of the integrated circuit by the interconnection structure.
The area and quantity and the voltage for being provided, electric current of the efficient film crystal silicon solar battery 1 and/or its array, can basis
The use needs of integrated chip are designed.
Please continue to refer to Figure 15, the efficient film crystal silicon solar battery 1 and/or its array are arranged in the integrated circuit
In idle space in layout, particularly between adjacent metal weld pad 9, the position of chip to scribing groove edge.
Refer to Figure 30 to Figure 38, the present embodiment also provide it is a kind of based on efficient film crystal silicon solar battery from main source of energy
The preparation method of integrated chip, the preparation method of the autonomous energy integration chip based on efficient film crystal silicon solar battery is extremely
Comprise the following steps less：
1) SOI substrate 10, the silicon epitaxy layer 11 and P of growing P-type high-dopant concentration successively in the SOI substrate 10 are provided
The silicon epitaxy layer 12 of type low doping concentration；
2) isolation structure 4 is formed in the SOI substrate 10 and the epitaxial layer, the SOI is served as a contrast by the isolation structure 4
Bottom 10 and the epitaxial layer are isolated into CMOS integrated circuits region and efficient film crystal silicon solar battery region；In the CMOS collection
CMOS integrated circuits are prepared in circuit region, and while base region are formed in the efficient film crystal silicon solar battery region
Domain 14；The CMOS integrated circuits include above the epitaxial layer and wrap up CMOS transistor 2 and the efficient film is brilliant
The dielectric layer 8 in silicon solar cell region and 5 He of high-potential electrode by the CMOS integrated circuits in the dielectric layer 8
Low-potential electrode 6, the high-potential electrode 5 and low-potential electrode 6 be located at the efficient film crystal silicon solar battery region away from
The side of the CMOS transistor 2；
3) etching removes the dielectric layer 8 in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132 are sequentially depositing and form hetero-junctions
Structure；Etch areas, base region 14 of the etch areas for solar cell are defined on the heterojunction structure；And etch
The intrinsic amorphous silicon layer 130, N beyond removing the efficient film crystal silicon solar battery region and above the etch areas
Type amorphous silicon layer 131 and transition nesa coating 132；
5) etching forms the lead window 83 of the CMOS integrated circuits；
6) prepare base electrode 16 and connect the base electrode 16 and the high-potential electrode 5 of the CMOS integrated circuits
Metal lead wire 31；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating 132；Deposition of transparent conductive film 133, and etch the removal efficient film
The nesa coating 133 beyond crystal silicon solar battery region and above the etch areas；
9) prepare emitter electrode 17 and connect the electronegative potential electricity of the emitter electrode 17 and the CMOS integrated circuits
The metal lead wire 32 of pole 6；
10) by step 9) obtained by structure carry out second annealing heat-treats.
In step 1) in, refer to the S1 steps and Figure 31 to Figure 32 of Figure 30, there is provided SOI substrate 10, in the SOI substrate
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of growing P-type high-dopant concentration successively on 10.
Specifically, refer to Figure 31, there is provided a SOI substrate 10, the SOI substrate 10 includes backing bottom from the bottom to top successively
101st, oxygen buried layer 102 and top layer silicon 103.The thickness of the top layer silicon 103 be 20nm～200nm, the thickness of the oxygen buried layer 102
For 200～500nm；The backing bottom 101 is silicon substrate, ceramic substrate or Sapphire Substrate.Preferably, in the present embodiment, institute
Backing bottom 101 is stated for silicon substrate.
Specifically, Figure 32 is referred to, physical vaporous deposition or chemical vapour deposition technique can be adopted in the top layer silicon
The silicon epitaxy layer 12 of the silicon epitaxy layer 11 and p-type low doping concentration of p-type high-dopant concentration described in 103 Epitaxial growths.Preferably,
In the present embodiment, using chemical vapour deposition technique outside the silicon of p-type high-dopant concentration described in 103 Epitaxial growth of the top layer silicon
Prolong the silicon epitaxy layer 12 of layer 11 and p-type low doping concentration.The silicon epitaxy layer 11 and p-type of the p-type high-dopant concentration is low-doped dense
The material of the silicon epitaxy layer 12 of degree is monocrystalline silicon and/or polysilicon；The thickness of the silicon epitaxy layer 11 of the p-type high-dopant concentration
For 0.05 μm～2 μm, the concentration of p-type element doping is 5 × 1017～5 × 1019cm-3；The silicon epitaxy of the p-type low doping concentration
The thickness of layer 12 is 1 μm～50 μm, and the concentration of p-type element doping is 5 × 1015～5 × 1017cm-3。
In step 2) in, the S2 steps and Figure 33 of Figure 30 are referred to, is formed in the SOI substrate 10 and the epitaxial layer
The SOI substrate 10 and the epitaxial layer are isolated into CMOS integrated circuits region and height by isolation structure 4, the isolation structure 4
Effect film crystal silicon solar battery region；CMOS integrated circuits are prepared in the CMOS integrated circuits region, and while described
Base region 14 is formed in efficient film crystal silicon solar battery region；The CMOS integrated circuits are included on the epitaxial layer
Side and wrap up the dielectric layer 8 in CMOS transistor 2 and the efficient film crystal silicon solar battery region and be located in the dielectric layer 8
The CMOS integrated circuits high-potential electrode 5 and low-potential electrode 6, the high-potential electrode 5 and low-potential electrode 6 are located at
Side of the efficient film crystal silicon solar battery region away from the CMOS transistor 2.
Specifically, the isolation structure 4 can be LOCOS isolation structures, or STI isolation structures, can also be
The combination of LOCOS isolation structures and STI isolation structures.
Specifically, Figure 33 is referred to, and isolation structure 4, the isolation is formed in the SOI substrate 10 and the epitaxial layer
The SOI substrate 10 and the epitaxial layer are isolated into CMOS integrated circuits region and efficient film crystal silicon solar battery by structure 4
Region；CMOS integrated circuits are prepared in the CMOS integrated circuits region, and while in efficient film crystal silicon sun electricity
Base region 14 is formed in pool area.The CMOS transistor 2 can be PMOS transistor, or nmos pass transistor, also
PMOS transistor and nmos pass transistor can be included simultaneously.
Specifically, the dielectric layer 8 can be single layer structure, or double-deck or sandwich construction.Preferably, this enforcement
In example, the dielectric layer 8 is double-decker, including first medium layer 81 and second dielectric layer 82；81, the first medium layer
In the upper surface of the SOI substrate 10, the second dielectric layer 82 is located at the upper surface of the first medium layer 81；Described first
Dielectric layer 81 is SiO2Layer, the second dielectric layer 82 are SiN layer.The CMOS transistor 2 and the CMOS integrated circuits
High-potential electrode 5 and low-potential electrode 6 are respectively positioned in the first medium layer 81.
Specifically, in the present embodiment, when the source drain region of the PMOS transistor is prepared, while forming the height
The base region 14 in effect film crystal silicon solar battery region.Doped ions in the base region 14 are B+Or BF2 +。
In step 3) in, the S3 steps and Figure 34 of Figure 30 are referred to, etching removes the efficient film crystal silicon solar battery
The dielectric layer 8 in region.
Specifically, the efficient film crystal silicon solar battery area can be removed using existing semiconductor etching process etching
The dielectric layer 8 in domain, specific method are, known to insider, to be not repeated herein.
In step 4) in, the S4 steps and Figure 35 of Figure 30 are referred to, intrinsic amorphous silicon layer 130, N-type non-crystalline silicon is sequentially depositing
Layer 131 and transition nesa coating 132 form heterojunction structure；Etch areas, the quarter are defined on the heterojunction structure
Base region 14 of the erosion region for solar cell；And it is beyond etching the removal efficient film crystal silicon solar battery region and described
The intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132 above etch areas.
Specifically, intrinsic amorphous is formed successively on the silicon epitaxy layer 12 of the p-type low doping concentration using pecvd process
Silicon layer 130 and N-type non-crystalline silicon layer 131；(RPD) technique is deposited in the N-type non-crystalline silicon layer 131 using sputtering or reaction and plasma
Upper formation transition nesa coating 132, the transition nesa coating 132 can be but be not limited only to ito film.It is described intrinsic non-
The thickness of crystal silicon layer 130 is 1nm～10nm, and the thickness of the N-type non-crystalline silicon layer 131 is 1nm～10nm, and the transition is transparent to be led
The thickness of electrolemma 132 is 120nm～200nm.
Specifically, can adopt what wet-etching technology, dry etch process or wet etching and dry etching combined
Technique etches groove in the etch areas.In the present embodiment, using wet-etching technology, electrochemical corrosive process or
RIE dry etch process removes the nesa coating 133 in the etch areas, used in the wet-etching technology
Etchant solution for dilution HCl solution, the etchant solution used in the electrochemical corrosive process be mass fraction be 5%～
15% NaOH solution.
Specifically, beyond etching removes the efficient film crystal silicon solar battery region and above the etch areas
During the intrinsic amorphous silicon layer 130, N-type non-crystalline silicon layer 131 and transition nesa coating 132, to remove covering completely
The intrinsic amorphous silicon layer 130, N-type beyond the efficient film crystal silicon solar battery region and above the etch areas
Amorphous silicon layer 131 and transition nesa coating 132 terminate for etching, after the completion of etching, completely reveal the base region 14.
In step 5) in, the S5 steps and Figure 36 of Figure 30 are referred to, in the high potential electricity of the CMOS integrated circuits
Pole 5 and 6 corresponding position of the low-potential electrode perform etching, to form the lead window 83 of the CMOS integrated circuits.
Specifically, in etching process, while to the high-potential electrode 5 and electronegative potential by the CMOS integrated circuits
The region that electrode 6 is located performs etching, while formed completely revealing the described of the high-potential electrode 5 and low-potential electrode 6
Lead window 83.
In step 6) in, the S6 steps and Figure 37 of Figure 30 are referred to, base electrode 16 and the connection base electrode is prepared
16 with the metal lead wire 31 of the high-potential electrode 5 of the CMOS integrated circuits.
Specifically, institute is prepared using serigraphy or evaporation process in the base region 14 of the base region 14
Base electrode 16 is stated, and while forms the gold of the connection base electrode 16 and the high-potential electrode 5 of the CMOS integrated circuits
Category lead 31.In the present embodiment, the metal lead wire 31 of the high-potential electrode 5 of the base electrode 16 and the CMOS integrated circuits
Material be but be not limited only to aluminium.
In step 7) in, refer to the S7 steps of Figure 30, by step 6) obtained by structure carry out annealing for the first time at heat
Reason.
Specifically, the first time annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, the first time annealing
The temperature of heat treatment is 350 DEG C～500 DEG C.By the first time annealing heat-treats, the CMOS integrated circuits can be completed
With the electrode metal of the base electrode 16.
It should be noted that after the first time annealing heat-treats are completed, the first time annealing heat-treats can be right
The performance of the transition nesa coating 132 has undesirable effect, and then can affect the efficient film crystal silicon solar battery
Performance.Therefore, after the first time annealing heat-treats are completed, in addition it is also necessary to remove the transition nesa coating 132；Again
Deposition of transparent conductive film 133, and beyond etching the removal efficient film crystal silicon solar battery region and the base region 14
The nesa coating 133 of top.The nesa coating 133 is but is not limited only to ito film.The nesa coating 133
Thickness be 60nm～120nm.
In step 8) in, the S8 steps of Figure 16 are referred to, the transition nesa coating 132 is removed；Deposition electrically conducting transparent
Film 133, and it is described transparent beyond etching the removal efficient film crystal silicon solar battery region and above the etch areas
Conducting film 133.
In step 9) in, the S9 steps and Figure 38 of Figure 30 are referred to, emitter electrode 17 and the connection emitter stage is prepared
The metal lead wire 32 of electrode 17 and the low-potential electrode 6 of the CMOS integrated circuits.
Specifically, the emitter electrode 17 is prepared on the emitter layer 13 using serigraphy or evaporation process,
And while form the metal lead wire 32 of the connection emitter electrode 17 and the low-potential electrode 6 of the CMOS integrated circuits.This
In embodiment, the material of the metal lead wire 32 of the low-potential electrode 6 of the emitter electrode 17 and the CMOS integrated circuits is equal
For but be not limited only to silver.
In step 10) in, refer to the S10 steps of Figure 30, by step 9) obtained by structure carry out second annealing heat
Process.
Specifically, second annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, anneal for described second
The temperature of heat treatment is 150 DEG C～350 DEG C.By second annealing heat-treats, it is possible to achieve the emitter electrode 17
With the good contact of the emitter layer 13.
Embodiment six
Figure 39 is referred to, a kind of autonomous energy integration based on efficient film crystal silicon solar battery is also provided in the present embodiment
The preparation method of chip, the method are essentially identical with the preparation method described in embodiment five, and the difference of the two is mainly in step
4) in, in the present embodiment, step 4) in etch areas not only include base region 14, also including 15 region of isolation channel.In step
It is rapid 4) complete after, while forming the base region 14 and the isolation channel 15 on the outside of the base region 14.
Figure 40 is referred to, a kind of autonomous energy integration based on efficient film crystal silicon solar battery is also provided in the present embodiment
In chip, the autonomous energy integration chip based on efficient film crystal silicon solar battery in the present embodiment and embodiment five
The structure of the autonomous energy integration chip based on efficient film crystal silicon solar battery is roughly the same, and the difference of the two is,
In the present embodiment, the efficient film crystal silicon solar battery be the efficient film crystal silicon of any one of embodiment two described in scheme too
Positive electricity pond；Isolation channel 15 is additionally provided with the outside of the base region groove 141 of the efficient film crystal silicon solar battery,
The isolation channel 15 is located at the outside of all base region grooves 141.
In sum, the present invention proposes the system of a kind of efficient film crystal silicon solar battery and its autonomous energy integration chip
Preparation Method, the process employs silicon thin film epitaxy technology, overcome CMOS integrated circuits and solar cell dense to silicon materials doping
Degree requires the contradiction between difference, and the silicon epitaxy layer of p-type high-dopant concentration can play back surface field passivation；Using intrinsic amorphous silicon
Layer/N-type non-crystalline silicon layer/nesa coating heterojunction structure, improves open-circuit voltage and conversion efficiency, is conducive to raising chip to have
Effect area and integrated level；Passivation and the optical characteristics of oxygen buried layer in SOI materials is make use of, film crystal silicon solar battery can be improved
Performance；Meanwhile, it is formed at the solar cell on SOI top material layer silicon and avoids IC chip substrate thinning in a package
The impact of technique.The efficient film solar cell that the autonomous power chip that the method is realized is prepared based on above-mentioned technology, fully profit
With between the idle space in integrated circuit layout, particularly metal pad (pad) and metal pad (pad), circuit is to scribe line
The some solar cells of marginal position layout design and/or array, can be that low-power consumption (LP) and super low-power consumption (ULP) provide power supply and supply
Give；The chip make use of the good isolation characteristics of SOI, can avoid crosstalk of the solar cell to integrated circuit (ICs).This is integrated
In technology, ITO technologies twice are employed, overcome impact of the high-temperature heat treatment to solar cell performance, particularly open-circuit voltage.
The preparation method of the present invention has compatibility with CMOS technology, it is adaptable to large-scale industrial production.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
The personage for knowing this technology all can carry out modifications and changes to above-described embodiment under the spirit and the scope without prejudice to the present invention.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (26)
1. a kind of preparation method of efficient film crystal silicon solar battery, it is characterised in that at least comprise the following steps：
1) SOI substrate is provided, the SOI substrate includes backing bottom, oxygen buried layer and top layer silicon from the bottom to top successively；
2) silicon epitaxy layer of the silicon epitaxy layer and p-type low doping concentration of p-type high-dopant concentration is sequentially formed in the top layer silicon；
3) emitter layer is formed on the silicon epitaxy layer of the p-type low doping concentration；Concrete grammar is：Initially with ion implanting
Or ion diffusion technique forms the N-type silicon layer of high-dopant concentration on the silicon epitaxy layer of the p-type low doping concentration；The doping
Element is P elements；Then silicon nitride passivation is formed using pecvd process in the N-type silicon layer of the high-dopant concentration；Or
Initially with pecvd process successively formation intrinsic amorphous silicon layer and N-type amorphous on the silicon epitaxy layer of the p-type low doping concentration
Silicon layer；Then it is deposited in the N-type non-crystalline silicon layer and forms nesa coating using sputtering or reaction and plasma；
4) etch areas are defined on the emitter layer, the etch areas is performed etching to form groove, the groove
At least include base region groove；The groove runs through the emitter layer, and the bottom of the groove is low-doped positioned at the p-type
The silicon epitaxy layer of concentration is interior or extends to the silicon epitaxy layer upper surface of the p-type high-dopant concentration；
5) base electrode is prepared in the base region channel bottom；
6) emitter electrode is prepared on the emitter layer；
7) by step 6) obtained by structure carry out annealing heat-treats.
2. the preparation method of efficient film crystal silicon solar battery according to claim 1, it is characterised in that：In step 2)
In, silicon epitaxy layer and p-type of the adopted chemical vapour deposition technique in p-type high-dopant concentration described in the top layer silicon Epitaxial growth
The silicon epitaxy layer of low doping concentration.
3. the preparation method of efficient film crystal silicon solar battery according to claim 1, it is characterised in that：In step 4)
In, removed using wet-etching technology, electrochemical corrosive process or RIE dry etch process described in the emitter layer
Bright conducting film, the etchant solution used in the wet-etching technology are dilution HCl solution, in the electrochemical corrosive process
The etchant solution for being used is NaOH solution that mass fraction is 5%～15%.
4. the preparation method of efficient film crystal silicon solar battery according to claim 1, it is characterised in that：In step 4)
In, the groove also includes the isolation channel on the outside of the base region groove.
5. the preparation method of efficient film crystal silicon solar battery according to claim 1, it is characterised in that：Using screen printing
Brush or evaporation coating technique prepare the base electrode and the emitter electrode.
6. the preparation method of efficient film crystal silicon solar battery according to claim 1, it is characterised in that：In step 7)
In, the annealing heat-treats are in N2, carry out under the conditions of Ar or air atmosphere, the temperature of the annealing heat-treats is 150 DEG C～350
℃。
7. a kind of efficient film crystal silicon solar battery, it is characterised in that：The solar cell at least includes：
SOI substrate, includes backing bottom, oxygen buried layer and top layer silicon from the bottom to top successively；
Epitaxial layer, including the silicon epitaxy layer of the silicon epitaxy layer and p-type low doping concentration of p-type high-dopant concentration；The p-type is highly doped
The silicon epitaxy layer of concentration is located at the upper surface of the top layer silicon, and the silicon epitaxy layer of the p-type low doping concentration is located at p-type height
The upper surface of the silicon epitaxy layer of doping content；
Emitter layer, is convexly equipped in the upper surface of the silicon epitaxy layer of the p-type low doping concentration；The emitter layer be include it is highly doped
The N-type silicon layer of miscellaneous concentration/silicon nitride passivation Rotating fields；Or be to include intrinsic amorphous silicon layer/N-type non-crystalline silicon layer/nesa coating
The heterojunction structure of structure, the thickness of the intrinsic amorphous silicon layer is 1nm～10nm, and the thickness of the N-type non-crystalline silicon layer is 1nm
～10nm, the thickness of the nesa coating is 60nm～120nm；
Groove, at least including base region groove；The groove runs through the emitter layer, and the bottom of the groove is positioned at described
The silicon epitaxy layer of p-type low doping concentration is interior or extends to the silicon epitaxy layer upper surface of the p-type high-dopant concentration；The groove will
The silicon epitaxy layer of the emitter layer and the p-type low doping concentration is divided into by the silicon epitaxy layer of the p-type low doping concentration
Silicon epitaxy layer, the p-type low doping concentration with the boss structure of emitter layer stacking or by the p-type high-dopant concentration
The boss structure that stacks with the emitter layer of silicon epitaxy layer；
Base electrode, positioned at the bottom of the base region groove；
Emitter electrode, on the emitter layer.
8. efficient film crystal silicon solar battery according to claim 7, it is characterised in that：The thickness of the top layer silicon is
20nm～200nm, the thickness of the oxygen buried layer is 200～500nm；The backing bottom is silicon substrate, ceramic substrate or sapphire
Substrate.
9. efficient film crystal silicon solar battery according to claim 7, it is characterised in that：The material of the epitaxial layer is single
Crystal silicon and/or polysilicon；The thickness of the silicon epitaxy layer of the p-type high-dopant concentration is 0.05 μm～2 μm, p-type element doping
Concentration is 5 × 1017～5 × 1019cm-3；The thickness of the silicon epitaxy layer of the p-type low doping concentration is 1 μm～50 μm, p-type element
The concentration of doping is 5 × 1015～5 × 1017cm-3。
10. efficient film crystal silicon solar battery according to claim 7, it is characterised in that：The base electrode with it is described
Boss structure constitutes mesa structure, and the spacing between the base electrode and the boss structure is 5 μm～200 μm.
11. efficient film crystal silicon solar batteries according to claim 7, it is characterised in that：The base electrode with it is described
Boss structure constitutes pectinate texture, and the spacing between the base electrode and the boss structure is 0.5 μm～2 μm.
12. efficient film crystal silicon solar batteries according to claim 7, it is characterised in that：The groove also includes isolation
Groove, the isolation channel are located at the outside of the base region groove.
13. efficient film crystal silicon solar batteries according to claim 7, it is characterised in that：The base electrode is aluminium electricity
Pole, the emitter electrode are silver electrode.
A kind of 14. autonomous energy integration chips based on efficient film crystal silicon solar battery, it is characterised in that：It is described from main source of energy
Integrated chip at least includes：
Efficient film crystal silicon solar battery and/or its array any one of claim 7 to 13, serves as a contrast positioned at the SOI
On bottom；
CMOS integrated circuits, positioned at the SOI substrate or outer of the efficient film crystal silicon solar battery and/or its array side
Prolong on layer；The CMOS integrated circuits are made up of CMOS transistor and its metal connection；
Interconnection structure, is adapted to the electrode and solar cell and/or the electrode of its array of the CMOS integrated circuits；And
Isolation structure, between the adjacent CMOS transistor, the adjacent CMOS transistor and the efficient film crystal silicon sun
It is in the top layer silicon between battery and between the adjacent efficient film crystal silicon solar battery or brilliant positioned at the adjacent CMOS
Between body pipe, between the adjacent CMOS transistor and efficient film crystal silicon solar battery and the adjacent efficient film crystal silicon too
In the top layer silicon between positive electricity pond and the epitaxial layer.
The 15. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 14, its feature
It is：The CMOS integrated circuits include high-potential electrode and low-potential electrode；The efficient film crystal silicon solar battery and/or
The base electrode of its array is connected with the high-potential electrode of the integrated circuit by the interconnection structure, the efficient film
The emitter electrode of crystal silicon solar battery and/or its array passes through the low-potential electrode of the interconnection structure and the integrated circuit
It is connected.
The 16. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 14, its feature
It is：The isolation structure is LOCOS isolation structures and/or STI isolation structures.
17. a kind of preparation methods of the autonomous energy integration chip based on efficient film crystal silicon solar battery, it is characterised in that extremely
Comprise the following steps less：
1) SOI substrate, the deposition mask layer in the SOI substrate, by photoetching and etching technics on the mask layer are provided
Define extension window, and the silicon epitaxy layer and p-type of selective growth p-type high-dopant concentration are low-doped successively in the extension window
The silicon epitaxy layer of concentration；
2) remove the mask layer, form isolation structure in the SOI substrate, the isolation structure by the SOI substrate every
From the efficient film crystal silicon solar battery region constituted for CMOS integrated circuits region and by the epitaxial layer；In the CMOS collection
CMOS integrated circuits are prepared in circuit region, and while battery are formed in the efficient film crystal silicon solar battery region
Base region；The CMOS integrated circuits include the CMOS transistor above the SOI substrate and the integrated electricity of parcel CMOS
Road region and the dielectric layer and the composition CMOS in the dielectric layer in the efficient film crystal silicon solar battery region
It is brilliant that the high-potential electrode and low-potential electrode of integrated circuit, the high-potential electrode and low-potential electrode are located at the efficient film
Side of the silicon solar cell region away from the CMOS transistor；
3) etching removes the dielectric layer in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer, N-type non-crystalline silicon layer and transition nesa coating are sequentially depositing and form heterojunction structure；Described different
Etch areas, base region of the etch areas at least including solar cell are defined on matter junction structure；And it is described to etch removal
The intrinsic amorphous silicon layer, N-type non-crystalline silicon layer beyond efficient film crystal silicon solar battery region and above the etch areas
With transition nesa coating；
5) etching forms the lead window of the CMOS integrated circuits；
6) prepare base electrode and connect the metal lead wire of the base electrode and the high-potential electrode of the CMOS integrated circuits；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating；Deposition of transparent conductive film, and etch the removal efficient film crystal silicon sun electricity
The nesa coating beyond the emitter region of pond and above the etch areas；
9) prepare emitter electrode and connect the emitter electrode and draw with the metal of the CMOS integrated circuits low-potential electrode
Line；
10) by step 9) obtained by structure carry out second annealing heat-treats.
The preparation side of the 18. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 17
Method, it is characterised in that：In step 4) in, the etch areas also include on the outside of the base region of the solar cell every
From groove.
The preparation side of the 19. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 17
Method, it is characterised in that：The temperature of the first time annealing heat-treats is 350 DEG C～500 DEG C；Second annealing heat-treats
Temperature is 150 DEG C～350 DEG C.
The preparation side of the 20. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 17
Method, it is characterised in that：The thickness of the intrinsic amorphous silicon layer is 1nm～10nm, the thickness of the N-type non-crystalline silicon layer be 1nm～
10nm, the thickness of the transition nesa coating is 120nm～200nm, the thickness of the nesa coating be 60nm～
120nm。
The preparation side of the 21. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 17
Method, it is characterised in that：Step 6) in the prepared base electrode be aluminium electrode, step 9) in the prepared emitter stage
Electrode is silver electrode.
22. a kind of preparation methods of the autonomous energy integration chip based on efficient film crystal silicon solar battery, it is characterised in that extremely
Comprise the following steps less：
1) SOI substrate is provided, the silicon epitaxy layer and p-type of growing P-type high-dopant concentration are low-doped dense successively in the SOI substrate
The silicon epitaxy layer of degree；
2) form isolation structure in the SOI substrate and the epitaxial layer, the isolation structure is by the SOI substrate and described
Epitaxial layer is isolated into CMOS integrated circuits region and efficient film crystal silicon solar battery region；In the CMOS integrated circuits region
Interior preparation CMOS integrated circuits, and while battery base region is formed in the efficient film crystal silicon solar battery region；Institute
Stating CMOS integrated circuits includes CMOS transistor above the epitaxial layer and parcel CMOS integrated circuits region and described
The height of the dielectric layer in efficient film crystal silicon solar battery region and the composition CMOS integrated circuits in the dielectric layer
Potential electrode and low-potential electrode, the high-potential electrode and low-potential electrode are located at the efficient film crystal silicon solar battery area
Side of the domain away from the CMOS transistor；
3) etching removes the dielectric layer in the efficient film crystal silicon solar battery region；
4) intrinsic amorphous silicon layer, N-type non-crystalline silicon layer and transition nesa coating are sequentially depositing and form heterojunction structure；Described different
Etch areas, base region of the etch areas at least including solar cell are defined on matter junction structure；And it is described to etch removal
The intrinsic amorphous silicon layer, N-type non-crystalline silicon layer beyond efficient film crystal silicon solar battery region and above the etch areas
With transition nesa coating；
5) etching forms the lead window of the CMOS integrated circuits；
6) prepare base electrode and connect the metal lead wire of the base electrode and the high-potential electrode of the CMOS integrated circuits；
7) by step 6) obtained by structure carry out first time annealing heat-treats；
8) remove the transition nesa coating；Deposition of transparent conductive film, and etch the removal efficient film crystal silicon sun electricity
The nesa coating beyond pool area and above the etch areas；
9) prepare emitter electrode and connect the emitter electrode and draw with the metal of the CMOS integrated circuits low-potential electrode
Line；
10) by step 9) obtained by structure carry out second annealing heat-treats.
The preparation side of the 23. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 22
Method, it is characterised in that：In step 4) in, the etch areas also include on the outside of the base region of the solar cell every
From groove.
The preparation side of the 24. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 22
Method, it is characterised in that：The temperature of the first time annealing heat-treats is 350 DEG C～500 DEG C；Second annealing heat-treats
Temperature is 150 DEG C～350 DEG C.
The preparation side of the 25. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 22
Method, it is characterised in that：The thickness of the intrinsic amorphous silicon layer is 1nm～10nm, the thickness of the N-type non-crystalline silicon layer be 1nm～
10nm, the thickness of the transition nesa coating is 120nm～200nm, the thickness of the nesa coating be 60nm～
120nm。
The preparation side of the 26. autonomous energy integration chips based on efficient film crystal silicon solar battery according to claim 22
Method, it is characterised in that：Step 6) in the prepared base electrode be aluminium electrode, step 9) in the prepared emitter stage
Electrode is silver electrode.
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| CN101719496A (en) * | 2009-12-03 | 2010-06-02 | 复旦大学 | Self-power integrated circuit chip and production method thereof |
| CN201708168U (en) * | 2010-07-26 | 2011-01-12 | 河南阿格斯新能源有限公司 | Solar battery |
| CN103137765A (en) * | 2013-02-04 | 2013-06-05 | 北京工业大学 | Aluminum-induced crystallization polycrystalline silicon thin-film solar cell and preparation method thereof |
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| CN101719496A (en) * | 2009-12-03 | 2010-06-02 | 复旦大学 | Self-power integrated circuit chip and production method thereof |
| CN201708168U (en) * | 2010-07-26 | 2011-01-12 | 河南阿格斯新能源有限公司 | Solar battery |
| CN103137765A (en) * | 2013-02-04 | 2013-06-05 | 北京工业大学 | Aluminum-induced crystallization polycrystalline silicon thin-film solar cell and preparation method thereof |
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