CN104303274A - Plasma etching method and plasma treatment device - Google Patents

Plasma etching method and plasma treatment device Download PDF

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CN104303274A
CN104303274A CN201380025589.4A CN201380025589A CN104303274A CN 104303274 A CN104303274 A CN 104303274A CN 201380025589 A CN201380025589 A CN 201380025589A CN 104303274 A CN104303274 A CN 104303274A
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plasma
gas
etch processes
mask
etch
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CN104303274B (en
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渡边光
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32091Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32137Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155Frequency modulation
    • H01J37/32165Plural frequencies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)

Abstract

A method for performing plasma etching on a silicon oxide film layer laminated on a wafer, using a silicon mask formed on the silicon oxide film as the mask; wherein the silicon oxide film layer (3) is etched using a plasma of a CF-containing gas, and an Si-containing material is then deposited on the mask using a plasma of an Si-containing gas, after which the silicon oxide film layer is again etched using a plasma of a CF-containing gas in a state in which the Si-containing material is deposited on the silicon mask. A hole having an aspect ratio equal to or greater than 60 is thereby formed.

Description

Plasma-etching method and plasma processing apparatus
Technical field
The present invention relates to and the method for plasma etch process is carried out to handled object and implements the plasma processing apparatus of this plasma etching.
No. 2012-136093, the Japanese Patent Application that the application filed an application in Japan based on June 15th, 2012 and the US61/663133 CLAIM OF PRIORITY of filing an application in the U.S. on June 22nd, 2012, quote their content here.
Background technology
In the manufacturing process of semiconductor device, carry out etching under the effect of such as plasma on handled object, the microfabrication such as film forming.As the example of the microfabrication utilizing plasma etching to carry out, there is the hole of such as groove, capacitor.
When forming hole by using the etch processes of plasma on silicon layer, such as silicon oxide film etc. is used as mask, but in this etch processes, if the etch-rate for improving silicon layer, then the etch-rate of silicon oxide film also can raise.Therefore, there is Selection radio when cannot improve etching, the such problem of etch depth cannot be deepened.Because if mask is etched to the greatest extent, then have to stop etching.
Therefore, such as, in patent documentation 1, disclosing such technology: when etching the silicon layer as handled object, using HBr gas, O 2gas, SiF gas etc., as process gas, implement etching to two kinds of High frequency power different for the lower electrode applying frequency loading handled object being configured at processing substrate indoor.Adopt this engraving method, the hole of high-aspect-ratio can be formed on silicon layer.
Patent documentation 1: Japanese Unexamined Patent Application Publication 2008-505497 publication
Summary of the invention
the problem that invention will solve
But, in recent years, along with the miniaturization, highly integrated of semiconductor device, in order to form the capacitor of the electric capacity with expectation, need to form hole, the groove that such as depth-to-width ratio is the high-aspect-ratio of more than 60.Its reason is, the electric capacity of capacitor becomes large with the area of the electrode forming capacitor in direct ratioly, along with miniaturization, in order to the surface area of maintenance electrode, requires that the degree of depth adding deep hole is tackled.
But the engraving method of patent documentation 1 cannot form the hole that depth-to-width ratio is more than 60 such high-aspect-ratios.
The present invention makes in view of the above problems, its object is to the hole, the groove that are formed high-aspect-ratio by plasma etch process.
for the scheme of dealing with problems
In order to reach described object, the present invention is a kind of plasma-etching method, in this plasma-etching method, between the upper electrode be located in container handling and lower electrode, apply High frequency power and make process gaseous plasma, as the mode of mask, plasma etch process is carried out to be formed at the silicon layer on this silicon nitride to the membranous layer of silicon oxide be laminated on substrate and silicon nitride layer, it is characterized in that, hole or the groove with the depth-to-width ratio of regulation is formed by following steps: carry out the 1st etch processes in this plasma-etching method, in the 1st etch processes, the plasma containing CF gas and the plasma containing CFH gas is utilized to etch described silicon nitride layer, then, carry out the 2nd etch processes, in the 2nd etch processes, the plasma containing CF gas is utilized to etch described membranous layer of silicon oxide, then, the plasma containing Si gas is utilized to deposit containing Si material on described mask, afterwards, carry out the 3rd etch processes, in the 3rd etch processes, under described silicon mask deposits the state containing Si material, the plasma containing CF gas is utilized again to etch membranous layer of silicon oxide.
The present inventors confirms, after silicon layer is carried out etch processes as mask to silicon oxide film, what utilize containing Si gas is plasma-deposited containing Si material, even if thus the plasma reused afterwards containing CF gas carries out etch processes, mask also can not be disappeared to the greatest extent by etching.The present invention makes based on this opinion, adopts the present invention, and using silicon layer as after mask carries out etch processes to membranous layer of silicon oxide, what utilize containing Si gas is plasma-deposited containing Si material.Further, afterwards, the plasma containing CF gas is used again to carry out etch processes.Now, even if again etch, mask also can not disappear and be maintained, and therefore compared with the pastly the hole of the pattern of expectation can be dug further deeply.As a result, the hole of the depth-to-width ratio of regulation can be formed, groove, such as depth-to-width ratio be more than 60 hole, groove.
Another invention of the application is a kind of plasma processing apparatus, it between the upper electrode be located in container handling and lower electrode, applies High frequency power and makes process gaseous plasma, the membranous layer of silicon oxide be laminated on substrate and silicon nitride layer are carried out to the plasma processing apparatus of plasma etching, it is characterized in that, this plasma processing apparatus comprises: container handling, and it is for receiving described substrate; High frequency electric source, it is for applying High frequency power to the upper electrode be located in described container handling and lower electrode; Process supplies for gas, it is for supply process gas in described container handling, described process supplies for gas comprises: etching gas supply unit, its supply be used for silicon nitride layer carry out etch processes containing CF gas and containing CFH gas, for membranous layer of silicon oxide is carried out etch processes containing CF gas; Coating gas supply part, its supply is used for containing Si gas containing Si material being formed on the silicon mask on described silicon oxide film deposition.
the effect of invention
Adopt the present invention, hole, the groove of high-aspect-ratio can be formed by plasma etch process.
Accompanying drawing explanation
Fig. 1 is the longitudinal section of the schematic configuration of the plasma processing apparatus representing present embodiment.
Fig. 2 is the cutaway view being shown schematically in state wafer being formed with membranous layer of silicon oxide, silicon nitride layer and silicon mask.
Fig. 3 schematically shows the cutaway view being formed porose state by the 2nd etch processes at wafer.
Fig. 4 schematically shows the cutaway view making to contain the state of Si electrodeposition substance on mask by coating process.
Fig. 5 is the cutaway view of the state schematically showing the wafer carried out after the 3rd etch processes.
Fig. 6 is the key diagram of the result representing validation test.
Fig. 7 is the table of the result representing validation test.
Embodiment
Hereinafter, with reference to the accompanying drawings of an example of embodiments of the present invention.Fig. 1 is the longitudinal section of the schematic configuration of the plasma processing apparatus 1 representing embodiments of the present invention.The plasma processing apparatus 1 of present embodiment is the plasma etch process device of such as parallel plate-type, utilizes plasma to carry out etch processes to the membranous layer of silicon oxide be laminated on wafer W.Further, in the present embodiment, the wafer W that carry out etch processes is silicon substrate, and surface is formed with membranous layer of silicon oxide 3 as shown in Figure 2 thereon.Membranous layer of silicon oxide 3 is formed silicon nitride layer 4, silicon nitride layer 4 is formed with predetermined pattern the mask 5 be such as made up of polysilicon.
Plasma processing apparatus 1 has roughly cylindric container handling 11, and container handling 11 is provided with the wafer jig 10 for keeping wafer W.Container handling 11 utilizes earth connection 12 to be electrically connected and ground connection with the earth.Further, the inwall of container handling 11 is covered by lining (not shown), is formed with the spraying plating overlay film be made up of the material of plasma-resistance on the surface of lining.
The lower surface of wafer jig 10 is supported by the pedestal 13 as lower electrode.Pedestal 13 is formed as roughly discoid by metals such as such as aluminium.Be provided with supporting station 15 in the bottom of container handling 11 across insulation board 14, pedestal 13 is supported in the upper surface of this supporting station 15.Being provided with electrode (not shown) in the inside of wafer jig 10, generating electrostatic force by applying direct voltage to this electrode, thus wafer W can be adsorbed maintenance.
Pedestal 13 upper surface and be the conditioning ring 20 being provided with the conductivity be made up of such as silicon at the peripheral part of wafer jig 10, conditioning ring 20 is for improving the uniformity of plasma treatment.The lateral surface of pedestal 13, supporting station 15 and this three of conditioning ring 20 is covered by by the cylinder element 21 that such as quartz is formed.
In the inside of supporting station 15 in the such as circular refrigerant flow path 15a be provided with for flow of refrigerant, by controlling the temperature of the cold-producing medium supplied in this refrigerant flow path 15a, the temperature of the wafer W kept by wafer jig 10 can be controlled.And, between wafer jig 10 and the wafer W that remain by this wafer jig 10, be provided with the heat-conducting gas pipe 22 for supplying heat-conducting gas, such as helium, heat-conducting gas pipe 22 such as with run through the bottom of container handling 11, pedestal 13, supporting station 15 and insulation board 14 mode arrange.
Pedestal 13 is electrically connected with the 1st high frequency electric source the 30,1st high frequency electric source 30 for generating plasma to this pedestal 13 supply high frequency electric power via the 1st adaptation 31.1st high frequency electric source 30 is configured to the High frequency power of output example as the frequency of 27MHz ~ 100MHz, and output example is as the High frequency power of 100MHz in the present embodiment.1st adaptation 31 matches for the internal driving and load impedance making the 1st high frequency electric source 30, plays such effect: when generating plasma in container handling 11, make the internal driving of the 1st high frequency electric source 30 and load impedance apparent consistent.
In addition, pedestal 13 is electrically connected with the 2nd high frequency electric source the 40,2nd high frequency electric source 40 for applying bias voltage to this pedestal 13 supply high frequency electric power to wafer W via the 2nd adaptation 41, thus guides ion into wafer W.2nd high frequency electric source 40 is configured to the High frequency power of output example as the frequency of 400kHz ~ 13.56MHz, and output example is as the High frequency power of 3.2MHz in the present embodiment.2nd adaptation 41 is the same with the 1st adaptation 31, matches for the internal driving and load impedance making the 2nd high frequency electric source 40.
Above-mentioned 1st high frequency electric source 30, the 1st adaptation 31, the 2nd high frequency electric source 40, the 2nd adaptation 41 are connected with control part 150 described later, utilize control part 150 to control their action.
Upper electrode 42 is being provided with in the mode relative and parallel with pedestal 13 as above the pedestal 13 of lower electrode.Upper electrode 42 is supported on the top of container handling 11 by the supporting member 50 of conductivity.Thus, upper electrode 42 is the same with container handling 11, is earthing potential.
Upper electrode 42 is made up of battery lead plate 51 and electrode support plate 52, and battery lead plate 51 is formed with the opposite face relative with the wafer W being held in wafer jig 10, and electrode support plate 52 supports this battery lead plate 51 from the top of this battery lead plate 51.Be formed with multiple gas supply port 53 at battery lead plate 51 in the mode of this battery lead plate 51 through, multiple gas supply port 53 is for the inside supply process gas to container handling 11.Battery lead plate 51 is made up of the less low-resistance electric conductor of such as Joule heat or semiconductor, adopts such as silicon in the present embodiment.Further, electrode support plate 52 is made up of electric conductor, adopts such as aluminium in the present embodiment.
Be provided with at the central portion of electrode support plate 52 inside and be formed as roughly discoid gas diffusion chamber 54.In addition, be formed with multiple pore 55 extended from gas diffusion chamber 54 downwards in the bottom of electrode support plate 52, gas supply port 53 is connected with gas diffusion chamber 54 via this pore 55.
Gas diffusion chamber 54 is connected with gas supply pipe 71.Gas supply pipe 71 is connected with process supplies for gas 72 as shown in Figure 1, supplies the process gas come be supplied to gas diffusion chamber 54 via gas supply pipe 71 from process supplies for gas 72.The process gas being supplied to gas diffusion chamber 54 is imported in container handling 11 via pore 55 and gas supply port 53.That is, upper electrode 42 plays a role as the shower nozzle of supply process gas in container handling 11.
The process supplies for gas 72 of present embodiment comprises the etching gas supply unit 72a of the process gas for supplying etch processes and the coating gas supply part 72b for carrying out applying process.In addition, process supplies for gas 72 is included in the valve 73a and flow rate adjusting mechanism 74a that arrange between gas supply part 72a and gas diffusion chamber 54, the valve 73b arranged between gas supply part 72b and gas diffusion chamber 54 and flow rate adjusting mechanism 74b.Flow to the gas of gas diffusion chamber 54 supply is controlled by flow rate adjusting mechanism 74a, 74b.
As the etching gas of etch processes, the etching etching gas of silicon nitride layer 4 can use such as C 4f 6/ CH 2f 2/ O 2mist, the etching etching gas of membranous layer of silicon oxide 3 can use C 4f 6/ Ar/O 2mist.Coating gas for carrying out applying process can use such as containing SiCl 4gas, in the present embodiment, use such as SiCl 4the mist of/He.
In the bottom of container handling 11, form exhaust flow path 80 by the inwall of container handling 11 and the lateral surface of cylinder element 21, exhaust flow path 80 plays a role as the stream of the outside atmosphere gas in container handling 11 being discharged to this container handling 11.Exhaust outlet 90 is provided with in the bottom surface of container handling 11.Be formed with exhaust chamber 91 in the below of exhaust outlet 90, this exhaust chamber 91 is connected with exhaust apparatus 93 via blast pipe 92.Thus, by driving exhaust apparatus 93, the atmosphere gas in container handling 11 can be discharged via exhaust flow path 80 and exhaust outlet 90, thus the vacuum degree of regulation being decompressed in container handling.
Further, around container handling 11, ring-shaped magnetic body 100 is configured with this container handling 11 in concentric circles.Utilize ring-shaped magnetic body 100 can to the applying magnetic field, space between wafer jig 10 and upper electrode 42.This ring-shaped magnetic body 100 is configured to by not shown rotating mechanism rotatable.
Described plasma processing apparatus 1 is provided with control part 150 as described above.Control part 150 is such as computers, has program storage part (not shown).Program storage part also store for each power supply 30,40, each adaptation 31,41 and each flow rate adjusting mechanism 74a, 74b etc. control and make the program of plasma processing apparatus 1 action.
In addition, also can be, described program is stored in the storage medium of the embodied on computer readable such as hard disk (HD), floppy disk (FD), CD (CD), magneto optical disk (MO), storage card of such as embodied on computer readable, is installed to control part 150 from this storage medium.
The plasma processing apparatus 1 of present embodiment is formed as described above, then, is described the plasma etch process of the plasma processing apparatus 1 of present embodiment.
For plasma etch process, first, in container handling 11, move into wafer W, wafer W is loaded and is held on wafer jig 10.Now, as described, wafer W is formed with the mask 5 of membranous layer of silicon oxide 3, silicon nitride layer 4 and predetermined pattern as shown in Figure 2.
If wafer W is held in wafer jig 10, then be vented in container handling 11 under the effect of exhaust apparatus 93, meanwhile for carry out the etch processes (the 1st etch processes) of silicon nitride layer 4 process gas first from etching gas supply unit 72a to specify that flow supplies in container handling 11.The process gas of the 1st etch processes uses C 4f 6/ CH 2f 2/ O 2mist, supply with the flow of 42sccm/90sccm/100sccm respectively.
Meanwhile, the 1st high frequency electric source 30 and the 2nd high frequency electric source 40 is utilized to apply High frequency power to the pedestal 13 as lower electrode continuously.Thus, the process gas being supplied to the etch processes in container handling 11 is in plasma between upper electrode 42 and pedestal 13.Now, plasma is closed between upper electrode 42 and pedestal 13 under the effect in the magnetic field of ring-shaped magnetic body 100.So, utilize ion, the free radical generated by the plasma in container handling 11 to be that mask 5 pairs of silicon nitride layers 4 of etching etch with polysilicon.
If the etching of silicon nitride layer 4 terminates, just then carry out the etch processes of the membranous layer of silicon oxide 3 as the 2nd etch processes.In this etch processes, from etching gas supply unit 72a using the flow of 100sccm/100sccm/94sccm, supply is as the C of etching gas 4f 6/ Ar/O 2, utilize and carry out etch processes by the ion of the plasma generation in container handling 11, free radical across mask 5 pairs of membranous layer of silicon oxide 3.Thus, as shown in Figure 3, form hole 200.In addition, when carrying out the etching of silicon nitride layer 4 and membranous layer of silicon oxide 3, the mask 5 of polysilicon is also etched simultaneously.
If the 2nd etch processes terminates, just then carry out the coating process of wafer W.In the coating process, from coating gas supply part 72b using the supply of the flow of 18sccm/100sccm as the SiCl of coating gas 4/ He.And, now, stop the 2nd high frequency electric source 40 to apply High frequency power to pedestal 13.So, as shown in Figure 4, utilize and deposit containing Si Compound D by the ion of the plasma generation in container handling 11, the mask 5 of free radical on wafer W, the upper surface of mask 5 is applied.
If the coating process of mask 5 terminates, just next again carry out the etch processes of membranous layer of silicon oxide 3.In etch processes (the 3rd etch processes) after coating, from etching gas supply unit 72a using the flow of 100sccm/100sccm/94sccm, supply is as the C of etching gas 4f 6/ Ar/O 2.So, using the mask 5 that deposits containing Si Compound D as etching mask, membranous layer of silicon oxide 3 is etched again.When carrying out the 3rd etch processes, as shown in Figure 5, mask 5 is also etched simultaneously, but the thickness that mask 5 has carried out coating process containing Si Compound D and short transverse increases.Therefore, after having carried out the 3rd etch processes, mask 5 also can not have been disappeared to the greatest extent by etching.Like this, there is residue by mask 5, again can carry out etch processes to membranous layer of silicon oxide 3, can dig further in the depth direction deeply membranous layer of silicon oxide 3.
In addition, as shown in Figure 4, be not only deposited on the upper surface of the mask after etch processes 5 containing Si Compound D, be also deposited on the side in the hole 200 of the membranous layer of silicon oxide 3 formed by the 2nd etch processes.So not only the upper surface of mask 5 applies, the side of membranous layer of silicon oxide 3 also applies.Thus, can prevent this situation: the side of membranous layer of silicon oxide 3 by etching, over etching is occurred when carrying out the 3rd etch processes, the diameter in the hole 200 of membranous layer of silicon oxide 3 becomes large thus.And when such as imbedding the process of metal to this hole 200 in subsequent handling and form capacitor, the electric capacity of the capacitor formed and the diameter in hole 200 are inversely proportional to.In other words, if the diameter that can maintain hole 200 is less, then the reduction of the capacity of electric capacity can be prevented.
In the above embodiment, during coating process, the 2nd high frequency electric source 40 does not apply High frequency power to pedestal 13.Therefore, can not guide ion into wafer W, during coating process, mask 5 can not by the ion(ic) etching being attracted.Therefore, it is possible to prevent the thickness of the short transverse of mask 5 from reducing, can dig further in the depth direction deeply membranous layer of silicon oxide 3 in the 3rd etch processes.
Adopting above execution mode, after polysilicon being used as mask 5 and etch processes has been carried out to membranous layer of silicon oxide 3, containing Si Compound D by deposit on mask 5 containing the plasma of Si gas.And, afterwards, use the plasma containing CF gas again to carry out etch processes.Now, in the etching again carried out, mask also can not disappear and be maintained, therefore, it is possible to make the hole 200 of the pattern of expectation dig further than ever deeply.As a result, can form such as depth-to-width ratio is the hole of the high-aspect-ratio of more than 60.
Further, be not only deposited on the upper surface of the mask 5 after the 2nd etch processes containing Si Compound D, be also deposited on the side in the hole 200 formed by the 2nd etch processes, therefore, it is possible to prevent from being etched excessively in the side of the 3rd etch processes hole when 200.As a result, can prevent the diameter in the hole 200 of membranous layer of silicon oxide 3 from becoming large thus.Such as, when imbedding the process of metal to this hole 200 in subsequent handling and form capacitor, the electric capacity of the capacitor formed and the diameter in hole 200 are inversely proportional to.So owing to adopting the present invention, can prevent the diameter in hole 200 from becoming large, in other words, the diameter that can maintain hole 200 is less, therefore, it is possible to the reduction of the electric capacity of the capacitor that will be formed after preventing.
In the above embodiment, describe the situation forming silicon nitride layer between mask 5 and membranous layer of silicon oxide 3, but no matter whether have silicon nitride layer to use the present invention.
In above execution mode, have employed SiCl as containing Si gas 4the mist of/He, but also can add O in this mist 2, so also can obtain same effect.The present inventors has carried out comparative test described later and has conducted in-depth research, and finds at interpolation O 2and supply SiCl 4/ He/O 2mist when, preferably the flow of each gas of this mist is respectively 20sccm/100sccm/125sccm.
In addition, the present inventor confirms: use SiCl in the coating process of mask 5 4when the mist of/He, the coated silicon fiml of mask 5, at use SiCl 4/ He/O 2mist when, the coated silicon oxide film of mask 5.And confirm: no matter use which kind of mist can both apply well mask 5, the disappearance of mask 5 in the 3rd etch processes can be prevented.
In the above embodiment, after having carried out applying process, carry out the 3rd etch processes, but also repeatedly can carry out this coating process and the 3rd etch processes.More specifically, utilize the mask 5 that apply containing Si Compound D to disappear because of the 3rd etch processes before temporary transient this etch processes of stopping.Then, again carry out coating process, utilize and containing Si Compound D, remaining mask 5 is applied, thus can again carry out the 3rd etch processes.Like this, repeatedly carry out coating process and etch processes, thus can such as hole 200 be dug darker, hole, the groove of high-aspect-ratio can be formed thus further.
Further, when repeatedly carrying out coating process and etch processes, as the mist of coating process, also SiCl can be used alternatingly 4the mist of/He and SiCl 4/ He/O 2mist.
In addition, in the above embodiment, employ polysilicon as mask 5, but also amorphous silicon can be used as mask 5.
Embodiment
As embodiment, after wafer W having been carried out to the 1st etch processes and the 2nd etch processes, use SiCl 4the mist of/He or SiCl 4/ He/O 2mist to mask 5 carry out coating process, use coating after mask 5 implement the 3rd etch processes.At that time, about coating process condition, the 3rd etching time on the impact of the shape in formed hole 200, carried out validation test.Now, the diameter of wafer W is 300mm, and the thickness as the polysilicon of mask 5 is 1200nm, and the thickness of silicon nitride layer 4 is 300nm.Further, the thickness being formed at the membranous layer of silicon oxide 3 of wafer W is 3500nm.
For the condition of plasma treatment during coating process, at use SiCl 4during the mist of/He, SiCl 4flow be the flow of 20sccm, He be 100sccm.In addition, by SiCl 4/ He/O 2mist for applying process time, SiCl 4flow be the flow of 20sccm, He be 100sccm, O 2flow be 125sccm.At that time, the pressure in container handling 11 is 1.33Pa, and the power of the 1st high frequency electric source 30 is 500W, and the number of repetition of coating process is changed, and the time of coating process is each time occurred the scope of 5 seconds ~ 20 seconds respectively.In addition, in the coating process, be all 0W (not powering) at the power of all situations the 2nd high frequency electric source 40.
1st etch processes utilizes C 4f 6/ CH 2f 2/ O 2mist carry out, C 4f 6flow be 42sccm, CH 2f 2flow be 90sccm, O 2flow be 100sccm.At that time, the pressure in container handling 11 is 2.0Pa, and the power of the 1st high frequency electric source 30 is 1400W, and the power of the 2nd high frequency electric source 40 is 4200W, and the 1st etch processes implements 205 seconds.Further, the 2nd etch processes and the 3rd etch processes use C 4f 6/ O 2the mist of/Ar carries out, C 4f 6the flow of gas is 100sccm, O 2the flow of gas is the flow of 94sccm, Ar gas is 100sccm.At that time, the pressure in container handling 11 is 2.26Pa, and the power of the 1st high frequency electric source 30 is 1500W, and the power of the 2nd high frequency electric source 40 is 7800W ~ 10000W, and the temperature of wafer W is 40 DEG C ~ 200 DEG C.The diameter of wafer W is 300mm, and the power density being therefore scaled the 1st high frequency electric source 30 during electric power and power density (Japanese: Electricity force density) of unit are is 2.12W/cm 2, the power density of the 2nd high frequency electric source 40 is 11W/cm 2~ 14.2W/cm 2.
In addition, as comparative example, also validation test is carried out to the situation only utilizing the 2nd etch processes to form hole.At that time, the cumulative time of the 2nd etch processes of carrying out in comparative example is identical with the cumulative time of the 2nd in embodiment and the 3rd etch processes.
The result of validation test represents in the table of Fig. 6 and Fig. 7.Fig. 6 schematically shows and carries out etch processes and the cutaway view defining the state in hole on membranous layer of silicon oxide 3, and the confirmation project in validation test is each size of 1 ~ 4 of the numeral impaled with circle in Fig. 6.Size 1 represents the size of the opening of the upper end of silicon nitride layer 4, and size 2 represents the size of the part that the width in mask 5 is the narrowest, and size 3 represents the size of the width the best part in hole 200.Size 4 represents the size of the depth direction in the hole 200 formed by etch processes.The size 1 ~ 4 of Fig. 6 is corresponding with the numeral described in the table of Fig. 7.Further, " depth-to-width ratio " in table refers to the ratio of size 1 and size 4." mask residual film " refers to that etch processes terminates the thickness of mask 5 remaining on rear wafer W.Further, " Selection radio " in table 1 refers to Selection radio that the residual film based on mask 5 is obtained, etch processes.
The temperature of wafer W is between 40 DEG C ~ 200 DEG C during the 1st etch processes ~ the 3rd etch processes and coating process, is constant, according to the difference of test, the temperature of wafer W is changed.Further, the value of the power of the 2nd high frequency electric source 40 is also be in 11W/cm in the 2nd etch processes and the 3rd etch processes 2~ 14.2W/cm 2between, be constant, according to the difference of test, the value of power changed.
As shown in the table of figure 7, confirm: with do not carry out applying process and the 3rd etch processes comparative example compared with, use SiCl 4in the embodiment 1 of the mist of/He, depth-to-width ratio is greatly improved, and can etch with the depth-to-width ratio of more than 60.Further, in the result shown in Fig. 7, the size of the size 4 of embodiment 1, the i.e. depth direction in hole 200 increases considerably compared with the size 4 of comparative example.It can thus be appreciated that, also can seek the raising of etch-rate in embodiment 1.
Confirm: in the embodiment 2 of repeatedly carrying out applying process and the 3rd etch processes and embodiment 3, also in the same manner as in Example 1, compared with comparative example, depth-to-width ratio is improved.Further, in embodiment 2 and embodiment 3, size 3 is less than the size 3 in comparative example.Carry out applying process containing Si Compound D this is because the side in hole 200 utilizes, thus the side in hole 200 can have been suppressed to be etched excessively in the 3rd etch processes of then carrying out afterwards.And; compared with only carrying out primary coating process, carrying out the embodiment 1 of the 3rd etch processes afterwards; in embodiment 2 and embodiment 3; 3rd etch processes is carried out repeatedly; repeatedly often carry out order 3 etch processes in the 3rd etch processes all to carry out coating and process, therefore can think and the protection of the side in hole 200 carried out closely.That is, by repeatedly carry out coating process and etch processes can etch with higher depth-to-width ratio.Further, size 3 diminishes, thus when such as apertures 200 forms capacitor, interelectrode distance can be made to diminish, so, in embodiment 2 and embodiment 3, compared with comparative example, the capacitor that electric capacity is large can be formed.
With do not carry out applying process and the 3rd etch processes comparative example compared with, use SiCl 4/ He/O 2mist embodiment 4 in be also that depth-to-width ratio obtains larger raising, can depth-to-width ratio more than 60 etch.
Embodiment 5 represents and utilizes SiCl in the coating process 4the mist of/He has carried out the coating process of 5 seconds, has used SiCl afterwards 4/ He/O 2mist carried out the result of the situation of the coating process of 20 seconds further.Confirm in this case also: compared with comparative example, depth-to-width ratio obtains larger raising.In addition, in embodiment 6, compared with comparative example, Selection radio is also greatly improved.This is because, SiCl 4/ He/O 2the Si coated film containing O (oxygen) formed and SiCl 4the Si coated film that/He is formed restrained effectively the etching of oppose side wall.
Embodiment 6 is expressed as follows the result of situation: compared with the temperature 40 DEG C of the wafer W of embodiment 1, and the temperature of wafer W becomes 200 DEG C, in addition identical with embodiment 1.In this case, also confirm: compared with comparative example, depth-to-width ratio obtains larger raising.This is because the part that size 2 narrows broadens relatively when high temperature, therefore, it is possible to etch into the darker part in hole 200.The reason that size 2 broadens is, when the temperature of wafer W is high temperature, the chemical reaction of free radical is promoted.
Embodiment 7 is expressed as follows the result of situation: compared with the temperature 40 DEG C of the wafer W of embodiment 1, and the temperature of wafer W becomes 120 DEG C, the 2nd and the 3rd etch processes time the 2nd high frequency electric source 40 performance number become 10000W from 7800W.That is, the electric power of unit are and power density are from 11W/cm 2become 14.2W/cm 2.In this case, also confirm: compared with comparative example, depth-to-width ratio obtains larger raising.This is because, when at Yin Gaowen, size 2 broadens, uprise for attracting the power density of ion.That is, according to embodiment 6 and embodiment 7, in order to depth-to-width ratio is more than 60, the temperature of preferred wafer W is 120 DEG C ~ 200 DEG C, and further, preferably the power density of the 2nd high frequency electric source 40 is 11W/cm 2~ 14.2W/cm 2.
Above, describe the preferred embodiment of the present invention, but the invention is not restricted to described example.Obviously to those skilled in the art, easily in the scope of the technical conceive described in claims, expect various modification or modification, these also belong to protection scope of the present invention certainly.
description of reference numerals
1, plasma processing apparatus; 10, wafer jig; 11, container handling; 12, earth connection; 13, pedestal; 14, insulation board; 15, supporting station; 20, conditioning ring; 21, cylinder element; 22, heat-conducting gas pipe; 30, the 1st high frequency electric source; 31, the 1st adaptation; 40, the 2nd high frequency electric source; 41, the 2nd adaptation; 42, upper electrode; 50, supporting member; 51, battery lead plate; 52, electrode support plate; 53, gas supply port; 54, gas diffusion chamber; 55, pore; 72a, etching gas supply unit; 72b, coating gas supply part; 73a, 73b, valve; 74a, 74b, flow rate adjusting mechanism; 80, exhaust flow path; 90, exhaust outlet; 91, exhaust chamber; 92, blast pipe; 93, exhaust apparatus; 100, ring-shaped magnetic body; 150, control part; W, wafer; R, resist layer pattern; H, residual film thickness; D, containing Si compound; M, etching mask.

Claims (7)

1. a plasma-etching method, in this plasma-etching method, between the upper electrode be located in container handling and lower electrode, apply High frequency power and make process gaseous plasma, to the membranous layer of silicon oxide be laminated on substrate and silicon nitride layer to carry out plasma etch process by being formed at the mode of the silicon layer on this silicon nitride as mask, it is characterized in that, in this plasma-etching method, form hole or the groove with the depth-to-width ratio of regulation as follows:
Carry out the 1st etch processes, in the 1st etch processes, utilize the plasma containing CF gas and the plasma containing CFH gas to etch described silicon nitride layer,
Then, carry out the 2nd etch processes, in the 2nd etch processes, utilize the plasma containing CF gas to etch described membranous layer of silicon oxide,
Then, the plasma containing Si gas is utilized to deposit containing Si material on described mask,
Afterwards, carry out the 3rd etch processes, in the 3rd etch processes, under described silicon mask deposits the state containing Si material, utilize the plasma containing CF gas again to etch membranous layer of silicon oxide.
2. plasma-etching method according to claim 1, wherein,
The depth-to-width ratio of described regulation is more than 60.
3. plasma-etching method according to claim 1, wherein,
Repeatedly carry out deposition on described silicon mask and contain the 3rd etch processes containing CF gas, membranous layer of silicon oxide etched described in the disposal and utilization of Si material.
4. plasma-etching method according to claim 1, wherein,
Described is SiCl containing Si gas 4gas.
5. plasma-etching method according to claim 1, wherein,
Described is SiCl containing Si gas 4and O 2mist.
6. plasma-etching method according to claim 1, wherein,
The temperature of the described substrate in described 2nd etch processes and described 3rd etch processes is 120 DEG C ~ 200 DEG C,
In described 2nd etch processes and described 3rd etch processes, be applied for described lower electrode the High frequency power attracting ion,
The power density of the described High frequency power applied is 11W/cm 2~ 14.2W/cm 2.
7. a plasma processing apparatus, it is the plasma processing apparatus for carrying out plasma etching to the membranous layer of silicon oxide be laminated on substrate and silicon nitride layer, it is characterized in that,
This plasma processing apparatus comprises:
Container handling, it is for receiving described substrate;
High frequency electric source, it is for applying High frequency power to the upper electrode be located in described container handling and lower electrode; And
Process supplies for gas, it is for supply process gas in described container handling,
Described process supplies for gas comprises:
Etching gas supply unit, its supply be used for silicon nitride film carry out etch processes containing CF gas and containing CHF gas, for membranous layer of silicon oxide is carried out etch processes containing CF gas;
Coating gas supply part, its supply is used for containing Si gas containing Si material being formed on the silicon mask on described silicon oxide film deposition.
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