CN104301090A - Four-dimensional chaotic system circuit with time-delay term - Google Patents

Abstract

The invention discloses a four-dimensional chaotic system circuit with time-lag items. The four-dimensional chaotic system circuit comprises a first channel circuit, a second channel circuit, a third channel circuit and a fourth channel circuit. The first channel circuit is composed of a multiplying unit A1, a phase inverter U1A, a phase inverter U2A, an antiphase integrator U3A, a time-lag unit and a resistor. The second channel circuit is composed of a multiplying unit A2, a phase inverter U4A, an antiphase integrator U5A and a resistor. The third channel circuit is composed of a multiplying unit A3, a phase inverter U6A, an antiphase integrator U7A and a resistor. The fourth channel circuit is composed of a multiplying unit A4, a multiplying unit A5, a phase inverter U9A, an antiphase integrator U10A and a resistor. According to the four-dimensional chaotic system circuit with the time-lag items, elements and element parameter values in the circuit units are changed so that eleven kinds of four-dimensional fractional order chaotic circuits with time-lag items can be achieved, and all the chaotic system circuits have respective chaotic dynamics behaviors. If the output signals of the system are used in the secrete communication field, and the confidentiality can be greatly improved.

Description

Four-dimensional chaotic system circuit with time-delay term

technical field

The invention relates to a four-dimensional chaotic system circuit with time-delay items, and belongs to the technical field of chaotic signal generator design.

Background technique

Since Lorenz of the Massachusetts Institute of Technology discovered the first chaotic attractor in 1963, there has been an upsurge in the study of chaos theory and practical applications. Chaotic signals have the characteristics of non-periodic, continuous broadband spectrum, and noise-like, which can provide rich signal design and generation mechanism, while time-delay chaotic systems can generate infinite-dimensional state space, so that the system has complex dynamic characteristics, new time-delay The continuous discovery and construction of chaotic systems can enrich chaos theory and deepen the understanding of chaotic phenomena.

At present, chaos science is gradually transitioning from theoretical research to practical application stage, and circuit realization is the most direct means to prove the existence of chaotic attractors and apply it to the engineering field. Designing time-delay chaotic system circuits with complex nonlinear terms, And extending its integer-order chaotic system to fractional-order chaotic system can accurately reflect the dynamic characteristics of the system. In addition, by changing the order of the chaotic system (that is, changing the structure of the circuit unit of the chaotic system), different order chaotic system circuits can be designed. If this kind of time-delay chaotic system circuit is applied to the experimental teaching of nonlinear circuits, the intuitiveness of nonlinear circuit design can be increased, and this kind of chaotic system circuit has a good application prospect in the field of secure communication.

Contents of the invention

The purpose of the present invention is to provide a chaotic system circuit, which can realize the secure communication of the chaotic signal by using the encoding and decoding technology of the system output signal. In addition, the chaotic system circuit can also be applied to the non-linear circuit teaching experiment.

The technical scheme adopted in the present invention is:

A four-dimensional chaotic system circuit with a time-delay term, which consists of four channel circuits: the first channel circuit consists of a multiplier A1, an inverter U1A, an inverter U2A, an inverting integrator U3A, a time-delay unit and a resistor R1 , R2, R3, R4, R5, R6, R7 and R8, the second channel circuit is composed of multiplier A2, inverter U4A, inverting integrator U5A and resistors R9, R10, R11 and R12, the third channel circuit It is composed of multiplier A3, inverter U6A, inverting integrator U7A and resistors R13, R14, R15, R16 and R17. The fourth channel circuit consists of multiplier A4, multiplier A5, inverter U9A, inverting integrator Composed of U10A and resistors R18, R19, R20 and R21; the output signal of the first channel circuit is fed back to the input terminal, one end is connected to the resistor R4 and the delay unit as an input signal, and the other end is connected to the resistor R8 as another input signal, the output The signal is also used as one input signal of the multiplier A2 in the second channel circuit, the multiplier A3 in the third channel circuit and the multiplier A5 in the fourth channel circuit; the output signal of the second channel circuit is fed back to the input terminal, The connection resistor R9 is used as one input signal, and the output signal is also used as one input signal of the multiplier A1 in the first channel circuit, the multiplier A3 in the third channel circuit and the multiplier A4 in the fourth channel circuit; The output signal of the channel circuit is fed back to the input terminal, and the resistor R16 is connected as an input signal, which is also used as an input signal of the multiplier A1 in the first channel circuit and the multiplier A2 in the second channel circuit respectively. Connect the multipliers A4 and A5 respectively to act on the fourth channel; the output signal of the fourth channel circuit is fed back to the input terminal and connected to the resistor R15 in the third channel circuit as an input signal, and the output signal is also connected with the resistor in the first channel R5 is connected as an input signal.

The inverting integrator includes an inverter and a circuit unit. When the circuit unit is a single capacitor, the four-dimensional chaotic system circuit is a four-dimensional integer-order chaotic system circuit; when the circuit unit is formed by mixing and connecting several resistance-capacitor parallel circuits When , the four-dimensional chaotic system circuit is a four-dimensional fractional order chaotic system circuit. Since the order of the fractional-order circuit unit is 0.90-0.99, ten kinds of four-dimensional fractional-order chaotic system circuits containing time-delay items are formed. The output of the fractional-order inverting integrator U3A in the first channel circuit is an X signal; the second channel The output of the fractional inverting integrator U5A in the circuit is a Y signal; the output of the fractional inverting integrator U7A in the third channel circuit is a Z signal; the output of the fractional inverting integrator U10A in the fourth channel circuit is a W signal.

The time-delay unit includes two inverters, two resistors and ten T-type LCL filters, wherein the T-type LCL filter is composed of two inductors and one capacitor connected in parallel, each inductor is 9.5mH , the capacitance is 525nF, the input signal passes through an inverter first, then connects a 1KΩ resistor, then connects ten T-type LCL filters in series, then connects a 1KΩ resistor, and finally outputs the signal through another inverter .

The present invention designs a novel fractional order circuit unit, successfully realizes a circuit unit with a fractional order of 0.90 to 0.99, and uses an analog circuit to realize eleven kinds of chaotic system time-delay circuits, and each chaotic system circuit has its own Therefore, this kind of chaotic system has complex dynamic characteristics. If the output signal of the system is used in the field of secure communication, the security can be greatly improved. The present invention has the advantages of: (1) adding a time-delay unit on the basis of the traditional chaotic system circuit, and extending it to the field of fractional order, which has more practical research value; (2) the system circuit in the present invention has complex Due to the nonlinear dynamic characteristics, the coding and decoding technology of the signal can be used to realize the secure communication of the chaotic signal.

Description of drawings

Fig. 1 is a schematic circuit diagram of the present invention;

Fig. 2 is the circuit diagram of integer order chaotic system;

Fig. 3 is a structural diagram of a time-delay unit;

Fig. 4 is the structure diagram of the circuit unit whose fractional order is 0.90;

Fig. 5 is the structure diagram of the circuit unit whose fractional order is 0.91;

Fig. 6 is the structure diagram of the circuit unit whose fractional order is 0.92;

Fig. 7 is the structure diagram of the circuit unit whose fractional order is 0.93;

Fig. 8 is a circuit unit structure diagram with a fractional order number of 0.94;

Fig. 9 is a circuit unit structure diagram with a fractional order number of 0.95;

Fig. 10 is the structure diagram of the circuit unit whose fractional order is 0.96;

Fig. 11 is a circuit unit structure diagram with a fractional order of 0.97;

Fig. 12 is a circuit unit structure diagram with a fractional order number of 0.98;

Fig. 13 is a circuit unit structure diagram with a fractional order number of 0.99;

Fig. 14 is the X-Y phase plane diagram of integer order chaotic system circuit;

Fig. 15 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.90;

Fig. 16 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.91;

Fig. 17 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.92;

Fig. 18 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order order is 0.93;

Fig. 19 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.94;

Fig. 20 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.95;

Fig. 21 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.96;

Fig. 22 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.97;

Fig. 23 is the X-Y phase plane diagram of the chaotic system circuit whose fractional order is 0.98;

Fig. 24 is an X-Y phase plan view of a chaotic system circuit with a fractional order of 0.99.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific implementation.

The mathematical model involved in the present invention is as follows:

$\left\{\begin{array}{c}\frac{{\mathrm{<span\; class="notranslate">\; d</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; x</span>}}{{\mathrm{<span\; class="notranslate">\; dt</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; yz</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; w</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\\ \frac{{\mathrm{<span\; class="notranslate">\; d</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; the\; y</span>}}{{\mathrm{<span\; class="notranslate">\; dt</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; xz</span>}<span\; class="notranslate">\; ,</span>\\ \frac{{\mathrm{<span\; class="notranslate">\; d</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; z</span>}}{{\mathrm{<span\; class="notranslate">\; dt</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; xy</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; w</span>}<span\; class="notranslate">\; ,</span>\\ \frac{{\mathrm{<span\; class="notranslate">\; d</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; w</span>}}{{\mathrm{<span\; class="notranslate">\; dt</span>}}^{\mathrm{<span\; class="notranslate">\; q</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; xz</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; yz</span>}<span\; class="notranslate">\; .</span>\end{array}\right.$

In the formula, x, y, z, w are state variables, and q is the order. When q=1, the system is an integer-order chaotic system, and when q<1, the system is a fractional-order chaotic system. τ is a time-delay item, and its coefficient is an unfixed value. According to the numerical simulation, eleven kinds of chaotic systems containing time-delay items in the present invention are all in a chaotic state when the time-delay variable τ=1, and the system is relatively stable , so the present invention selects the lag variable τ=1. The structure diagram of the corresponding time-delay unit is shown in Figure 3. The time-delay unit includes two inverters, two resistors and ten T-type LCL filters, where the T-type LCL filter is composed of two inductors and one Capacitors are composed of two parallel connections, each inductance is 9.5mH, and the capacitance is 525nF. The input signal first passes through an inverter, then connects a 1KΩ resistor, and then connects ten T-type LCL filters in series and then connects a 1KΩ The resistor, and finally output the signal through another inverter. This invention also has good expansibility, and the size of the time-delay variable can be changed according to needs. For example, when the time-delay variable τ=2 needs to be changed, it can be obtained by connecting two time-delay units in series. Such changes are all based on the present invention, and will not be listed one by one here.

The simulation circuit involved in the present invention is made up of first, second, third and fourth channel circuits, and the first, second, third and fourth channel circuits realize the first, second and third in the above-mentioned mathematical model respectively. , the fourth function.

As shown in Figure 1, the four-dimensional chaotic system circuit containing the time-delay term of the present invention is composed of four channel circuits: the output terminal of the fractional-order inverting integrator U3A in the first channel circuit is the X signal; The output terminal of the inverting integrator U5A is the Y signal; the output terminal of the fractional inverting integrator U7A in the third channel circuit is the Z signal; the output terminal of the fractional inverting integrator U10A in the fourth channel circuit is the W signal circuit, the resistor Capacitors are standard components, amplifier models are TL082CP; operational amplifier power supply value is 15V.

As shown in Figure 2, the integer-order chaotic system circuit of the present invention: the first channel circuit consists of a multiplier A1, an inverter U1A, an inverter U2A, an inverting integrator U3A, a time-delay unit, and resistors R1, R2, R3, Composed of R4, R5, R6, R7 and R8, the second channel circuit is composed of multiplier A2, inverter U4A, inverting integrator U5A and resistors R9, R10, R11 and R12, and the third channel circuit is composed of multiplier A3, Inverter U6A, inverting integrator U7A and resistors R13, R14, R15, R16 and R17, the fourth channel circuit consists of multiplier A4, multiplier A5, inverter U9A, inverting integrator U10A and resistor R18, Composed of R19, R20 and R21; the output signal of the first channel circuit is fed back to the input terminal, one end is connected to the resistor R4 and the time delay unit as an input signal, and the other end is connected to the resistor R8 as another input signal, and the output signal is also used as the second input signal respectively. One input signal of the multiplier A2 in the two-channel circuit, the multiplier A3 in the third channel circuit, and the multiplier A5 in the fourth channel circuit; the output signal of the second channel circuit is fed back to the input terminal, and the connection resistor R9 is used as one channel The input signal, the output signal is also used as one input signal of the multiplier A1 in the first channel circuit, the multiplier A3 in the third channel circuit and the multiplier A4 in the fourth channel circuit; the output signal of the third channel circuit Feedback to the input terminal, connect the resistor R16 as an input signal, and also serve as an input signal of the multiplier A1 in the first channel circuit and the multiplier A2 in the second channel circuit respectively, and the output signal is also respectively connected to the multiplier A4 And A5 acts on the fourth channel; the output signal of the fourth channel circuit is fed back to the input terminal and connected to the resistor R15 in the third channel circuit as an input signal, and the output signal is also connected to the resistor R5 in the first channel as an input Signal.

In the present invention, the fractional order circuit unit structure diagrams with fractional order numbers of 0.90, 0.91, 0.92, 0.93, 0.94, 0.95, 0.96, 0.97, 0.98, and 0.99 are shown in Figures 4, 5, 6, 7, 8, 9, and 10 respectively. , 11, 12, and 13.

The resistance and capacitance values of the fractional unit circuits in the above ten four-dimensional fractional chaotic system circuits containing time-delay items are:

Table 1 resistance value

q no R ₁ /MΩ R ₂ /MΩ R ₃ /MΩ R ₄ /MΩ 0.9 4 40.0753 20.1443 2.6122 0.2574 0.91 4 48.3909 17.8034 1.6909 0.1288 0.92 4 53.5260 14.6340 0.9585 0.0531 0.93 3 61.0797 10.9216 0.4448 0.94 3 68.6834 7.0126 0.1592 0.95 3 75.8351 3.5637 0.0367 0.96 3 81.9473 1.2210 0.0039 0.97 2 86.9046 0.1913 0.98 2 91.1831 0.0044 0.99 2 95.5402 4.6107×10 ^-8

Table 2 capacitance value

q no C ₁ /μF C ₂ /μF C ₃ /μF C ₄ /μF 0.9 4 0.5973 0.2714 0.2268 0.6472 0.91 4 0.4863 0.2484 0.2070 0.6242 0.92 4 0.4089 0.2296 0.1894 0.6020 0.93 3 0.3432 0.2245 0.7435 0.94 3 0.2934 0.2065 0.7148 0.95 3 0.2578 0.1916 0.6868 0.96 3 0.2324 0.1801 0.6601 0.97 2 0.2159 0.8045 0.98 2 0.2043 0.7710 0.99 2 0.1931 0.7386

Among them, q fractional order, n is the number of resistors and capacitors.

Carry out circuit simulation on the above eleven kinds of four-dimensional chaotic systems with time-delay items, and the obtained phase plane diagrams are shown in Fig. 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, The chaotic attractor has good ergodicity and boundedness. However, due to the difference in the fractional order, the movement form of the chaotic attractor is also somewhat different. This kind of fractional order chaotic system can be realized by circuit, so it has high research value.

Claims (5)

1. The four-dimensional chaotic system circuit containing time-delay term is characterized in that: the circuit is made up of four channel circuits: the first channel circuit is composed of multiplier A1, inverter U1A, inverter U2A, inverting integrator U3A, Delay unit and resistors R1, R2, R3, R4, R5, R6, R7 and R8, the second channel circuit consists of multiplier A2, inverter U4A, inverting integrator U5A and resistors R9, R10, R11 and R12 Composition, the third channel circuit is composed of multiplier A3, inverter U6A, inverting integrator U7A and resistors R13, R14, R15, R16 and R17, the fourth channel circuit is composed of multiplier A4, multiplier A5, inverter Composed of U9A, inverting integrator U10A and resistors R18, R19, R20 and R21; The output signal of the first channel circuit is fed back to the input terminal, one end is connected to the resistor R4 and the time delay unit as an input signal, and the other end is connected to the resistor R8 as another input signal, and the output signal is also used as a multiplier in the second channel circuit A2, one input signal of the multiplier A3 in the third channel circuit and the multiplier A5 in the fourth channel circuit; The output signal of the second channel circuit is fed back to the input terminal, and the resistor R9 is connected as an input signal. The output signal is also used as the multiplier A1 in the first channel circuit, the multiplier A3 in the third channel circuit, and the fourth channel circuit. One input signal of the multiplier A4 in; The output signal of the third channel circuit is fed back to the input terminal, and the connection resistor R16 is used as an input signal, and is also used as an input signal of the multiplier A1 in the first channel circuit and the multiplier A2 in the second channel circuit respectively. The signal is also respectively connected to the multipliers A4 and A5 to act on the fourth channel; The output signal of the fourth channel circuit is fed back to the input terminal and connected to the resistor R15 in the third channel circuit as an input signal, and the output signal is also connected to the resistor R5 in the first channel as an input signal. 2. the four-dimensional chaotic system circuit that contains time-delay term according to claim 1, is characterized in that: described anti-phase integrator comprises inverter and circuit unit, when circuit unit is single electric capacity, described four-dimensional chaotic system The circuit is an integer-order chaotic system circuit; when the circuit unit is formed by mixing and connecting several resistor-capacitor parallel circuits, the four-dimensional chaotic system circuit is a fractional-order chaotic system circuit. 3. the four-dimensional chaotic system circuit containing time-delay term according to claim 1 and 2, is characterized in that: described time-delay unit comprises two inverters, two resistances and ten T-type LCL filters, wherein The T-type LCL filter is composed of two inductors and a capacitor connected in parallel. Each inductor is 9.5mH and the capacitor is 525nF. The input signal first passes through an inverter, and then connects a 1KΩ resistor, and then connects with ten A T-type LCL filter is connected in series and then a 1KΩ resistor is connected, and finally the signal is output through another inverter. 4. The four-dimensional chaotic system circuit with time-delay term according to claim 3, characterized in that: the order of the fractional order is 0.90-0.99. 5. the four-dimensional chaotic system circuit containing time-delay term according to claim 4, is characterized in that: when described fractional order number is 0.90, the resistance and capacitance value in the circuit unit are respectively: 0.2596MΩ, 2.9047 MΩ, 2.9010MΩ, 59.9250MΩ, 0.9362μF, 0.2230μF, 2.0969μF and 0.2251μF; When the fractional order is 0.91, the resistance and capacitance values in the circuit unit are: 0.1295MΩ, 1.8354MΩ, 2.3330MΩ, 64.1137MΩ, 0.90312μF, 0.2048μF, 2.0209μF and 0.2142μF; When the fractional order is 0.92, the resistance and capacitance values in the circuit unit are: 0.0561MΩ, 14.5312MΩ, 0.0705MΩ, 54.5843MΩ, 0.8206μF, 0.1701μF, 2.2605μF and 0.4311μF; When the fractional order is 0.93, the resistance and capacitance values in the circuit unit are: 10.8112MΩ, 61.6349MΩ, 0.0219MΩ, 0.9501μF, 0.3579μF and 3.4185μF; When the fractional order is 0.94, the resistance and capacitance values in the circuit unit are: 6.9540MΩ, 68.9012MΩ, 0.0076MΩ, 0.9120μF, 0.3018μF and 3.3059μF; When the fractional order is 0.95, the resistance and capacitance values in the circuit unit are: 3.5466MΩ, 75.8888MΩ, 0.0017MΩ, 0.8745μF, 0.2615μF and 3.2007μF; When the fractional order is 0.96, the resistance and capacitance values in the circuit unit are: 1.2188MΩ, 81.9533MΩ, 0.0002MΩ, 0.8390μF, 0.2335μF and 3.0946μF; When the fractional order is 0.97, the resistance and capacitance values in the circuit unit are respectively: 914.102Ω, 9.3303MΩ, 0.8045μF and 0.2159μF; When the fractional order is 0.98, the resistance and capacitance values in the circuit unit are respectively: 0.0044MΩ, 91.1831MΩ, 0.7710μF and 0.2043μF; When the fractional order is 0.99, the resistance and capacitance values in the circuit unit are respectively: 0.046107Ω, 95.5402MΩ, 0.7386μF and 0.1931μF.