CN104299639A - Soft failure resistant memory cell, latch and trigger - Google Patents
Soft failure resistant memory cell, latch and trigger Download PDFInfo
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- CN104299639A CN104299639A CN201410488333.3A CN201410488333A CN104299639A CN 104299639 A CN104299639 A CN 104299639A CN 201410488333 A CN201410488333 A CN 201410488333A CN 104299639 A CN104299639 A CN 104299639A
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Abstract
The invention discloses a soft failure resistant memory cell, a latch and a trigger. The soft failure resistant memory cell comprises a soft failure resistant circuit, wherein a cross coupling pull-down NMOS (N-channel metal oxide semiconductor) pipe and a pull-down maintaining NMOS pipe of the soft failure resistant circuit are both connected with NMOS pipes respectively; the soft failure resistant memory cell also comprises a phase inverter, the drain electrode of the cross coupling pull-down NMOS pipe is connected with the grid electrode of the NMOS pipe serially connected with the pull-down maintaining NMOS pipe by the phase inverter. The soft failure resistant memory cell, the latch and the trigger can effectively improve the soft failure resistant capability of the sequential circuit under the conditions of low delay and power consumption loss, and has important application value and the practical significance for the soft failure obvious increasingly.
Description
Technical field
The present invention relates to anti-soft failure technical field, more specifically relate to a kind of anti-soft failure storage unit and latch and trigger.
Background technology
Soft failure mainly produces because alpha ray enters into Si caused by a large amount of charge carrier; Because all more or less containing radioelement such as U, Th in Si material or envelope material, during the nuclear fission of these elements, produce alpha ray; Alpha ray can be deep in Si 20 ~ 30 μm, and can produce the electron-hole pair of 10fC in every 1 μm; These carrier electric charge produced can destroy the data of preserving in storer, but this destruction is temporary, is therefore called soft failure.
In prior art, the main thought of anti-soft failure circuit comprises:
(1) redundant storage unit stores information, and the impact making one of them unit be subject to soft failure can not change the output of circuit.Such as triple module redundancy technology, this technology can only prevent in 3 storage unit one situation that soft failure occurs, if the upset of in 3 unit 2 or the state that more mostly occurs, so this technology effectively cannot play the effect of anti-soft failure; Although secondly this technology is widely used in the past, its excessive area overhead and power consumption penalty cause greatly reducing in the using value of present stage.
(2) utilize 2 same memory cell and output control circuit, make to be subject to exporting when soft failure affects and can remaining on high-impedance state, thus avoid the impact of soft failure.The C-element output-stage circuit unit of such as widespread use, but described C-element output-stage circuit unit Problems existing is the soft failure that can not prevent all nodes completely.
(3) utilize Schmidt trigger to increase the feature of noise margin, reduce the soft failure circuit of initial input, make soft failure voltage between 2 threshold voltages, eliminate soft failure.But the anti-soft failure circuit be made up of schmidt trigger has problems, requirement for device size is higher, generation transient surge voltage must be reduced to below Schmidt trigger forward threshold voltage Vth+ by the transmission gate of the first order or voltage lowering circuit, otherwise the effect of anti-soft failure cannot be played, wherein reduce voltage due to device R C value difference with transmission gate circuit, this requirement may be caused well not realize; And the area of other voltage lowering circuit and power dissipation overhead are too large, cause the actual application value based on the anti-soft failure circuit of Schmidt trigger also little.
(4) change the structure of storage unit in circuit, increase redundant storage node in the memory unit, utilize feedback mechanism to prevent the generation of soft failure.Such as DICE structure and Quatro-8T structure, but DICE complex structure, be not suitable for practical application; Quatro-8T exist for the problem that circuit stores information may be caused to overturn from 0 to 1 soft failure.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention how effectively to eliminate the adverse effect that storage unit soft failure brings to circuit.
(2) technical scheme
In order to solve the problems of the technologies described above, the invention provides a kind of anti-soft failure storage unit, comprising anti-soft failure circuit, the NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
Preferably, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
The invention also discloses a kind of trigger, comprise anti-soft failure storage unit, described anti-soft failure storage unit comprises anti-soft failure circuit; The NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
Preferably, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
The invention also discloses a kind of latch, comprise anti-soft failure storage unit, described anti-soft failure storage unit comprises anti-soft failure circuit; The NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
Preferably, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
(3) beneficial effect
The invention provides a kind of anti-soft failure storage unit and the electronic component containing anti-soft failure storage unit, a kind of anti-soft failure storage unit of the present invention and based on the electronic component of anti-soft failure storage unit under lower delay and power consumption penalty situation, effectively can improve the anti-soft failure ability of sequential circuit, in soft failure problem day by day significant today, there is significant application value and practical significance.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is traditional anti-soft failure circuit structure diagram;
Fig. 2 is the oscillogram of A, B, C, D tetra-memory nodes in traditional anti-soft failure circuit;
Fig. 3 be in traditional anti-soft failure circuit A node from the oscillogram of 1 to 0 soft failure;
Fig. 4 be in traditional anti-soft failure circuit A node from the oscillogram of 0 to 1 soft failure;
Fig. 5 is one of the present invention anti-soft failure storage unit circuit structural drawing;
Fig. 6 is that the A node of a kind of anti-soft failure storage unit of the present invention is from 1 to 0 soft failure oscillogram;
Fig. 7 is that the A node of a kind of anti-soft failure storage unit of the present invention is from 0 to 1 soft failure oscillogram;
Fig. 8 is the flip-latch circuit structure figure based on anti-soft failure storage unit of the present invention;
Fig. 9 is the simulation waveform figure of the latch based on anti-soft failure storage unit of the present invention;
Figure 10 a is the structural representation of traditional master-slave flip-flop;
Figure 10 b is the schematic diagram of traditional master-slave flip-flop;
Figure 11 is the electrical block diagram of the master-slave flip-flop of the clock jitter sensitivity based on anti-soft failure storage unit of the present invention;
Figure 12 is the simulation waveform figure of the master-slave flip-flop of the clock jitter sensitivity based on anti-soft failure storage unit of the present invention;
Figure 13 is the C based on anti-soft failure storage unit of the present invention
2the electrical block diagram of MOS master-slave flip-flop;
Figure 14 a is the structural representation of traditional pulse trigger;
Figure 14 b is the schematic diagram of traditional pulse trigger;
Figure 15 is the electrical block diagram of the upper edge pulse trigger based on anti-soft failure storage unit of the present invention;
Figure 16 is the simulation waveform figure of the upper edge pulse trigger based on anti-soft failure storage unit of the present invention;
Figure 17 is the lower edge master-slave flip-flop simulation waveform figure based on the anti-soft failure circuit structure of tradition;
Figure 18 is the upper edge pulse trigger simulation waveform figure based on the anti-soft failure circuit structure of tradition.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Following examples for illustration of the present invention, but can not be used for limiting the scope of the invention.
Fig. 1 is traditional anti-soft failure circuit structure diagram; Described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor MP1, the second metal-oxide-semiconductor MP2, the 3rd metal-oxide-semiconductor MP3, the 4th metal-oxide-semiconductor MP4; The source grounding of described four pull-up PMOS; Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor, play and keep A, B nodal value to act on, described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor are all called pull-up and keep PMOS.
Anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor MN3, the 6th metal-oxide-semiconductor MN4, the 7th metal-oxide-semiconductor MN1, the 8th metal-oxide-semiconductor MN2; The source grounding of described four pull-down NMOS pipe; Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, described 7th MOS, the 8th MOS are all called drop-down maintenance NMOS tube, play the effect keeping node C, D value, their grid connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, and the drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
Described traditional Quatro-8T circuit comprises A, B, C, D4 memory node, and wherein A, B is main memory node, and its basic thought eliminating soft failure is still C, D memory node introducing redundancy.
The principle of work of traditional anti-soft failure circuit is:
During normal work, there are 2 kinds of working conditions, (1) suppose A=1, the 6th metal-oxide-semiconductor MN4 is in conducting state, and B point is discharged to 0, A=1 makes the 7th metal-oxide-semiconductor MN1 conducting simultaneously, D point is discharged to 0, thus makes the second metal-oxide-semiconductor MP2 conducting, and C point is charged to 1,4th metal-oxide-semiconductor MP4 is in the state of shutoff, remains the state of B=0; Now A=C=1, B=D=0; (2) B=1 is supposed, then the 5th metal-oxide-semiconductor MN3 is in the state of conducting, A point is discharged to 0, B=1, make the 8th metal-oxide-semiconductor MN2 be in the state of conducting, C point is discharged to 0 simultaneously, C=0 makes the first metal-oxide-semiconductor MP1 conducting, D point is charged to 1, and the 3rd metal-oxide-semiconductor MP3 is in off state, keeps the state of A=0; Now A=C=0, B=D=1.By the analysis of above two kinds of possibility situations, can draw following conclusion: under the state that circuit normally works, the logical value of primary storage node A and B is reverse each other, and the logical value of A and C is equal simultaneously, and the logical value of B and D is equal.As shown in Figure 2, V (a) V (b), V (c), V (d) represent the voltage oscillogram of A, B, C, D tetra-memory nodes to the oscillogram of the normal work of the anti-soft failure circuit of tradition four memory nodes respectively in the accompanying drawings.
The anti-soft failure circuit of described tradition is subject to soft failure when affecting, there are 2 kinds of situations, the first situation, as A=1, A=C=1, B=D=0, if A point be subject to soft failure impact occur from 1 to 0 upset, the 7th metal-oxide-semiconductor MN1 and the 6th metal-oxide-semiconductor MN4 becomes off state from conducting, but the storing value of B, C, D 3 can't be changed, D=0 makes the 3rd metal-oxide-semiconductor MP3 conducting, and the A point becoming 0 is charged to 1 again, thus eliminates the impact of the soft failure that A point is subject to.A point input one be similar to soft failure from 1 to 0 transient pulse, as shown in Figure 3, A point returns to 0, B, the storing value of C, D does not all change, and does not show in figure 3, illustrates that traditional anti-soft failure circuit effectively can prevent the soft failure from 1 to 0.
The second situation, as A=0, A=C=0, B=D=1, if the soft failure that A point is subject to from 0 to 1 overturns, 7th metal-oxide-semiconductor MN1 and the 6th metal-oxide-semiconductor MN4 becomes conducting from original off state, B discharges into 0 from 1, D is also from 1 electric discharge 0, D=0 makes the second metal-oxide-semiconductor MP2 conducting, C point is charged to 1 from 0, now A=C=1, B=D=0, it is just in time a steady state (SS) of traditional anti-soft failure circuit, circuit can maintain this state, thus make the upset of this storage unit generation state, the anti-soft failure circuit of tradition effectively cannot prevent the impact of soft failure from 0 to 1.
A point input one be similar to soft failure from 0 to 1 pulse waveform, as shown in Figure 4, the value of A point can not return to 1, the storing value of B point becomes 0 from original 1, the state of C and D two nodes also there occurs upset respectively simultaneously, the store status of circuit overturns, and the storing value that B, C, D are 3 does not show in the diagram.
Fig. 5 is one of the present invention anti-soft failure storage unit circuit structural drawing; Described a kind of anti-soft failure storage unit comprises traditional anti-soft failure circuit, the cross-couplings pull-down NMOS pipe (the 5th metal-oxide-semiconductor MN3, the 6th metal-oxide-semiconductor MN3) of described anti-soft failure circuit and drop-down maintenance NMOS tube (the 7th metal-oxide-semiconductor MN1, the 8th metal-oxide-semiconductor MN2) are connected a NMOS tube all separately, are respectively the 9th metal-oxide-semiconductor MN5, the tenth metal-oxide-semiconductor MN6, the 11 metal-oxide-semiconductor MN7, the 12 metal-oxide-semiconductor MN8; The grid of the metal-oxide-semiconductor of connecting with described cross-couplings pull-down NMOS pipe i.e. the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor is connected respectively at the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor.
The anti-soft failure storage unit of described one also comprises the first phase inverter and the second phase inverter, and the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the 11 metal-oxide-semiconductor; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the 12 metal-oxide-semiconductor.
When the anti-soft failure storage unit of described one normally works, according to analysis before, the logical value of A and B is contrary, simultaneously A=C and B=D, 5th metal-oxide-semiconductor MN3 is connected B and D respectively with the grid of the 9th metal-oxide-semiconductor MN5, equivalence can become a NMOS tube when normal work, in like manner the 6th metal-oxide-semiconductor MN4 and the tenth metal-oxide-semiconductor MN6 also equivalence can become a NMOS.7th metal-oxide-semiconductor MN1 and the grid of the 11 metal-oxide-semiconductor MN7 are connected the direction of A and B respectively, input can be regarded as consistent, equivalence becomes a NMOS tube, in like manner the 8th metal-oxide-semiconductor MN2 and the 12 metal-oxide-semiconductor MN8 also equivalence can become a NMOS tube, namely, when normal work, described a kind of anti-soft failure storage unit and the anti-soft failure circuit of tradition do not have actual difference.
There are two kinds of situations in the anti-soft failure storage unit of described one.The first situation, work as A=1, during B=0, the 7th metal-oxide-semiconductor MN1 and the 11 metal-oxide-semiconductor MN7 conducting, D is discharged into 0, thus make the second metal-oxide-semiconductor MP2 conducting, C point is charged to 1, and the 8th metal-oxide-semiconductor MN2 and the 12 metal-oxide-semiconductor MN8 is in off state, the 6th metal-oxide-semiconductor MN4 and the tenth metal-oxide-semiconductor MN6 conducting, thus maintain B=0, simultaneously also to maintain the state of A=1 constant for D=0; The second situation, works as A=0, and during B=1, the right and left due to described a kind of anti-soft failure storage unit is in symmetrical state, so similar with the first situation, is in normal store status, A=C=0, B=D=1.
Described a kind of anti-soft failure storage unit is subject to soft failure impact and is divided into two kinds of different situations.When the first situation A=1, B=0, A point is subject to the impact from 1 to 0 soft failure.A point becomes 0, and cause the 6th metal-oxide-semiconductor MN4 and the 7th metal-oxide-semiconductor MN1 to be become the state of shutoff from conducting, the 12 metal-oxide-semiconductor MN8 becomes conducting, but the store status of B, C, D 3 can't change.D=0 makes the 3rd metal-oxide-semiconductor MP3 be in the state of conducting, and A point is charged to high level the most at last, eliminates the impact of soft failure.Emulate the oscillogram that obtains as shown in Figure 6 with Hspice, can see that the soft failure produced at A point does not have an impact to the circuit store status of reality from oscillogram, circuit A, B, C, D4 node keeps original value constant.
The second situation A=0, during B=1, A point is subject to the impact from 0 to 1 soft failure.A point becomes high level and causes the 6th metal-oxide-semiconductor MN4 and the 7th metal-oxide-semiconductor MN1 to be in the state of conducting, and the 12 metal-oxide-semiconductor MN8 ends; The state that MN8 is in shutoff causes the logical value of C point to be affected, the state making the tenth metal-oxide-semiconductor MN6 be in disconnection due to C=0 causes the logical value of B point to change, thus make the grid of the 11 metal-oxide-semiconductor MN7 be input as 0, MN7 is in the state of shutoff, thus makes D point preserve the state of D=1.B=D=1 makes the 5th metal-oxide-semiconductor MN3 and the 9th metal-oxide-semiconductor MN5 all be in the state of conducting, thus ensures that A point can discharge into 0, thus makes the logical value of A point can eliminate the impact of soft failure.The waveform prevented with Hspice as shown in Figure 7, can see that A point produces from 0 to 1 soft failure can't affect B, C, D3 node storing value, the flop phenomenon in traditional Q uatro-8T circuit can not be there is, prove a kind of anti-soft failure storage unit have anti-from 0 to 1 the ability of soft failure.
Multiple electronic component can be constructed based on above-mentioned one anti-soft failure storage unit.
Latch is the building block in sequential logical circuit, and it is a level-sensitive circuit, namely when clock signal is high level, input signal D is sent to output.Now latch is in transparent pattern; When clock is low level, the input data be sampled at clock falling edge place all keep stable in the output terminal all stage.The latch formed based on above-mentioned a kind of anti-soft failure storage unit as shown in Figure 8, A, B node of anti-soft failure storage unit is as input, as CLK=1,2 transmission gates are all in conducting state, the reverse of D and D is write A and B two nodes respectively, as CLK=0,2 transmission gates are turned off, and a kind of anti-soft failure storage unit maintains original state and remains unchanged.
With Hspice40nm technique to the simulation waveform of the latch based on above-mentioned a kind of anti-soft failure storage unit as shown in Figure 9, can see and be in pellucidity when CLK=1, be maintain original state at CLK=0, verify the correctness of its logic function.
Be different from level sensitive latches, the register only sampling input when clock overturns of edging trigger, during 0 to 1 upset, sampling is called positive edge trigger register, and during 1 to 0 upset, sampling is called marginal along trigger register.Trigger is normally made up of latch.The most commonsense method forming an edge triggered flip flop adopts host-guest architecture exactly, and Figure 10 a and Figure 10 b is structural drawing and the schematic diagram of traditional flip-flop; In the low level stage of clock, main is transparent, and input Data is sent to the output terminal Q1 of main, during this period, is in maintenance state from level, keeps its original value by feedback.During the rising edge of clock, main stops input sample, and samples from level.In the clock high level stage, from level, the output terminal Q1 of main is sampled, and main is in maintenance state.Because Q1 is constant in the clock high level stage, therefore export Q2 each cycle and only overturn once.Due to the value of Q be exactly rising edge clock before Data value, therefore there is positive edge trigger effect.Negative edge triggered flip flop can be formed by same principle, only needs the simple position changing positive and negative latch.Can see that from Figure 10 b Q1 latches the value of input Data, and Q2 is in the value of the upper edge of clock sampling input D, and maintains in other stages.
Based on the responsive master-slave flip-flop of unit structure clock jitter that a kind of anti-soft failure stores, as shown in figure 11, the unit that trigger has 2 anti-soft failures to store is formed, and the unit that its anti-soft failure with anti-soft failure ability stores makes this triggering have the function of anti-soft failure.Respectively by A and the B node being oppositely input to the unit that the anti-soft failure of main stores of input D and D, as CLK=1, main is transparent, be in maintenance state from level, as CLK=0, main is in maintenance state, from the output of level circuit sampling main, and by the output terminal Q of result slave flipflop, namely export from the C node of level latch stores unit, constitute the hypotactic trigger of negative edging trigger.By the technique of Hspice40nm, circuit is emulated, the simulation waveform figure of the lower edge trigger obtained, as shown in figure 12, demonstrate the correctness of its logic function.In Figure 12, waveform is respectively clock signal clk waveform from top to bottom, input signal data waveform, and exports Q waveform.
Based on C
2the unit structure that MOS structure and anti-soft failure store is to the insensitive host-guest architecture trigger of clock jitter, and as shown in figure 13, its main adopts capacitance storage mode, from the unit that level adopts anti-soft failure to store.
For pulse trigger, ultimate principle generates a short pulse near clock rising or falling, the effect of this pulse is similar to the clock input signal of latch, it only samples in a very short time window, avoid race condition by the clearing time of latch is very short, be equivalent to pulse-generating circuit and latch combinations to constitute an edge triggered flip flop.Its structural drawing and schematic diagram are respectively as shown in Figure 14 a, 14b.
The circuit structure diagram of the pulse trigger of the unit stored based on anti-soft failure as shown in figure 15, comprises the unit that a pulse generating circuit and anti-soft failure store.Pulse generating circuit can have a mind to generation pulse at each rising edge clock place.As CLK=0, nodes X can be charged to VDD.At rising edge clock place, the time of one very short is had to be in high level with two inputs of door, that Pulse rises, MN is made so to be again in the state of conducting, drop-down X is finally Pulse signal is low level, wherein the pulse width of pulse generating circuit generation is by the Time delay control with door and two phase inverters, by changing delay to the adjustment of device size, can obtain the pulse width that we need.The pulse of generation being received input end A, B of being inputted the unit that anti-soft failure stores by transmission gate, be equivalent to clock control signal, on top along sampling, forming trigger.Emulate with the carrying out of Hspice40nm technique to the pulse trigger of structure, as shown in figure 16, demonstrate the correctness of its logic function.
Based on traditional Q uatro-8T circuit form lower edge master-slave flip-flop simulation waveform figure as shown in figure 17, based on traditional Q uatro-8T circuit form pulse trigger simulation waveform figure as shown in figure 18, from Figure 17 and Figure 18 oscillogram, can see that the sequential logical circuit Elementary Function formed based on traditional Q uatro-8T is entirely true, the waveform of the electron device constructed with the unit stored based on anti-soft failure does not have difference.
Use Hspice40nm technique, clock signal CLK frequency is 500MHZ, input signal data data duty cycle is 50%, the pulse trigger that the lower edge master-slave flip-flop that frequency 250MHZ is formed the lower edge master-slave flip-flop formed based on traditional Q uatro-8T circuit, the pulse slave flipflop formed based on traditional Q uatro-8T circuit, the unit that stores based on anti-soft failure, the unit stored based on anti-soft failure are formed emulates, the time delay of measurement triggering device respectively, average power consumption, and Power dissipation delay, as shown in table 1.
Table 1
As seen from the table, the number of pipe when the latch of the unit structure stored based on anti-soft failure and trigger are owing to adding discharge and recharge, thus cause the increase of delay, master-slave flip-flop lower power consumption, pulse trigger power consumption increases, but the anti-soft failure ability of the electronic component formed is obtained for enhancing, in power consumption with when postponing to lose little, better improve anti-soft failure ability.
A kind of anti-soft failure storage unit provided by the invention and based on the latch of anti-soft failure storage unit and trigger, under lower delay and power consumption penalty situation, effectively can improve the anti-soft failure ability of sequential circuit, in soft failure problem day by day significant today, there is significant application value and practical significance.
Above embodiment is only for illustration of the present invention, but not limitation of the present invention.Although with reference to embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, various combination, amendment or equivalent replacement are carried out to technical scheme of the present invention, do not depart from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of right of the present invention.
Claims (6)
1. an anti-soft failure storage unit, comprises anti-soft failure circuit, it is characterized in that, the NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
2. the anti-soft failure storage unit of one according to claim 1, is characterized in that, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
3. a trigger, is characterized in that, comprises anti-soft failure storage unit, and described anti-soft failure storage unit comprises anti-soft failure circuit; The NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
4. a kind of trigger according to claim 3, is characterized in that, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
5. a latch, is characterized in that, comprises anti-soft failure storage unit, and described anti-soft failure storage unit comprises anti-soft failure circuit; The NMOS tube of described anti-soft failure circuit is all connected a NMOS tube;
9th metal-oxide-semiconductor of connecting with the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the tenth metal-oxide-semiconductor are connected with the 3rd metal-oxide-semiconductor of described anti-soft failure circuit, the grid of the 4th metal-oxide-semiconductor respectively;
Also comprise the first phase inverter and the second phase inverter, the input end of described first phase inverter connects the drain electrode of described 6th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 7th metal-oxide-semiconductor of described anti-soft failure circuit; The input end of described second phase inverter connects the drain electrode of described 5th metal-oxide-semiconductor, and its output terminal connects the grid of the NMOS tube of connecting with the 8th metal-oxide-semiconductor of described anti-soft failure circuit.
6. a kind of latch according to claim 5, is characterized in that, described anti-soft failure circuit comprises four pull-up PMOS, is called the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor; The source grounding of described four pull-up PMOS;
Described first metal-oxide-semiconductor, the second metal-oxide-semiconductor are connected to form cross-couplings pull-up PMOS by cross-couplings, and the grid of described 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor respectively at described first metal-oxide-semiconductor;
Described anti-soft failure circuit also comprises four pull-down NMOS pipe, is called the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor; The source grounding of described four pull-down NMOS pipe;
Described 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor are connected to form cross-couplings pull-down NMOS pipe by cross-couplings, and the grid of described 7th MOS, the 8th MOS connects respectively at the grid of described 6th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor; The drain electrode of described 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor connects respectively at the drain electrode of described first metal-oxide-semiconductor, the second metal-oxide-semiconductor; The drain electrode of described 3rd MOS, the 4th MOS connects respectively at the drain electrode of described 5th MOS, the 6th MOS.
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| US20080094925A1 (en) * | 2006-10-20 | 2008-04-24 | Manoj Sachdev | Soft Error Robust Static Random Access Memory Cells |
| CN102760486A (en) * | 2012-07-20 | 2012-10-31 | 北京大学 | SRAM (Static Random Access Memory) cell and memory array |
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| US20080094925A1 (en) * | 2006-10-20 | 2008-04-24 | Manoj Sachdev | Soft Error Robust Static Random Access Memory Cells |
| CN102760486A (en) * | 2012-07-20 | 2012-10-31 | 北京大学 | SRAM (Static Random Access Memory) cell and memory array |
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