CN104281544A - Memorizer controller and signal generating method of memorizer controller - Google Patents

Memorizer controller and signal generating method of memorizer controller Download PDF

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Publication number
CN104281544A
CN104281544A CN201310281167.5A CN201310281167A CN104281544A CN 104281544 A CN104281544 A CN 104281544A CN 201310281167 A CN201310281167 A CN 201310281167A CN 104281544 A CN104281544 A CN 104281544A
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signal
clock
instruction
memory module
command
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CN104281544B (en
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吴宗翰
林政南
陈忠敬
张雍
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MediaTek Inc
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MStar Semiconductor Inc Taiwan
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/16—Memory access

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention provides a memorizer controller and a signal generating method of the memorizer controller. The signal generating method is used for operating a first memorizer module. The signal generating method comprises the following steps that a first clock rate signal with the signal period being unit time is generated; an instruction signal with the signal period being the unit time is generated, wherein the instruction signal comprises a plurality of instruction groups, and each instruction group is provided with a first instruction and a second instruction which are continuous; an addressing signal set with the signal period being two times of the unit time is generated; a first signal edge of the first clock rate signal is set to the safety phase position section of the instruction signal; a second signal edge of the first clock rate signal is set to the safety phase position section of the instruction signal and the addressing signal set.

Description

Memory Controller and signal generating method thereof
Technical field
The present invention has about memory area, and relates to a kind of Memory Controller and signal generating method thereof especially.
Background technology
In general, Memory Controller (memory controller) is connected to memory module, by writing data into memory module or can read data by memory module.Memory module the most general is now Double Data Rate (double data rate, hereinafter referred to as DDR) memory module.
Please refer to Figure 1A and Figure 1B, its illustrate as the annexation between Memory Controller and memory module and control signal eye pattern (eye diagram) schematic diagram.Memory Controller 100 and DDR memory module 110 design on circuit board (PCB), and control signal comprises clock signal (CLK1), address signal A [15:0], command signal CMD and block control signal BANK [2:0].Command signal CMD comprises write enable signal (WE), column address trigger pip (row address strobe, RAS) and row address trigger pip (column address strobe, CAS).Block control signal BANK [2:0] comprises 3 pin positions (pin), and address signal A [15:0] comprises 16 pin positions.
Memory Controller 100 utilizes control signal to manipulate DDR memory module 110, such as, reads data, write data etc.Because DDR memory module 110 fastens the data of locking on address signal A [15:0], command signal CMD, block control signal BANK [2:0] along (such as rising edge or negative edge negative edge) according to the signal of clock signal (CLK1).Therefore, Memory Controller 100 suitably must adjust the phase place (phase) of clock signal (CLK1), make DDR memory module 110 be able to according to the signal of clock signal (CLK1) along and successfully fasten lock (latch) residence and have data in control signal.For convenience of description, all fasten lock signal with the rising edge of clock signal (CLK1) below, but be not limited thereto.
As shown in the figure, the cycle of clock signal (CLK1) is T, and the signal period of address signal A [15:0], command signal CMD, block control signal BANK [2:0] is also T.But, because the driving force of each control signal is different, thus between the safe phase region of control signal (or being called data valid interval) can T be less than.Therefore, within the rising edge of clock signal (CLK1) must be adjusted between safe phase region by Memory Controller 100, fasten these control signals of lock to avoid between the safe phase region of control signal outer and make the mistake.
Between the safe phase region that the rising edge of clock signal (CLK1) is adjusted to command signal CMD (Eye_cmd), block control signal BANK [2:0] safe phase region between (Eye_bank) and address signal A [15:0] safe phase region between within (Eye_addr).Clearly, between the safe phase region of above-mentioned signal, be all less than T, especially the Numerous of address signal A [15:0], so (Eye_addr) is minimum between its safe phase region.
Along with the speed goes of storer (DRAM) module access is fast, from the progress of DDR2 module to DDR3 and DDR4 module.While memory module speed improves, signal quality can significantly reduce, add the difference of the variation of circuit board (PCB) and each pin position of memory module, control signal can be caused to have little bit different by Memory Controller to time of memory module, and rise time (rise time) during signal intensity and fall time (fall time) also different, and cause diminishing between the safe phase region of control signal.
Please refer to Fig. 2 A scheme with Fig. 2 B, its illustrate as the annexation between Memory Controller and two memory modules and control signal eye pattern schematic diagram.When utilizing Memory Controller 200 to control two DDR memory modules 210,220, first clock signal (CLK1) is connected to a DDR memory module 210, second clock signal (CLK2) is connected to the 2nd DDR memory module 220, and shared address signal A [15:0], command signal CMD, block control signal BANK [2:0].One DDR memory module 210 fastens the data on lock address signal A [15:0], command signal CMD, block control signal BANK [2:0] according to the first clock signal (CLK1); 2nd DDR memory module 220 fastens the data on lock address signal A [15:0], command signal CMD, block control signal BANK [2:0] according to the second clock signal (CLK2).
The pin number order necessarily promoting (drive) storer due to Memory Controller 200 is the twice of Figure 1A figure, adds the difference of circuit board (PCB), the quality of signal is worsened more, especially address signal A [15:0].Less compared to the safe phase region shown in Figure 1B, Fig. 2 B, between the safe phase region of especially address signal A [15:0], (Eye_addr) becomes very little.Due to address signal A [15:0] safe phase region between (Eye_addr) very little, make that Memory Controller 200 is more difficult adjusts suitable clock signal (CLK1, CLK2) phase place, allow two DDR memory modules 210,220 correctly fasten lock control signal.
Because the quality of all signals is difficult to be optimized (qualify) one by one at high speeds, so need an effective solution to solve above-mentioned problem.
Summary of the invention
In view of this, the object of the invention is to propose a kind of Memory Controller and signal generating method thereof, the present invention limits the producing method of command signal, and is expanded between the safe phase region of the control signal of part, makes memory module can normal running.
The present invention proposes a kind of signal generating method of Memory Controller, in order to manipulate first memory module, comprises the following steps: to produce the first clock signal that the signal period is a unit interval; Producing the signal period is the command signal of this unit interval, and command signal comprises multiple order bloc, and each order bloc has continuous print first instruction and second instruction; Producing the signal period is the addressing signal group being twice in this unit interval; First signal edge of the first clock signal is set between the safe phase region of command signal; And the secondary signal of the first clock signal edge is set between the safe phase region of command signal and addressing signal group.
The present invention also proposes a kind of Memory Controller, and be connected to first memory module, Memory Controller comprises: clock generating unit, and producing the signal period is that first clock signal of unit time is to first memory module; Control signal translates unit, produce the signal period be the command signal of unit time to first memory module, command signal comprises multiple order bloc, and each this order bloc has continuous print first instruction and the second instruction; And address translation unit, produce the signal period be twice in this unit interval addressing signal group to first memory module; Wherein, the first signal edge of the first clock signal is set between the safe phase region of command signal by clock generating unit; And the secondary signal of the first clock signal edge is set between the safe phase region of command signal and addressing signal group.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment exemplified hereinafter, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Figure 1A and Figure 1B illustrates annexation between Memory Controller and memory module and control signal eye pattern schematic diagram.
Fig. 2 A and Fig. 2 B illustrates annexation between Memory Controller and two memory modules and control signal eye pattern schematic diagram.
Fig. 3 A and Fig. 3 B illustrates according to the Memory Controller of the embodiment of the present invention and the annexation of memory module and control signal eye pattern schematic diagram thereof.
Fig. 4 A and Fig. 4 B illustrates according to the Memory Controller of other embodiments of the invention and the annexation of memory module and control signal eye pattern schematic diagram thereof.
Fig. 5 illustrates the signal generating method process flow diagram of the Memory Controller according to the specific embodiment of the invention.
Symbol description
100,200,400: Memory Controller
110:DDR memory module
210,410: the one DDR memory modules
220,420: the two DDR memory modules
402: address translation unit
404: control signal translates unit
406: clock generating unit
S502 ~ S512: steps flow chart
Embodiment
For two memory modules, control signal comprises the first clock signal (CLK1), the second clock signal (CLK2), command signal CMD, block control signal BANK [2:0] and address signal A [15:0].Command signal CMD comprises write enable signal (WE), column address trigger pip (row address strobe, RAS) and row address trigger pip (column address strobe, CAS).For example, the block control signal of 3 pin positions (pin) is BANK [2:0]; And the address signal of 16 pin positions is A [0:15].Moreover when the composition of crystal grain in memory module (chip) is different, the number of control signal also can be variant.In other words, above-mentioned control signal number is only one embodiment of the present of invention, and it is not used for limiting the present invention.
After DDR memory module receives command signal, the instruction performed according to this comprises without instructions operable (NOP), block bus charging instruction (PRE), drives block bus command (ACT), write instruction (Write) and reading command (Read).
And when NOP instruction, do not need to show interest in (don ' t care) the address signal A [15:0] of 16 pin positions and the block control signal BANK [2:0] of 3 pin positions.That is, when performing NOP instruction, the data on address signal A [15:0] and block control signal BANK [2:0] can be ignored.
In one embodiment, the signal generating method of Memory Controller is developed according to the characteristic of NOP instruction.For example, be an order bloc with two instructions in the command signal CMD exported at Memory Controller.And in order bloc, be sequentially instruction 1 (cmd1) and instruction 2 (cmd2), preferably, instruction 1 (cmd1) can be only NOP instruction; Instruction 2 (cmd2) can be then any one instruction above-mentioned.
Please refer to Fig. 3 A and Fig. 3 B, its illustrate annexation into Memory Controller of the present invention and memory module and control signal eye pattern schematic diagram thereof.Memory Controller 400 comprises address translation unit 402, control signal translates unit 404 and clock generating unit 406.Clock generating unit 406 produces the first clock signal (CLK1), the second clock signal (CLK2); Control signal is translated unit 404 and is produced command signal CMD; And address translation unit 402 produces block control signal BANK [2:0] and address signal A [15:0].The number of the visual DDR memory module of clock generating unit 406, produces a clock signal respectively to other DDR memory module.
As shown in Figure 3A, first clock signal (CLK1) is connected to a DDR memory module 410, second clock signal (CLK2) is connected to the 2nd DDR memory module 420, and a DDR memory module 410 and the 2nd DDR memory module 420 shared address signal A [15:0], command signal CMD, block control signal BANK [2:0].One DDR memory module 210 fastens the data on lock address signal A [15:0], command signal CMD, block control signal BANK [2:0] according to the first clock signal (CLK1); 2nd DDR memory module 220 fastens the data on lock address signal A [15:0], command signal CMD, block control signal BANK [2:0] according to the second clock signal (CLK2).
In this embodiment, the command signal sent at Memory Controller 400 comprises multiple order bloc, all comprises 2 continual commands in each order bloc.As shown in Figure 3 B, first order bloc is sequentially instruction 1 (cmd1), instruction 2 (cmd2); Second order bloc is sequentially instruction 1 ' (cmd1 '), instruction 2 ' (cmd2 '); And the 3rd order bloc is sequentially instruction 1 " (cmd1 "), instruction 2 " (cmd2 ").
In this embodiment, first instruction limited in order bloc can be only NOP instruction, and when DDR memory module 410,420 performs NOP instruction, does not need to show interest in the data on address signal A [0:15] and block control signal BANK [2:0].Preferably, Memory Controller 400 when producing first instruction in order bloc, between the safe phase region that the rising edge of its first clock signal (CLK1) and the second clock signal (CLK2) is not limited to drop on address signal A [0:15] and block control signal BANK [2:0] within Eye_addr and Eye_bank.In other words, Memory Controller 400 is when producing first instruction in order bloc, even if between the safe phase region that the rising edge of the first clock signal (CLK1) and the second clock signal (CLK2) drops on address signal A [0:15] and block control signal BANK [2:0] outside Eye_addr and Eye_bank, do not have any mistake yet and occur.
Please refer to Fig. 3 B, the first clock signal (CLK1) that in Memory Controller 400, clock pulse generator 406 exports is T with the cycle of the second clock signal (CLK2).Further, in Memory Controller 400, control signal translates signal period of command signal CMD that unit 404 exports is T; The block control signal BANK [2:0] that in Memory Controller 400, address translation unit 402 exports, the signal period of address signal A [0:15] are then 2T.It should be noted that, between the safe phase region of address signal A [0:15] and block control signal BANK [2:0], Eye_addr and Eye_bank has become large.
As shown in Figure 3 B, the instruction 1 in the instruction 1 (cmd1) in the first order bloc, instruction in the second order bloc 1 (cmd1 '), the 3rd order bloc is sequentially when time point t0, t2, t4 " (cmd1 ").Between the safe phase region that the rising edge of two clock signals (CLK1, CLK2) is positioned at command signal CMD (Eye_cmd), but between the safe phase region being positioned at address signal A [0:15] and block control signal BANK [2:0] outside Eye_addr and Eye_bank.That is, although two DDR memory modules 410,420 cannot obtain the correct data of address signal A [0:15] and block control signal BANK [2:0] really in the instruction that t0, t2, t4 time point receives, two DDR memory modules 410,420 still can correctly perform NOP instruction.
Further, when time point t1, t3, t5, be sequentially the instruction 2 in the instruction 2 (cmd2) in the first order bloc, instruction in the second order bloc 2 (cmd2 '), the 3rd order bloc " (cmd2 ").Between the safe phase region that the rising edge of two clock signals (CLK1, CLK2) is positioned at command signal CMD (Eye_cmd), block control signal BANK [2:0] safe phase region between Eye_bank, address signal A [0:15] safe phase region between within Eye_addr.It should be noted that, two DDR memory modules 410,420 can obtain the correct data of address signal A [0:15] and block control signal BANK [2:0] really in the instruction that t1, t3, t5 time point receives, and correctly can perform instruction according to this.
From illustrating above, the present embodiment limits Memory Controller can export multiple order bloc, and all has continuous two instructions in each order bloc.First instruction only can be NOP instruction.So, the signal period of its address signal A [0:15] and block control signal BANK [2:0] can be increased to 2T, make Eye_addr and Eye_bank between its safe phase region become large, more easily fasten the data of lock control signal.
It should be noted that, the present invention is not limited to the number only controlling two DDR memory modules.The present invention also may be used for the DDR memory module controlling single DDR memory module or control more than two.
Moreover the present invention is not limited to the signal period of address signal A [0:15] and block control signal BANK [2:0] all be increased to 2T simultaneously.Also can according to actual needs, only the signal period of address signal A [0:15] is increased to 2T, and is maintained T the signal period of block control signal BANK [2:0], its coherent signal waveform is as shown in Figure 4 A.
Or only the signal period of block control signal BANK [2:0] is increased to 2T, and is maintained T the signal period of address signal A [0:15], its coherent signal waveform as shown in Figure 4 B.
Please refer to Fig. 5, its illustrate signal generating method process flow diagram into Memory Controller of the present invention.First, the first clock signal (step S502) that the signal period is a unit interval is produced; Produce the command signal that the signal period is a unit interval, comprise multiple order bloc in command signal, each order bloc has continuous print first instruction, second instruction (step S504); Producing the signal period is two unit interval addressing signal group (step S506).Addressing signal group can be address signal A [0:15] and/or block control signal BANK [2:0] addressing signal group.
First of first clock signal signal edge is set between the safe phase region of command signal by clock generating unit 406, performs first instruction (step S510) to make DDR memory module; Second of first clock signal signal edge is set between the safe phase region of command signal, addressing signal group, performs second instruction (step S512) to make DDR storer.
According to the method for Fig. 5, when step S510 is to after step S512 executes, representative has performed an order bloc; And when again getting back to step S510, namely representative performs next instruction group.Wherein, an above-mentioned unit interval is the first clock cycle, and first instruction in order bloc is only NOP instruction.
From illustrating above, the signal period of address signal A [0:15] or block control signal BANK [2:0] is also extended for two unit interval to expand between its safe phase region by the order bloc that collocation embodiment discloses.So, Memory Controller correctly control DDR memory module can be made, and solve problem too little between known as memory device signals security phase region, and the stiffness of system that can strengthen along with memory access clock pulse speed increases day by day and access usefulness.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when defining with claims.

Claims (20)

1. a signal generating method for Memory Controller, in order to manipulate a first memory module, the method comprises the following steps:
Produce one first clock signal that the signal period is a unit interval;
Produce the command signal that the signal period is this unit interval, wherein, this command signal comprises multiple order bloc, and each this order bloc has continuous print one first instruction and one second instruction;
Producing the signal period is the addressing signal group being twice in this unit interval;
One first signal edge of this first clock signal is set between the safe phase region of this command signal; And
One secondary signal edge of this first clock signal is set between the safe phase region of this command signal and this addressing signal group.
2. signal generating method as claimed in claim 1, is characterized in that, also in order to manipulate a second memory module, comprise the following steps:
Produce one second clock signal that the signal period is this unit interval;
One first signal edge of this second clock signal is set between the safe phase region of this command signal; And
One secondary signal edge of this second clock signal is set between the safe phase region of this command signal and this addressing signal group.
3. signal generating method as claimed in claim 2, it is characterized in that, this first memory module and this second memory module are all double data rate memory module.
4. signal generating method as claimed in claim 1, is characterized in that, this unit interval is cycle of this first clock pulse.
5. signal generating method as claimed in claim 1, it is characterized in that, this addressing signal group comprises an address signal and a block control signal.
6. signal generating method as claimed in claim 1, is characterized in that, this first instruction is one without instructions operable.
7. signal generating method as claimed in claim 1, is characterized in that, this second instruction be one without instructions operable, a block bus charging instruction, drive block bus command, write instruction and a reading command one of them.
8. signal generating method as claimed in claim 1, is characterized in that, the first signal of this first clock signal is along outside between the safe phase region being positioned at this addressing signal group.
9. signal generating method as claimed in claim 1, is characterized in that, the first signal edge of this first clock signal, secondary signal edge are all the rising edge of this first clock signal.
10. signal generating method as claimed in claim 1, is characterized in that, this addressing signal group is either-or in an address signal and a block control signal.
11. signal generating methods as claimed in claim 10, it is characterized in that, when this addressing signal group is this address signal, the signal period of this block control signal is a unit interval, and is set between the safe phase region of this block control signal in this first signal edge of this first clock signal and this secondary signal edge.
12. signal generating methods as claimed in claim 10, it is characterized in that, when this addressing signal group is this block control signal, the signal period of this address signal is a unit interval, and is set between the safe phase region of this address signal in this first signal edge of this first clock signal and this secondary signal edge.
13. 1 kinds of Memory Controllers, can be connected to a first memory module, this Memory Controller comprises:
One clock generating unit, producing the signal period is that one first clock signal of a unit interval is to this first memory module;
One control signal translates unit, produce the signal period be a command signal of this unit interval to this first memory module, wherein, this command signal comprises multiple order bloc, and each this order bloc has continuous print one first instruction and one second instruction; And
One address translation unit, producing the signal period is that an addressing signal group of two times of these unit interval is to this first memory module;
Wherein, one first signal edge of this first clock signal is set between the safe phase region of this command signal by this clock generating unit; And a secondary signal edge of this first clock signal is set between the safe phase region of this command signal and addressing signal group.
14. Memory Controllers as claimed in claim 13, is characterized in that, be also connected to a second memory module, and this clock generating unit produces one second clock signal that the signal period is this unit interval; Wherein, one first signal edge of this second clock signal is set between the safe phase region of this command signal by this clock generating unit; And a secondary signal edge of this second clock signal is set between the safe phase region of this command signal and this indicator signal.
15. Memory Controllers as claimed in claim 14, is characterized in that, this first memory module and this second memory module are all double data rate memory module.
16. Memory Controllers as claimed in claim 13, is characterized in that, this unit interval is the one-period of this first clock pulse.
17. Memory Controllers as claimed in claim 13, is characterized in that, this addressing signal group comprises an address signal and a block control signal.
18. Memory Controllers as claimed in claim 13, is characterized in that, this first instruction is one without instructions operable.
19. Memory Controllers as claimed in claim 13, is characterized in that, this second instruction be one without instructions operable, a block bus charging instruction, drive block bus command, a write instruction and a reading command one of them.
20. Memory Controllers as claimed in claim 13, is characterized in that, the first signal of this first clock signal is along outside between the safe phase region being positioned at this addressing signal group.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111161772A (en) * 2018-11-07 2020-05-15 瑞昱半导体股份有限公司 Memory signal phase difference correction circuit and method
CN112309445A (en) * 2019-08-01 2021-02-02 群联电子股份有限公司 Memory interface circuit, memory storage device and signal generating method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030065465A1 (en) * 2000-08-14 2003-04-03 Brian Johnson Method and apparatus providing improved data path calibration for memory devices
US6944738B2 (en) * 2002-04-16 2005-09-13 Sun Microsystems, Inc. Scalable design for DDR SDRAM buses
WO2006023387A1 (en) * 2004-08-20 2006-03-02 Rambus Inc. Individual data line strobe-offset control in memory systems
CN1838307A (en) * 2005-03-04 2006-09-27 英飞凌科技股份公司 Chip to chip interface including assymetrical transmission impedances
CN101699560A (en) * 2009-09-30 2010-04-28 曙光信息产业(北京)有限公司 Memory controller and multi-memory system
CN102117244A (en) * 2010-01-05 2011-07-06 上海硅知识产权交易中心有限公司 Control structure supporting double data rate (DDR) addressing of audio and video intellectual property (IP) cores

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030065465A1 (en) * 2000-08-14 2003-04-03 Brian Johnson Method and apparatus providing improved data path calibration for memory devices
US6944738B2 (en) * 2002-04-16 2005-09-13 Sun Microsystems, Inc. Scalable design for DDR SDRAM buses
WO2006023387A1 (en) * 2004-08-20 2006-03-02 Rambus Inc. Individual data line strobe-offset control in memory systems
CN1838307A (en) * 2005-03-04 2006-09-27 英飞凌科技股份公司 Chip to chip interface including assymetrical transmission impedances
CN101699560A (en) * 2009-09-30 2010-04-28 曙光信息产业(北京)有限公司 Memory controller and multi-memory system
CN102117244A (en) * 2010-01-05 2011-07-06 上海硅知识产权交易中心有限公司 Control structure supporting double data rate (DDR) addressing of audio and video intellectual property (IP) cores

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111161772A (en) * 2018-11-07 2020-05-15 瑞昱半导体股份有限公司 Memory signal phase difference correction circuit and method
CN112309445A (en) * 2019-08-01 2021-02-02 群联电子股份有限公司 Memory interface circuit, memory storage device and signal generating method
CN112309445B (en) * 2019-08-01 2023-10-13 群联电子股份有限公司 Memory interface circuit, memory storage device and signal generation method

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