CN104182357B - Memory controller and signal generating method of memory controller - Google Patents
Memory controller and signal generating method of memory controller Download PDFInfo
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- CN104182357B CN104182357B CN201310195213.XA CN201310195213A CN104182357B CN 104182357 B CN104182357 B CN 104182357B CN 201310195213 A CN201310195213 A CN 201310195213A CN 104182357 B CN104182357 B CN 104182357B
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Abstract
The invention provides a memory controller and a signal generating method of the memory controller. The signal generating method provided by the invention is characterized in that the generating sequence of instruction signals is optimized, and in addition, safe phase intervals of partial address signals are enlarged for carrying out DDR memory module accessing. The memory controller and the signal generating method of the memory controller have the advantages that the memory controller can normally control a DDR memory module, in addition, the problem of too small signal safe phase interval of the existing memory is solved, and in addition, the accessing efficacy and the system stability degree gradually increased along with the accessing clock speed acceleration of the memory can be enhanced.
Description
Technical field
The invention relates to memory area, and in particular to a kind of Memory Controller and its signal generation side
Method.
Background technology
In general, Memory Controller (memory controller) is connected to memory module, can write data
Memory module or by reading data in memory module.Most common memory module is double data rate now
(double data rate, hereinafter referred to as DDR) memory module.
Refer to Figure 1A and Figure 1B, its depicted annexation between Memory Controller and memory module and
Control signal eye pattern (eye diagram) schematic diagram.Memory Controller 100 is to be designed at circuit with DDR memory module 110
On plate (PCB), its control signal at least includes：Clock signal (CLK1), address signal (A), command signal (CMD), block control
Signal (BANK) processed.Command signal (CMD) includes：Write enable signal (WE), column address trigger (row address
Strobe, RAS), row address trigger (column address strobe, CAS).The block control letter of 3 foot positions (pin)
Number BANK [2:0], the address signal A [15 of 16 foot positions:0].
Memory Controller 100 manipulates DDR memory module 110 using control signal, for example, reads data, write
Data etc..As DDR memory module 110 is the signal edge (such as rising edge or falling edge) according to clock signal (CLK1)
The data come in latch address signal (A), command signal (CMD), block control signal (BANK).Therefore, Memory Controller
100 phase places (phase) that must suitably adjust clock signal (CLK1) so that DDR memory module 110 is able to according to seasonal pulse
The signal edge of signal (CLK1) and successfully there is the data in control signal in latch (latch) residence.For convenience of explanation, below
Latch signal is come with the rising edge of clock signal (CLK1) all, but is not limited to this.
As illustrated, the cycle of clock signal (CLK1) is T, address signal (A), command signal (CMD), block control letter
The signal period of number (BANK) is also T.However, due to the driving force of each control signal it is different, so control signal
Safe phase place interval (or referred to as data valid interval) can be less than T.Therefore, Memory Controller 100 must be by clock signal
(CLK1) rising edge is adjusted within safe phase place interval, with avoid outside the safe phase place interval of control signal latch this
A little control signals and cause mistake.
As illustrated, the rising edge of clock signal (CLK1) is adjusted to the safe phase place interval (Eye_ of command signal (CMD)
Cmd), safe phase place interval (Eye_bank) of block control signal (BANK), and the safe phase place of address signal (A) it is interval
(Eye_addr) within., it is clear that the safe phase place of above-mentioned signal is interval to be smaller than T, the especially number of address signal (A)
It is numerous, so its safe phase place interval (Eye_addr) is minimum.
With memorizer (DRAM) module access speed it is more and more faster, from the progress of DDR2 modules to DDR3 modules.Can
That signal quality can be greatly reduced while memory module speed is improved, along with circuit board (PCB) variation and deposit
The difference of each foot position of memory modules, can cause control signal to have a little by the time of Memory Controller to memory module
Difference, and the rise time (rise time) during signal intensity and fall time (fall time) increase, and cause control
Diminish between the safe phase region of signal.
Fig. 2A and Fig. 2 B are refer to, its depicted annexation between Memory Controller and two memory modules
And control signal eye pattern schematic diagram.Two DDR memory modules 210,220 are controlled using a Memory Controller 200
When, the first clock signal (CLK1) is connected to the first DDR memory module 210, and the second clock signal (CLK2) is connected to second
DDR memory module 220, and shared address signal (A), command signal (CMD), block control signal (BANK).That is, first
DDR memory module 210 is according to the first clock signal (CLK1) latch address signal (A), command signal (CMD), block control
Data on signal (BANK)；Second DDR memory module 220 according to the second clock signal (CLK2) latch address signal (A),
Data in command signal (CMD), block control signal (BANK).
As Memory Controller 200 necessarily promotes the pin number mesh of (Drive) memorizer for the twice of Figure 1A, then plus
The variation of upper circuit board (PCB) and the difference of two memorizer (DRAM) foot positions, can be such that the quality of signal more deteriorates, especially
Address signal (A) and more deteriorate.Compared to Figure 1B, the safe phase region shown in Fig. 2 B is less, especially address signal (A)
Safe phase place interval (Eye_addr) has become very little.That is, due to the safe phase place interval (Eye_ of address signal (A)
Addr) very little so that Memory Controller 200 is more difficult to adjust out appropriate clock signal (CLK1, CLK2) phase place, allows two
Individual DDR memory module 210,220 smooth latch signals.
As the quality of all signals is difficult to be optimized (qualify) one by one at high speeds, so needing one
Individual effective solution is above-mentioned to solve the problems, such as.
The content of the invention
In view of this, it is an object of the invention to propose a kind of Memory Controller and its signal generating method, the present invention
The producing method of command signal is limited, and the safe phase place interval of the address signal of part is expanded so that memorizer mould
Block can be with normal operating.
In order to achieve the above object, according to a kind of signal generating method of Memory Controller proposed by the invention, to grasp
Control first memory module, comprises the following steps：The generation signal period is first clock signal of a unit interval, block control
The address signal of signal and Part I；Produce the command signal that the signal period is the unit interval, wherein, the command signal bag
Include multiple instruction group, each order bloc has continuous first instruction, the second instruction, the 3rd instruction, and the 4th instruction；Produce
Signal period is the address signal of a Part II of two times of unit interval；First signal edge of first clock signal is set
It is interval due to the safe phase place of the address signal of the command signal, the block control signal and the Part I；By this first when
The secondary signal edge of arteries and veins signal be set in the command signal, the block control signal, the address signal of the Part I and this
The safe phase place of two partial address signals is interval；3rd signal edge of first clock signal is set in into command signal, block
Control signal is interval with the safe phase place of the address signal of Part I；And the 4th signal edge of the first clock signal is set
It is interval in the safe phase place of the address signal of command signal, block control signal, the address signal of Part I and Part II.
The present invention more proposes a kind of Memory Controller, is connected to first memory module, and Memory Controller includes：When
Arteries and veins generation unit, generation signal period are first clock signal of a unit interval to first memory module；Control signal turns
Unit is translated, the generation signal period is the command signal of the unit interval to first memory module, wherein, bag in the command signal
Multiple instruction group is included, each order bloc has continuous first instruction, the second instruction, the 3rd instruction and the 4th instruction；And,
Address translation unit, generation signal period are the block control signal of the unit interval and the address signal of Part I to this
First memory module, and the address signal of the Part II that the signal period is two times of unit interval is produced to the first storage
Device module.Clock generating unit by the first signal edge of the first clock signal be set in command signal, block control signal and
The safe phase place of the address signal of Part I is interval；The secondary signal edge of the first clock signal is set in into command signal, area
The safe phase place of block control signal, the address signal of Part I and Part II address signal is interval；First seasonal pulse is believed
Number the 3rd signal edge be set in command signal, block control signal and Part I address signal safe phase region
Between；And the 4th signal edge of the first clock signal is set in the address letter of command signal, block control signal, Part I
Number and Part II address signal safe phase place it is interval.
Description of the drawings
It is that the above objects, features and advantages of the present invention can be become apparent, below in conjunction with tool of the accompanying drawing to the present invention
Body embodiment elaborates, wherein：
The depicted annexations and control signal between Memory Controller and memory module of Figure 1A and Figure 1B
Eye pattern schematic diagram.
The depicted annexations and control between Memory Controller and two memory modules of Fig. 2A and Fig. 2 B
Signal eye diagram schematic diagram.
Instruction and the data schematic diagram of corresponding control signal that DDR memory module depicted in Fig. 3 is performed.
It is the company of the Memory Controller according to the specific embodiment of the invention and memory module depicted in Fig. 4 A and Fig. 4 B
Connect relation and its control signal eye pattern schematic diagram.
It is the signal generating method flow chart of the Memory Controller according to the specific embodiment of the invention depicted in Fig. 5.
100、200、400：Memory Controller
110：DDR memory module
210、410：First DDR memory module
220、420：Second DDR memory module
402：Address translation unit
404：Control signal translates unit
406：Clock generating unit
S502～S516：Steps flow chart
Specific embodiment
The control signal of DDR memory module includes：First clock signal (CLK1), the second clock signal (CLK2), refer to
Make signal (CMD), block control signal (BANK), and address signal (A).Command signal (CMD) includes：Write enable signal
(WE), column address trigger (row address strobe, RAS), row address trigger (column address
Strobe, CAS).For example, the block control signal (BANK) of 3 foot positions (pin) is BANK [2:0]；And the ground of 16 foot positions
Location signal (A) includes the tenth address signal A [10], and other address signals A [0 according to function classification:9] with A [11:15].
Fig. 3 is refer to, instruction and the data schematic diagram of corresponding control signal that DDR memory module depicted in which is performed.
Command signal includes：Without instructions operable (NOP), block bus charging instruction (PRE), drive block bus command (ACT), write
Instruction (Write) and reading instruction (Read).
In NOP instruction, it is not required to show interest in the address signal A [15 of (don ' t care) 16 foot positions:0] and 3 foot positions area
Block control signal BANK [2:0].That is, when performing NOP instruction, negligible address signal A [15:0] and block control signal
BANK[2:0] data on.
When PRE is instructed, need to be in block control signal BANK [2:Live data is provided on 0], and in the tenth address signal A
[10] data of logical zero is provided.And other address signals A [0:9] with A [11:15] then it is not required to show interest in.
When ACT is instructed, need to be in block control signal BANK [2:Live data is provided on 0], and in the address of 16 foot positions
Signal A [15:0] provide live data.
When Write and Read is instructed, need to be in block control signal BANK [2:0] live data is provided on, in 11 foot positions
Address signal A [11] and A [9:Live data is provided on 0], and the data of logical zero is provided in the tenth address signal A [10].
And the address signal A [15 that 4 feet are:12] then it is not required to show interest in.
Order property according to more than, when NOP instruction and PRE are instructed, DDR memory module is not required to show interest in which
He is address signal A [0:9] with A [11:15] data on.In a specific embodiment, in the instruction of Memory Controller output
In signal (CMD), system is with four instructions as an order bloc.And four instruction in regular turn for instruction 1 (cmd1), instruction 2 (cmd2),
3 (cmd3) of instruction, 4 (cmd4) of instruction, wherein, when instructing 1 (cmd1) with instruction 3, are only capable of producing NOP instruction or PRE refer to
Order；And when instructing 2 (cmd2) with instruction 4 (cmd4), then can produce any of the above-described kind of instruction.
Refer to Fig. 4 A and Fig. 4 B, which is depicted be Memory Controller of the present invention and memory module annexation and
Its control signal eye pattern (eye diagram) schematic diagram.Include address translation unit 402, control letter in Memory Controller 400
Number translation unit 404 and clock generating unit 406.Clock generating unit 406 produce the first clock signal (CLK1), second when
Arteries and veins signal (CLK2)；Control signal translation unit 404 produces command signal (CMD)；And address translation unit 402 produces block control
Signal (BANK) processed and address signal (A).The number of 406 visual DDR memory module of clock generating unit, produces one respectively
Individual clock signal is to individual other DDR memory module.
As shown in Figure 4 A, the first clock signal (CLK1) is connected to the first DDR memory module 410, the second clock signal
(CLK2) it is connected to the second DDR memory module 420, and the first DDR memory module 410 and the second DDR memory module 420
Shared address signal (A), command signal (CMD), block control signal (BANK).That is, the first DDR memory module 210
According to the data in the first clock signal (CLK1) latch address signal (A), command signal (CMD), block control signal (BANK)；
Second DDR memory module 220 is according to the second clock signal (CLK2) latch address signal (A), command signal (CMD), block
Data in control signal (BANK).
In a specific embodiment, the command signal sent in Memory Controller 400 includes multiple instruction group, each
All include 4 continual commands in order bloc.As shown in Figure 4 B, first order bloc is sequentially instruction 1 (cmd1), instruction 2
(cmd2) 3 (cmd3), 4 (cmd4) of instruction, are instructed；Second order bloc be sequentially instruction 1 ' (cmd1 '), 2 ' (cmd2 ') of instruction,
3 ' (cmd3 ') of instruction, 4 ' (cmd4 ') of instruction.
In this embodiment, first instruction limited in order bloc can only be NOP instruction and PRE with the 3rd instruction
One of instruction, and when the execution NOP instruction of DDR memory module 410,420 and PRE instructions, be not required to show interest in other addresses letters
Number A [0:9] with A [11:15] data on.It is preferred that Memory Controller 400 produce order bloc in first instruction with
During the 3rd instruction, its first clock signal (CLK1) is not limited to fall with the rising edge of the second clock signal (CLK2)
Other address signals A [0:9] with A [11:15] within safe phase place interval (Eye_other_addr).In other words, store
Device controller 400 produce order bloc in first instruction with the 3rd instruction when, even if the first clock signal (CLK1) with
The rising edge of the second clock signal (CLK2) falls in other address signals A [0:9] with A [11:15] safe phase place interval (Eye_
Other_addr, outside), there will not be any mistake and occur.
Refer to Fig. 4 B, the first clock signal (CLK1) that clock pulse generator 406 is exported in Memory Controller 400 with
The cycle of the second clock signal (CLK2) is T.Also, the finger of the control signal translation output of unit 404 in Memory Controller 400
The signal period for making signal (CMD) is T；The block control signal of the output of address translation unit 402 in Memory Controller 400
BANK[2:0], the signal period of the tenth address signal A [10] is T.And address translation unit 404 is defeated in Memory Controller 400
Other address signals A [0 for going out:9] with A [11:15] signal period is then 2T, it is noted that other address signals A [0:9]
With A [11:15] safe phase place interval (Eye_other_addr) has become big.
As shown in Figure 4 B, be sequentially in time point t0, t2, t4, t6 instruction 1 (cmd1) in the first order bloc, first
The instruction 1 ' (cmd1 ') in instruction 3 (cmd3), the second order bloc in order bloc, the instruction 3 ' in the second order bloc
(cmd3’).Now.The safe phase place that the rising edge of two clock signals (CLK1, CLK2) is located at command signal (CMD) is interval
(Eye_cmd), safe phase place interval (Eye_bank) of block control signal (BANK), and the tenth address signal (A [10])
Safe phase place interval (Eye_a10) within；But it is located at other address signals A [0:9] with A [11:15] safe phase region
Between outside (Eye_other_addr).That is, although two DDR memory modules 410,420 are in t0, t2, t4, t6 time point institute
The instruction of reception cannot obtain address signal A [0 really:9] with A [11:15] correct data, but two DDR memory moulds
Block 410,420 can correctly perform NOP instruction or PRE instructions.
Further, be sequentially when time point t1, t3, t5, t7 instruction 2 (cmd2) in the first order bloc, first
The instruction 2 ' (cmd2 ') in instruction 4 (cmd4), the second order bloc in order bloc, the instruction 4 ' in the second order bloc
(cmd4’).The rising edge of two clock signals (CLK1, CLK2) is located at the safe phase place interval (Eye_ of command signal (CMD)
Cmd), safe phase place interval (Eye_bank) of block control signal (BANK), the safe phase place of the tenth address signal (A [10])
Interval (Eye_a10) and other address signals A [0:9] with A [11:15] safe phase place interval (Eye_other_addr) it
It is interior.It should be noted that two DDR memory modules 410,420 can be obtained really in the instruction received by t1, t3, t5, t7 time point
To other address signals A [0:9] with A [11:15] correct data, it is possible to correctly execute instruction according to this.
From described above, the present embodiment limits Memory Controller and is only capable of exporting multiple instruction group, and each instruction
All there are continuous four instructions in group.First instruction and second instruction can only be one of NOP instruction and PRE instructions.Such as
This, can be by other address signals A [0:9] with A [11:15] signal period increases as 2T so that its safe phase place interval (Eye_
Other_addr) become big, it is easier to the data of latch control signal.
It should be noted that the present invention is not limited to only control the number of two DDR memory modules.The present invention can also be used
In the DDR memory module for controlling single DDR memory module or control more than two.
Fig. 5 is refer to, its depicted signal generating method flow chart for Memory Controller of the present invention.It is concrete real in one
Apply in example, address signal is divided into two parts, the address signal of Part I is the tenth address signal A [10], and the
The address signal of two parts is other address signals A [0:9] with A [11:15].
First, the first clock signal, block control signal and Part I that the signal period is a unit interval are produced
Address signal (step S502)；The command signal that the signal period is a unit interval is produced, is included in command signal many
Individual order bloc, each order bloc have it is continuous first instruction, second instruction, the 3rd instruction, and the 4th instruction
(step S504)；Produce the address signal (step S506) of the Part II that the signal period is two unit interval.
First signal edge of the first clock signal is set in command signal, block control letter by clock generating unit 406
Number, and Part I address signal safe phase place interval (step S510) so that DDR memory module performs first
Instruction；Second signal edge of the first clock signal is set in into the address letter of command signal, block control signal, Part I
Number, and Part II address signal safe phase place interval (step S512) so that DDR memory performs second instruction；
3rd signal edge of the first clock signal is set in into the address signal of command signal, block control signal and Part I
Safe phase place interval (step S514) so that DDR memory module performs the 3rd instruction；And, the first seasonal pulse is believed
Number the 4th signal edge be set in the ground of command signal, block control signal, the address signal of Part I and Part II
Safe phase place interval (step S516) of location signal, so that DDR memory module performs the 4th instruction.
According to the method for Fig. 5, after step S510 has been performed to step S516, representative has performed an order bloc；And
When turning again to step S510, that is, represent and perform next instruction group.Wherein, an above-mentioned unit interval is the first seasonal pulse week
First instruction and the 3rd instruction system in phase, and order bloc instructs one of them for NOP instruction with PRE.
Explanation from more than, the order bloc of embodiment of arranging in pairs or groups disclosure by other memory signals A [0:9] and A
[11:15] it is interval to expand its safe phase place that signal period is extended for two unit interval.Thus, memorizer can be caused to control
Device normally controls DDR memory module, and solves the problems, such as that known as memory device signals security phase place is interval too little, and can increase
The strong stiffness of system increasingly increased with memory access seasonal pulse speed and access efficiency.
Although the present invention is disclosed as above with preferred embodiment, so which is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect, therefore the protection model of the present invention
Enclose when by being defined that claims are defined.
Claims (18)
1. a kind of signal generating method of Memory Controller, to manipulate a first memory module, the method includes following
Step：
Produce the ground of one first clock signal, a block control signal and a Part I that the signal period is a unit interval
Location signal；
The command signal that the signal period is the unit interval is produced, wherein, the command signal includes multiple instruction group, each
The order bloc has continuous 1 first instruction, one second instruction, one the 3rd instruction and one the 4th instruction；
Produce the address signal of the Part II that the signal period is two times of unit interval；
One first signal edge of first clock signal is set in into the command signal, the block control signal and this first
The safe phase place of the address signal for dividing is interval；
One secondary signal edge of first clock signal is set in into the command signal, the block control signal, the Part I
Address signal and the Part II address signal safe phase place it is interval；
One the 3rd signal edge of first clock signal is set in into the command signal, the block control signal and this first
The safe phase place of the address signal for dividing is interval；And
One the 4th signal edge of first clock signal is set in into the command signal, the block control signal, the Part I
Address signal and the Part II address signal safe phase place it is interval.
2. signal generating method as claimed in claim 1, more to manipulate a second memory module, comprises the following steps：
Produce one second clock signal that the signal period is the unit interval；
One first signal edge of second clock signal is set in into the command signal, the block control signal and this first
The safe phase place of the address signal for dividing is interval；
One secondary signal edge of second clock signal is set in into the command signal, the block control signal, the Part I
Address signal and the Part II address signal safe phase place it is interval；
One the 3rd signal edge of second clock signal is set in into the command signal, the block control signal and this first
The safe phase place of the address signal for dividing is interval；And
One the 4th signal edge of second clock signal is set in into the command signal, the block control signal, the Part I
Address signal and the Part II address signal safe phase place it is interval.
3. signal generating method as claimed in claim 2, it is characterised in that the first memory module and the second memory
Module is all double data rate memory module.
4. signal generating method as claimed in claim 1, it is characterised in that the unit interval is of first seasonal pulse all
Phase.
5. signal generating method as claimed in claim 1, it is characterised in that the Part I address signal is 1 the tenth address
Signal；And the Part II address signal is zero-address signal to the 9th address signal and the 11st address signal to the tenth
Five address signals.
6. signal generating method as claimed in claim 1, it is characterised in that first instruction is with the 3rd instruction for without fortune
Make one of instruction and a block bus charging instruction.
7. signal generating method as claimed in claim 1, it is characterised in that second instruction is with the 4th instruction for without fortune
Instruct, a block bus charging instruction, a driving block bus command, a write instruction read one of instruction with one.
8. signal generating method as claimed in claim 1, it is characterised in that the first signal edge of first clock signal and
Three signal edge are can be located at outside the safe phase place interval of the address signal of the Part II.
9. signal generating method as claimed in claim 1, it is characterised in that the first signal edge of first clock signal,
Binary signal edge, the 3rd signal edge and the 4th signal edge are all the rising edge of first clock signal.
10. a kind of Memory Controller, is connected to a first memory module, and the Memory Controller includes：
One clock generating unit, generation signal period are one first clock signal of a unit interval to the first memory mould
Block；
One control signal translates unit, and the generation signal period is a command signal of the unit interval to the first memory mould
Block, wherein, the command signal includes multiple instruction group, and there is each order bloc continuous 1 first instruction, one second to refer to
Make, one the 3rd instruction is instructed with one the 4th；And
One address translation unit, produces a block control signal and the ground of a Part I that the signal period is the unit interval
Location signal is to the first memory module, and produces the address letter of the Part II that the signal period is two times of unit interval
Number to the first memory module；
Wherein, one first signal edge of first clock signal is set in the command signal, the block by the clock generating unit
The safe phase place of the address signal of control signal and the Part I is interval；By a secondary signal edge of first clock signal
It is set in the command signal, the block control signal, the address signal of the Part I and the Part II address signal
Safe phase place is interval；By one the 3rd signal edge of first clock signal be set in the command signal, the block control signal with
And the safe phase place of the address signal of the Part I is interval；And one the 4th signal edge of first clock signal is set in
The safety of the command signal, the address signal of the block control signal, the address signal of the Part I and the Part II
Phase place is interval.
11. Memory Controllers as claimed in claim 10, which is further connected to a second memory module, and the seasonal pulse is produced
Unit produces one second clock signal that the signal period is the unit interval；Wherein, the seasonal pulse is produced second clock signal
One first signal edge be set in the command signal, the block control signal and the Part I address signal safe phase
Position is interval；By a secondary signal edge of second clock signal be set in the command signal, the block control signal, this first
The address signal for dividing and the safe phase place of the Part II address signal are interval；By one the 3rd signal of second clock signal
The safe phase place that edge is set in the address signal of the command signal, the block control signal and the Part I is interval；And,
One the 4th signal edge of second clock signal is set in into the ground of the command signal, the block control signal, the Part I
The safe phase place of the address signal of location signal and the Part II is interval.
12. Memory Controllers as claimed in claim 11, it is characterised in that the first memory module and second storage
Device module is all double data rate memory module.
13. Memory Controllers as claimed in claim 10, it is characterised in that the unit interval is of first seasonal pulse
Cycle.
14. Memory Controllers as claimed in claim 10, it is characterised in that the Part I address signal is 1 the tenth ground
Location signal；And the Part II address signal is zero-address signal to the 9th address signal and the 11st address signal to the
15 address signals.
15. Memory Controllers as claimed in claim 10, it is characterised in that first instruction is a nothing with the 3rd instruction
One of instructions operable and a block bus charging instruction.
16. Memory Controllers as claimed in claim 10, it is characterised in that second instruction is a nothing with the 4th instruction
Instructions operable, a block bus charging instruction, one drive block bus command, a write instruction with one read instruction wherein it
One.
17. Memory Controllers as claimed in claim 10, it is characterised in that first seasonal pulse is believed by the clock generating unit
Number first signal edge and the 3rd signal edge address signal that is set in the Part II safe phase place interval outside.
18. Memory Controllers as claimed in claim 10, it is characterised in that the first signal edge of first clock signal,
Secondary signal edge, the 3rd signal edge and the 4th signal edge are all the rising edge of first clock signal.
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