CN101699560A - Memory controller and multi-memory system - Google Patents
Memory controller and multi-memory system Download PDFInfo
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- CN101699560A CN101699560A CN200910235298A CN200910235298A CN101699560A CN 101699560 A CN101699560 A CN 101699560A CN 200910235298 A CN200910235298 A CN 200910235298A CN 200910235298 A CN200910235298 A CN 200910235298A CN 101699560 A CN101699560 A CN 101699560A
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Abstract
The invention provides a memory controller and a multi-memory system, the memory controller comprises a double data rate DDR controller and at least one signal register, wherein the DDR controller is used for producing memory driving signals according to an instruction of a central processing unit, and the memory driving signals comprise first signal line groups and second signal line groups, wherein each second signal line group is applicable to being connected with two memory particles in the corresponding memory; the signal register is used for carrying out power amplification and shaping on the first signal line groups outputted by the DDR controller, wherein each first signal line group after the power amplification and the shaping is applicable to being connected with each memory particle in the corresponding memory. The memory controller and the multi-memory system can enhance the driving ability of the memory controller and reduce the cost of the system.
Description
Technical field
The present invention relates to the computer hardware technology field, relate more specifically to Memory Controller Hub and multi-memory system.
Background technology
Owing to signal intensity decays along with signal wire length prolongs, and through a DIMM (Dual InLine Memory Module, two memory body modules in upright arrangement) signal has than high attenuation after the slot, therefore DDR2 (Double Date Rate, the double data-carrier store) controller of a standard can only drive 2 DIMM internal memories.System for many internal memories of needs just needs to use a plurality of Memory Controller Hub, and these Memory Controller Hub not only take more space, also can bring the raising of product price.
Control more internal memory in order to use less Memory Controller Hub, can adopt increases signal and deposits mode on memory bar, promptly use RDIMM (Registered Dual Inline MemoryModule) to come alternate standard DIMM, thereby make single memory bar weaken, reach the purpose that single controller drives many internal memories the requirement of signal intensity.But this RDIMM market demand is little, and shipment amount is few, and procurement cycle is long, and price is far above DIMM.
Therefore, need at present a kind ofly can control more internal memories and the less Memory Controller Hub of cost.
Summary of the invention
In order one of to address the above problem, the present invention proposes a kind of Memory Controller Hub, comprise double data rate (DDR) controller and at least one sign register.Wherein, the DDR controller is used for producing the internal memory drive signal according to the instruction of central processing unit, the internal memory drive signal comprises first signal line group and secondary signal line group, and wherein each is organized described secondary signal line group and is suitable for being connected with two internal memory particles in the corresponding internal memory; Sign register is used for first signal line group of DDR controller output is carried out power amplification and shaping, and wherein each group is suitable for being connected with each internal memory particle in the corresponding internal memory through first signal line group of power amplification and shaping.
According to embodiments of the invention, first signal line group comprises that address area selection wire in chip selection signal line, the internal memory particle, address wire, row address selection signal, column address selection signal, written allowance signal, clock signal, clock allow signal, on-die termination device modelled signal.
According to embodiments of the invention, secondary signal line group comprises data input/output line, data mask control line and data strobe signal line.
According to embodiments of the invention, the output terminal of DDR controller comprises at least one group first signal line group, and the input end of each sign register is connected with one group of described first signal line group.
According to embodiments of the invention, internal memory comprises dual inline memory module (DIMM).
According to embodiments of the invention, DDR controller and sign register are arranged on the motherboard.
The invention allows for a kind of multi-memory system, comprise Memory Controller Hub and internal memory, Memory Controller Hub comprises double data rate (DDR) controller and at least one sign register.Wherein, the DDR controller is used for producing the internal memory drive signal according to the instruction of central processing unit, the internal memory drive signal comprises first signal line group and secondary signal line group, and wherein each group secondary signal line group is suitable for being connected with two internal memory particles in the corresponding internal memory; Sign register is used for first signal line group of described DDR controller output is carried out power amplification and shaping, and wherein each group is suitable for being connected with each internal memory particle in the corresponding internal memory through first signal line group of power amplification and shaping.
According to embodiments of the invention, first signal line group comprises that address area selection wire in chip selection signal line, the internal memory particle, address wire, row address selection signal, column address selection signal, written allowance signal, clock signal, clock allow signal, on-die termination device modelled signal.
According to embodiments of the invention, secondary signal line group comprises data input/output line, data mask control line and data strobe signal line.
According to embodiments of the invention, the output terminal of DDR controller comprises at least one group first signal line group, and the input end of each sign register is connected with one group of first signal line group.
According to embodiments of the invention, internal memory comprises dual inline memory module (DIMM).
According to embodiments of the invention, DDR controller and sign register are arranged on the motherboard.
Memory Controller Hub proposed by the invention and multi-memory system can strengthen the driving force of Memory Controller Hub, reduce system cost.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the synoptic diagram of an embodiment of multi-memory system of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
As one embodiment of the present of invention, memory bar can be the DIMM memory bar, CS (chipselect wherein, chip selection signal) 0, CS1, BA0～BA2 (bank address, address area address signal in the internal memory particle), A0～A13/A14 (address, address wire), RAS (Row Address Strobe, row address is selected signal), CAS (Column Address Strobe, column address is selected signal), WE (Write Enable, written allowance signal), CK (Clock, clock signal), CKE (ClockEnable, clock allows signal) 0, CKE1, ODT (On Die Terminator, on-die termination device modelled signal) 0, the signal demand of ODT1 is connected to the whole Rank (memory block) of internal memory.And every DQ (data I/O), DQS (Data Strobe, data strobe), DM (DQ Mask, data mask control signal) only are connected to 2 Monolithic (internal memory particle).
Be illustrated in figure 1 as the synoptic diagram of an embodiment of multi-memory system of the present invention, wherein, this system comprises Memory Controller Hub 11 and internal memory 12.
Memory Controller Hub 11 comprises DDR (Double Data Rate, double data rate) controller 111 and at least one sign register.DDR controller 111 is used for producing the internal memory drive signal according to the instruction of central processing unit, this internal memory drive signal comprises first signal line group and secondary signal line group, wherein each group secondary signal line group is suitable for being connected with two internal memory particles in the corresponding internal memory, as shown in phantom in FIG..Sign register 112,113 is used for first signal line group of described DDR controller output is carried out power amplification and shaping, wherein each group is connected with each internal memory particle in the corresponding internal memory 12 through first signal line group of power amplification and shaping, shown in solid line among the figure.
As one embodiment of the present of invention, first signal line group comprises CS0, CS1, BA0～BA2, A0～A13/A14, RAS, CAS, WE, CK, CKE0, CKE1, ODT0, ODT1 signal wire.
As one embodiment of the present of invention, secondary signal line group comprises data input/output line, data mask control line and data strobe signal line.
As one embodiment of the present of invention, the DDR controller can be DDR2 (Double Data Rate2, double data rate 2) controller.
As one embodiment of the present of invention, the output terminal of DDR controller comprises a plurality of first signal line group, each first signal line group connects two sign register (Register, be labeled as R among the figure), for example, as shown in Figure 1, the output signal of DDR controller can comprise one group of first signal line group, thereby Memory Controller Hub 11 can comprise two sign registers 112,113.Certainly, it only is an example of the present invention that a DDR controller connects two sign registers, also can adopt other sign register number.
As one embodiment of the present of invention, internal memory 12 can comprise DIMM (Dual InlineMemory Module, dual inline memory module).Employing standard DIMM memory bar makes this multi-memory system and Memory Controller Hub have good compatibility, can be used in plurality of devices, and can significantly reduce system cost.
As one embodiment of the present of invention, the output terminal of each sign register 112,113 comprises two signal line group, and each signal line group connects a DIMM.Certainly, this only is an example of the present invention, in specific implementation process, and the number of the memory bar that can connect according to each sign register of parameter changes such as design output of sign register.
As one embodiment of the present of invention, DDR controller 111 and sign register 112,113 can be arranged at PCB (Printed Circuit Board, printed circuit board (PCB)) on the motherboard, output signal to DDR controller and sign register is divided into groups, can be by realizing at the enterprising row wiring of pcb board.
The embodiment of Memory Controller Hub of the present invention and multi-memory system adopts the scheme that sign register spare is placed on motherboard (MotherBoard), the feasible DIMM that still adopts standard, but controller can drive the standard DIMM internal memory more than 2, strengthened the driving force of Memory Controller Hub, and, can significantly reduce system cost owing to adopted standard DIMM.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (12)
1. a Memory Controller Hub is characterized in that, comprises double data rate DDR controller and at least one sign register, wherein,
Described DDR controller is used for producing the internal memory drive signal according to the instruction of central processing unit, described internal memory drive signal comprises first signal line group and second group of signal line group, and wherein each is organized described secondary signal line group and is suitable for being connected with two internal memory particles in the corresponding internal memory;
Described sign register is used for described first signal line group of described DDR controller output is carried out power amplification and shaping, and wherein described first signal line group through power amplification and shaping of each group is suitable for being connected with each internal memory particle in the corresponding internal memory.
2. Memory Controller Hub according to claim 1, it is characterized in that described first signal line group comprises that address area selection wire in chip selection signal line, the internal memory particle, address wire, row address selection signal, column address selection signal, written allowance signal, clock signal, clock allow signal, on-die termination device modelled signal.
3. Memory Controller Hub according to claim 1 is characterized in that, described secondary signal line group comprises data input/output line, data mask control line and data strobe signal line.
4. Memory Controller Hub according to claim 1 is characterized in that, the output terminal of described DDR controller comprises at least one group first signal line group, and the input end of each described sign register is connected with one group of described first signal line group.
5. Memory Controller Hub according to claim 1 is characterized in that described internal memory comprises dual inline memory module DIMM.
6. according to each described Memory Controller Hub of claim 1-5, it is characterized in that described DDR controller and sign register are arranged on the motherboard.
7. a multi-memory system is characterized in that, comprises Memory Controller Hub and internal memory, and described Memory Controller Hub comprises double data rate DDR controller and at least one sign register, wherein,
Described DDR controller is used for producing the internal memory drive signal according to the instruction of central processing unit, first signal line group that described internal memory drive signal comprises and second group of signal line group, wherein each is organized described secondary signal line group and is suitable for being connected with two internal memory particles in the corresponding internal memory;
Described sign register is used for described first signal line group of described DDR controller output is carried out power amplification and shaping, and wherein described first signal line group through power amplification and shaping of each group is suitable for being connected with each internal memory particle in the corresponding internal memory.
8. multi-memory system according to claim 7, it is characterized in that described first signal line group comprises that address area selection wire in chip selection signal line, the internal memory particle, address wire, row address selection signal, column address selection signal, written allowance signal, clock signal, clock allow signal, on-die termination device modelled signal.
9. multi-memory system according to claim 7 is characterized in that, described secondary signal line group comprises data input/output line, data mask control line and data strobe signal line.
10. multi-memory system according to claim 7 is characterized in that, the output terminal of described DDR controller comprises at least one group first signal line group, and the input end of each described sign register is connected with one group of described first signal line group.
11. multi-memory system according to claim 7 is characterized in that, described internal memory comprises dual inline memory module DIMM.
12., it is characterized in that described DDR controller and sign register are arranged on the motherboard according to each described multi-memory system of claim 7-11.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043740A (en) * | 2010-12-17 | 2011-05-04 | 天津曙光计算机产业有限公司 | Realization method for controller to be compatible to multicapacity memory by FPGA (field programmable gate array) |
| CN104281544A (en) * | 2013-07-05 | 2015-01-14 | 晨星半导体股份有限公司 | Memorizer controller and signal generating method of memorizer controller |
| WO2016082182A1 (en) * | 2014-11-28 | 2016-06-02 | 华为技术有限公司 | Method for configuring memory system having optical interface and memory system |
| CN105845167A (en) * | 2015-01-30 | 2016-08-10 | 爱思开海力士有限公司 | Data transmission circuit |
| CN111949213A (en) * | 2020-07-28 | 2020-11-17 | 新华三半导体技术有限公司 | Memory particle access control chip, memory particle access control system and method |
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| US7042770B2 (en) * | 2001-07-23 | 2006-05-09 | Samsung Electronics Co., Ltd. | Memory devices with page buffer having dual registers and method of using the same |
| JP4492938B2 (en) * | 2004-05-26 | 2010-06-30 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device and operation method thereof |
| CN100508064C (en) * | 2005-01-31 | 2009-07-01 | 上海奇码数字信息有限公司 | Storage access controller and storage access method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043740A (en) * | 2010-12-17 | 2011-05-04 | 天津曙光计算机产业有限公司 | Realization method for controller to be compatible to multicapacity memory by FPGA (field programmable gate array) |
| CN102043740B (en) * | 2010-12-17 | 2016-04-20 | 曙光信息产业股份有限公司 | A kind of FPGA realizes the controller implementation method of compatible multicapacity internal memory |
| CN104281544A (en) * | 2013-07-05 | 2015-01-14 | 晨星半导体股份有限公司 | Memorizer controller and signal generating method of memorizer controller |
| WO2016082182A1 (en) * | 2014-11-28 | 2016-06-02 | 华为技术有限公司 | Method for configuring memory system having optical interface and memory system |
| CN107003808A (en) * | 2014-11-28 | 2017-08-01 | 华为技术有限公司 | The collocation method and memory system of memory system with optical interface |
| CN107003808B (en) * | 2014-11-28 | 2019-11-22 | 华为技术有限公司 | The configuration method and memory system of memory system with optical interface |
| CN105845167A (en) * | 2015-01-30 | 2016-08-10 | 爱思开海力士有限公司 | Data transmission circuit |
| CN105845167B (en) * | 2015-01-30 | 2020-12-08 | 爱思开海力士有限公司 | Data transmission circuit |
| CN111949213A (en) * | 2020-07-28 | 2020-11-17 | 新华三半导体技术有限公司 | Memory particle access control chip, memory particle access control system and method |
| CN111949213B (en) * | 2020-07-28 | 2022-08-30 | 新华三半导体技术有限公司 | Memory particle access control chip, memory particle access control system and method |
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| CN101699560B (en) | 2012-12-12 |
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Address after: 100193 Beijing, Haidian District, northeast Wang West Road, building 8, No. 36 Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Address before: 100084 No. 6 South Road, Zhongguancun Academy of Sciences, Beijing, Haidian District Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |
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Effective date of registration: 20220729 Address after: 100089 building 36, courtyard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Patentee after: DAWNING INFORMATION INDUSTRY Co.,Ltd. Address before: 100193 No. 36 Building, No. 8 Hospital, Wangxi Road, Haidian District, Beijing Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |