CN104281535A - Method and device for processing mapping tables in memory - Google Patents
Method and device for processing mapping tables in memory Download PDFInfo
- Publication number
- CN104281535A CN104281535A CN201410494461.9A CN201410494461A CN104281535A CN 104281535 A CN104281535 A CN 104281535A CN 201410494461 A CN201410494461 A CN 201410494461A CN 104281535 A CN104281535 A CN 104281535A
- Authority
- CN
- China
- Prior art keywords
- sub
- storage space
- lot
- mapping table
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a method and a device for processing mapping tables in the memory. The method includes steps of judging whether target mapping sub-tables exist in memory sub-spaces Slot or not; if no target mapping sub-stables exist in the memory sub-spaces Slot, judging whether the memory sub-spaces Slot with empty state identifiers exist or not, and if yes, adding the target mapping sub-tables to the memory sub-spaces Slot with the empty state identifiers; updating the state identifiers of the memory sub-spaces Slot into non-empty state identifiers. By the method and the device for processing the mapping tables in the memory, conversion times of the mapping tables in the memory and read-write operation of data are reduced, and read-write delay is shortened.
Description
Technical field
The present invention relates to technical field of data processing, particularly relate to the disposal route of a kind of mapping table in internal memory and the treating apparatus of a kind of mapping table in internal memory.
Background technology
At eMMC (Embedded Multi Media Card, embedded multi-media card), FTL (Flash Translation Layer in the product such as flash memory NAND, flash translation layer (FTL)), the medium being a kind of and talk with between operating system, owing to there is FTL, therefore operating system can using products such as flash memories as a disc driver, the products such as flash memory is set up multiple virtual data block or sector in order to store and management data.
For FTL, Problems existing is at present, when needing RAM (the Random Access Memory mapping table in FTL being read operating system, random access memory/internal memory) in time, there is the problem that mapping table is too large and can not all be loaded in internal memory sometimes.Therefore can only load when internal memory runs a part for mapping table is loaded in internal memory, change when needing other parts of mapping table, the way of this conversion is called " dynamic load mapping table " again.
With reference to a kind of schematic diagram realizing the common method of dynamic load mapping table shown in Fig. 1, its concrete steps of carrying out dynamic load mapping table are: mapping table is divided into multiple equal part Mapping table Part_1, Mapping table Part_2 ... Mapping table Part_m ... Mapping table Part_n, only operationally a part for mapping table is loaded in internal memory, such as only load Mapping table Part_m in internal memory, when needing other parts of mapping table in the read-write process in data, such as need Mapping table Part_n, need first Mapping table Part_m to be saved in flash memory NAND, again Mapping table Part_n is loaded in internal memory.The shortcoming of this common method is, the conversion at every turn carrying out mapping table needs the process of carrying out extra reading and writing data, causes larger read-write to postpone.
Therefore, the technical matters needing those skilled in the art urgently to solve at present is exactly: propose the disposal route of a kind of mapping table in internal memory and device, in order to reduce the conversion times of mapping table in internal memory, reduce the read-write operation of data, shorten read-write and postpone.
Summary of the invention
Embodiment of the present invention technical matters to be solved is to provide the disposal route of a kind of mapping table in internal memory, in order to reduce the conversion times of mapping table in internal memory, reduces the read-write operation of data, shortens read-write and postpones.
Accordingly, the embodiment of the present invention additionally provides the treating apparatus of a kind of mapping table in internal memory, in order to ensure the implementation and application of said method.
In order to solve the problem, the invention discloses the disposal route of a kind of mapping table in internal memory, described mapping table comprises two or more sub-mapping table; The storage space of described internal memory comprises two or more sub-storage space S lot, and described sub-storage space S lot has corresponding status indicator, and described status indicator comprises dummy status mark and non-null states mark; Described method comprises:
Judge whether the sub-mapping table of target is present in described sub-storage space S lot;
If the sub-mapping table of described target is not present in described sub-storage space S lot, then judge whether the sub-storage space S lot existing for dummy status mark;
If exist for the sub-storage space S lot of dummy status mark, then sub-for described target mapping table is added in the described sub-storage space S lot for dummy status mark;
The status indicator of described sub-storage space S lot is updated to non-null states mark.
Preferably, the access queue of described sub-storage space S lot is stored in described internal memory; Described internal memory communicates mutually with flash memory NAND; Described judge whether to exist for the step of the sub-storage space S lot of dummy status mark after, also comprise:
If do not exist for the sub-storage space S lot of dummy status mark, then according to described access queue, the sub-mapping table in the sub-storage space S lot identified for non-null states is saved in flash memory NAND;
The status indicator of described sub-storage space S lot is updated to dummy status mark.
Preferably, the step that the sub-mapping table in the sub-storage space S lot identified for non-null states is saved in flash memory NAND comprises by described foundation access queue:
Obtain the sub-storage space S lot for non-null states mark being in the tail of the queue of described access queue;
Sub-mapping table in described sub-storage space S lot is saved to flash memory NAND.
Preferably, described method also comprises:
When described internal memory is in idle condition, judge whether the sub-storage space S lot existing for dummy status mark.
Preferably, described new mapping table added the step of the sub-storage space S lot of most dummy status mark after, also comprise:
Upgrade described sub-storage space S lot access queue.
The embodiment of the invention also discloses the treating apparatus of a kind of mapping table in internal memory, described mapping table comprises two or more sub-mapping table; The storage space of described internal memory comprises two or more sub-storage space S lot, and described sub-storage space S lot has corresponding status indicator, and described status indicator comprises dummy status mark and non-null states mark; Described device comprises:
First judge module, for judging whether the sub-mapping table of target is present in described sub-storage space S lot; If the sub-mapping table of described target is not present in described sub-storage space S lot, then call the second module;
Second judge module, for judging whether the sub-storage space S lot existing for dummy status mark; If exist for the sub-storage space S lot of dummy status mark, then call interpolation module;
Add module, for being added into by sub-for described target mapping table in the described sub-storage space S lot for dummy status mark;
First update module, for being updated to non-null states mark by the status indicator of described sub-storage space S lot.
Preferably, the access queue of described sub-storage space S lot is stored in described internal memory; Described internal memory communicates mutually with flash memory NAND; Described device also comprises:
Preserving module, if the sub-storage space S lot for not existing for dummy status mark, then according to described access queue, the sub-mapping table in the sub-storage space S lot identified for non-null states being saved in flash memory NAND;
Second update module, for being updated to dummy status mark by the status indicator of described sub-storage space S lot.
Preferably, described preservation module comprises:
Sub-storage space S lot obtains submodule, for obtaining the sub-storage space S lot for non-null states mark of the tail of the queue being in described access queue;
Sub-mapping table preserves submodule, for being saved in flash memory NAND by the sub-mapping table in described sub-storage space S lot.
Preferably, described device also comprises:
Idle determination module, for when described internal memory is in idle condition, judges whether the sub-storage space S lot existing for dummy status mark.
Preferably, described device also comprises:
Access queue update module, for upgrading described sub-storage space S lot access queue.
Compared with prior art, the embodiment of the present invention comprises following advantage:
The embodiment of the present invention is assigned a part of storage space in internal memory, and this storage space is divided into again multiple sub-storage space S lot, for depositing the data of specific format.In the process of carrying out reading and writing data, if find that the sub-mapping table of target is not present in sub-storage space S lot, then need sub-for this target mapping table to be added in the sub-storage space S lot of non-null states mark.Owing to being assigned multiple sub-storage space S lot in internal memory, therefore only need to add sub-for target mapping table to do not have sub-mapping table sub-storage space S lot, unnecessary read-write operation can be reduced, reduce the conversion times of mapping table, improve internal memory handling property.
In addition, the embodiment of the present invention also monitors the state of all sub-storage space S lot when idle condition, and the state access queue of whole sub-storage space S lot records the access situation of sub-storage space S lot.If find that whole sub-storage space S lot has sub-mapping table, then the sub-storage space S lot of access queue afterbody can be in, namely the long-time sub-mapping table do not carried out in the sub-storage space S lot of accessing operation is saved in flash memory NAND, thus the sub-mapping table of target vacating sub-storage space S lot to add, shorten read-write and postpone.
Accompanying drawing explanation
Fig. 1 is a kind of schematic diagram realizing the common method of dynamic load mapping table of the present invention;
Fig. 2 is the flow chart of steps of the disposal route embodiment 1 of a kind of mapping table of the present invention in internal memory;
Fig. 3 of the present inventionly a kind ofly adds sub-for target mapping table to schematic diagram before internal memory;
Fig. 4 of the present inventionly a kind ofly adds sub-for target mapping table to schematic diagram after internal memory;
Fig. 5 is the flow chart of steps of the disposal route embodiment 2 of a kind of mapping table of the present invention in internal memory;
Sub-mapping table is of the present inventionly a kind ofly stored into the schematic diagram before flash memory NAND by Fig. 6;
Sub-mapping table is of the present inventionly a kind ofly stored into the schematic diagram after flash memory NAND by Fig. 7;
Fig. 8 is the structured flowchart of the treating apparatus embodiment of a kind of mapping table of the present invention in internal memory.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Embodiment one:
With reference to Fig. 2, show the flow chart of steps of the disposal route embodiment 1 of a kind of mapping table of the present invention in internal memory, described mapping table can comprise two or more sub-mapping table; The storage space of described internal memory can comprise two or more sub-storage space S lot, and described sub-storage space S lot can have corresponding status indicator, and described status indicator can comprise dummy status mark and non-null states mark;
In specific implementation, mapping table is divided into multiple equal sub-mapping table, such as Mapping table part_1, Mapping table part_2, Mapping table part_3 ...In internal memory, distribute the storage space of a part, and be divided into the sub-storage space of a lot of block, the sub-storage space of each block can be used for depositing the data of specific format, such as mapping table.This seed storage space can be called visually a groove (Slot), just as each groove in audio amplifier can deposit a CD, in embodiments of the present invention, each groove can deposit mapping table data.
Described sub-storage space S lot is provided with corresponding status indicator, in order to show its store status.Specifically can comprise dummy status mark and non-null states mark.Wherein, dummy status mark in order to represent its correspondence storage space S lot in currently do not deposited sub-mapping table, non-null states mark has then deposited sub-mapping table in order to current in the storage space S lot of its correspondence.
Described method specifically can comprise the steps:
Step 201, judges whether the sub-mapping table of target is present in described sub-storage space S lot; If the sub-mapping table of described target is not present in described sub-storage space S lot, then perform step 202;
Step 202, judges whether the sub-storage space S lot existing for dummy status mark; If exist for the sub-storage space S lot of dummy status mark, then perform step 203;
Step 203, is added in the described sub-storage space S lot for dummy status mark by sub-for described target mapping table;
In embodiments of the present invention, in the process of user writable data, if the current required sub-mapping table of target is not present in internal memory, when not namely being present in certain sub-storage space S lot, then need sub-for target mapping table to add to a certain sub-storage space S lot for dummy status mark in internal memory, namely currently not deposit in the sub-storage space S lot of sub-mapping table.If now judge the sub-storage space S lot existing for dummy status mark, then sub-for target mapping table can be joined in the sub-storage space S lot into dummy status mark, to ensure the normal operation of user writable data.
Step 204, is updated to non-null states mark by the status indicator of described sub-storage space S lot.
When sub-for target mapping table is joined after in sub-storage space S lot, owing to having housed sub-mapping table in this sub-storage space S lot, now also the status indicator of this sub-storage space S lot should be revised as non-null states mark from dummy status mark, illustrate that this sub-storage space S lot has housed sub-mapping table thus.
The embodiment of the present invention is understood better in order to make those skilled in the art, to can refer to shown in Fig. 3 of the present invention a kind of adds sub-for target mapping table to schematic diagram before internal memory, NAND (flash memory) communicates mutually with RAM (internal memory) in the drawings, the sub-mapping table Mapping table Part_1 of mapping table is included in NAND, Mapping table Part_2, Mapping table Part_3, Mapping table Part_4, Mapping table Part_5, divide in RAM and have multiple sub-storage space S lot 0, Slot 1, Slot 2, Slot 3, wherein, Mapping table Part_1 is stored in Slot 0, therefore sub-storage space S lot 0, Slot 1, Slot 2, the state that Slot 3 is corresponding is respectively Non-empty (non-null states), empty (dummy status), empty (dummy status), empty (dummy status).
Sub-for target mapping table is added to schematic diagram after internal memory with reference to of the present invention a kind of shown in Fig. 4, in the process of user writable data, if current required target sub-mapping table Mapping table Part_3 is not present in internal memory, then need Mapping table Part_3 to join in internal memory in the sub-storage space of empty, when Mapping table Part_3 is joined in internal memory for empty Slot 1 after, then need to be Non-empty (non-null states) by the status modifier of Slot 1.
The embodiment of the present invention is assigned a part of storage space in internal memory, and this storage space is divided into again multiple sub-storage space S lot, for depositing the data (such as mapping table) of specific format.In the process of carrying out reading and writing data, if find that the sub-mapping table of target is not present in sub-storage space S lot, then need sub-for this target mapping table to be added in the sub-storage space S lot of non-null states mark.Owing to being assigned multiple sub-storage space S lot in internal memory, therefore only need to add sub-for target mapping table to do not have sub-mapping table sub-storage space S lot, unnecessary read-write operation can be reduced, reduce the conversion times of mapping table, improve internal memory handling property.
Embodiment two:
With reference to Fig. 5, show the flow chart of steps of the disposal route embodiment 2 of a kind of mapping table of the present invention in internal memory, described mapping table can comprise two or more sub-mapping table; The storage space of described internal memory can comprise two or more sub-storage space S lot, and described sub-storage space S lot can have corresponding status indicator, and described status indicator can comprise dummy status mark and non-null states mark; The access queue of described sub-storage space S lot can be stored in described internal memory; Described internal memory can communicate mutually with flash memory NAND; Specifically can comprise the steps:
Step 401, judges whether the sub-mapping table of target is present in described sub-storage space S lot; If the sub-mapping table of described target is not present in described sub-storage space S lot, then perform step 402; If the sub-mapping table of described target is present in described sub-storage space S lot, then perform step 407;
In one preferred embodiment of the invention, described method can also comprise the steps:
Step S11, when described internal memory is in idle condition, judges whether the sub-storage space S lot existing for dummy status mark.
In embodiments of the present invention, the access queue of described sub-storage space S lot is stored in internal memory.Example of the present invention can monitor the state of all sub-storage space S lot when idle condition, the state access queue of whole sub-storage space S lot records the access situation of sub-storage space S lot.If find that whole sub-storage space S lot has sub-mapping table, then the sub-storage space S lot of access queue afterbody can be in, namely the long-time sub-mapping table do not carried out in the sub-storage space S lot of accessing operation is saved in flash memory NAND, thus the sub-mapping table of target vacating sub-storage space S lot to add, avoid the sub-storage space S lot sometimes needing not exist for dummy status when adding the sub-mapping table of target, also need to empty the time needed for a certain sub-storage space S lot further, shorten read-write and postpone.
With reference to of the present invention a kind of shown in Fig. 6, sub-mapping table is stored into the schematic diagram before flash memory NAND, when in the idle state, detects the state of internal memory neutron storage space S lot.Suppose the sub-storage space S lot 0 in RAM, Slot 1, Mapping table Part_1 is stored respectively, Mapping table Part_3 in Slot 2, Slot 3, Mapping table Part_4, Mapping table Part_5, then sub-storage space S lot 0, Slot 1, the state that Slot 2, Slot 3 is corresponding is respectively Non-empty (non-null states).
With reference to of the present invention a kind of shown in Fig. 7, sub-mapping table is stored into the schematic diagram after flash memory NAND, when in the idle state, the state of all sub-storage space S lot detected, find sub-storage space S lot 0, Slot 1, Slot 2, the state that Slot 3 is corresponding is respectively Non-empty, in order to avoid when needs mapping table that target is sub-, not for empty sub-storage space S lot deposits, now can will be in access queue tail of the queue, the sub-mapping table namely not carrying out the sub-storage space S lot of storage operation is for a long time saved in NAND.In this example, because Slot 0 is in access queue tail of the queue, therefore it can be removed from access queue, and the Mapping table Part_1 in Slot 0 is saved in NAND.
Certainly, in actual applications, can also set and not have accessed sub-storage space S lot to remove from access queue by exceeding Preset Time, the embodiment of the present invention is not limited this.
It should be noted that, in the process of user writable data, also with when needing to add sub-for target mapping table to sub-storage space S lot in internal memory, just determine whether the sub-storage space S lot that dummy status identifies, the embodiment of the present invention is not limited this equally.
Step 402, judges whether the sub-storage space S lot existing for dummy status mark; If exist for the sub-storage space S lot of dummy status mark, then perform step 405; If do not exist for the sub-storage space S lot of dummy status mark, then perform step 403;
Step 403, is saved in flash memory NAND according to described access queue by the sub-mapping table in the sub-storage space S lot identified for non-null states;
Needs illustrate, also mapping table can be kept in other storeies except flash memory NAND, the embodiment of the present invention is not limited this.
In one preferred embodiment of the invention, described step 403 can comprise following sub-step:
Sub-step S21, obtains the sub-storage space S lot for non-null states mark being in the tail of the queue of described access queue;
Sub-step S22, is saved to flash memory NAND by the sub-mapping table in described sub-storage space S lot.
Step 404, is updated to dummy status mark by the status indicator of described sub-storage space S lot;
Step 405, is added in the described sub-storage space S lot for dummy status mark by sub-for described target mapping table;
Step 406, is updated to non-null states mark by the status indicator of described sub-storage space S lot;
Step 407, upgrades described sub-storage space S lot access queue.
In specific implementation, sub-for target mapping table is joined in sub-storage space S lot, or current accessed is after having stored the sub-storage space S lot of the sub-mapping table of target, because the sub-storage space S lot of access there occurs change, therefore need to upgrade the sub-storage space S lot access queue in internal memory, in access queue, be revised as first by what now store the sub-storage space S lot of the sub-mapping table of target.
For Fig. 4, in RAM, store the access queue recording sub-storage space S lot access order.Because the sub-storage space S lot now accessed has changed to Slot 1, therefore also need in access queue, to be revised as first by the Slot 1 of store M apping table Part_3 in internal memory.
It should be noted that, for embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the embodiment of the present invention is not by the restriction of described sequence of movement, because according to the embodiment of the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and involved action might not be that the embodiment of the present invention is necessary.
Embodiment three:
With reference to Fig. 8, show the structured flowchart of the treating apparatus embodiment of a kind of mapping table of the present invention in internal memory, described mapping table can comprise two or more sub-mapping table; The storage space of described internal memory can comprise two or more sub-storage space S lot, and described sub-storage space S lot can have corresponding status indicator, and described status indicator can comprise dummy status mark and non-null states mark; Specifically can comprise as lower module:
First judge module 601, for judging whether the sub-mapping table of target is present in described sub-storage space S lot; If the sub-mapping table of described target is not present in described sub-storage space S lot, then call the second module;
Second judge module 602, for judging whether the sub-storage space S lot existing for dummy status mark; If exist for the sub-storage space S lot of dummy status mark, then call interpolation module;
In one preferred embodiment of the invention, the access queue of described sub-storage space S lot can be stored in described internal memory; Described internal memory can communicate mutually with flash memory NAND; Described device can also comprise as lower module:
Preserving module, if the sub-storage space S lot for not existing for dummy status mark, then according to described access queue, the sub-mapping table in the sub-storage space S lot identified for non-null states being saved in flash memory NAND;
Second update module, for being updated to dummy status mark by the status indicator of described sub-storage space S lot.
Add module 603, for being added into by sub-for described target mapping table in the described sub-storage space S lot for dummy status mark;
First update module 604, for being updated to non-null states mark by the status indicator of described sub-storage space S lot.
In one preferred embodiment of the invention, described preservation module can comprise following submodule:
Sub-storage space S lot obtains submodule, for obtaining the sub-storage space S lot for non-null states mark of the tail of the queue being in described access queue;
Sub-mapping table preserves submodule, for being saved in flash memory NAND by the sub-mapping table in described sub-storage space S lot.
In one preferred embodiment of the invention, described device also comprises as lower module:
Idle determination module, for when described internal memory is in idle condition, judges whether the sub-storage space S lot existing for dummy status mark.
In one preferred embodiment of the invention, described device also comprises as lower module:
Access queue update module, for upgrading described sub-storage space S lot access queue.
For device embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, terminal device (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing terminal equipment produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computing machine or other programmable terminal equipment, thus the instruction performed on computing machine or other programmable terminal equipment is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal device and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal device.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal device comprising described key element and also there is other identical element.
Above to the disposal route of a kind of mapping table provided by the present invention in internal memory and the treating apparatus of a kind of mapping table in internal memory, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. the disposal route of mapping table in internal memory, is characterized in that, described mapping table comprises two or more sub-mapping table; The storage space of described internal memory comprises two or more sub-storage space S lot, and described sub-storage space S lot has corresponding status indicator, and described status indicator comprises dummy status mark and non-null states mark; Described method comprises:
Judge whether the sub-mapping table of target is present in described sub-storage space S lot;
If the sub-mapping table of described target is not present in described sub-storage space S lot, then judge whether the sub-storage space S lot existing for dummy status mark;
If exist for the sub-storage space S lot of dummy status mark, then sub-for described target mapping table is added in the described sub-storage space S lot for dummy status mark;
The status indicator of described sub-storage space S lot is updated to non-null states mark.
2. method according to claim 1, is characterized in that, stores the access queue of described sub-storage space S lot in described internal memory; Described internal memory communicates mutually with flash memory NAND; Described judge whether to exist for the step of the sub-storage space S lot of dummy status mark after, also comprise:
If do not exist for the sub-storage space S lot of dummy status mark, then according to described access queue, the sub-mapping table in the sub-storage space S lot identified for non-null states is saved in flash memory NAND;
The status indicator of described sub-storage space S lot is updated to dummy status mark.
3. method according to claim 2, is characterized in that, the step that the sub-mapping table in the sub-storage space S lot identified for non-null states is saved in flash memory NAND comprises by described foundation access queue:
Obtain the sub-storage space S lot for non-null states mark being in the tail of the queue of described access queue;
Sub-mapping table in described sub-storage space S lot is saved to flash memory NAND.
4. method according to claim 1, is characterized in that, also comprises:
When described internal memory is in idle condition, judge whether the sub-storage space S lot existing for dummy status mark.
5. method according to claim 1 and 2, is characterized in that, described new mapping table added the step of the sub-storage space S lot of most dummy status mark after, also comprise:
Upgrade described sub-storage space S lot access queue.
6. the treating apparatus of mapping table in internal memory, is characterized in that, described mapping table comprises two or more sub-mapping table; The storage space of described internal memory comprises two or more sub-storage space S lot, and described sub-storage space S lot has corresponding status indicator, and described status indicator comprises dummy status mark and non-null states mark; Described device comprises:
First judge module, for judging whether the sub-mapping table of target is present in described sub-storage space S lot; If the sub-mapping table of described target is not present in described sub-storage space S lot, then call the second module;
Second judge module, for judging whether the sub-storage space S lot existing for dummy status mark; If exist for the sub-storage space S lot of dummy status mark, then call interpolation module;
Add module, for being added into by sub-for described target mapping table in the described sub-storage space S lot for dummy status mark;
First update module, for being updated to non-null states mark by the status indicator of described sub-storage space S lot.
7. device according to claim 6, is characterized in that, stores the access queue of described sub-storage space S lot in described internal memory; Described internal memory communicates mutually with flash memory NAND; Described device also comprises:
Preserving module, if the sub-storage space S lot for not existing for dummy status mark, then according to described access queue, the sub-mapping table in the sub-storage space S lot identified for non-null states being saved in flash memory NAND;
Second update module, for being updated to dummy status mark by the status indicator of described sub-storage space S lot.
8. device according to claim 7, is characterized in that, described preservation module comprises:
Sub-storage space S lot obtains submodule, for obtaining the sub-storage space S lot for non-null states mark of the tail of the queue being in described access queue;
Sub-mapping table preserves submodule, for being saved in flash memory NAND by the sub-mapping table in described sub-storage space S lot.
9. device according to claim 6, is characterized in that, also comprises:
Idle determination module, for when described internal memory is in idle condition, judges whether the sub-storage space S lot existing for dummy status mark.
10. the device according to claim 6 or 7, is characterized in that, also comprises:
Access queue update module, for upgrading described sub-storage space S lot access queue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410494461.9A CN104281535B (en) | 2014-09-24 | 2014-09-24 | A kind for the treatment of method and apparatus of mapping table in internal memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410494461.9A CN104281535B (en) | 2014-09-24 | 2014-09-24 | A kind for the treatment of method and apparatus of mapping table in internal memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104281535A true CN104281535A (en) | 2015-01-14 |
| CN104281535B CN104281535B (en) | 2017-11-17 |
Family
ID=52256429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410494461.9A Active CN104281535B (en) | 2014-09-24 | 2014-09-24 | A kind for the treatment of method and apparatus of mapping table in internal memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104281535B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107168888A (en) * | 2017-05-19 | 2017-09-15 | 惠州佰维存储科技有限公司 | The mapping table management method and its system of Nand flash memories |
| CN108073524A (en) * | 2016-11-15 | 2018-05-25 | 慧荣科技股份有限公司 | Memory management method applicable to data storage device |
| CN109375877A (en) * | 2018-10-24 | 2019-02-22 | 江苏华存电子科技有限公司 | A kind of method of managing main frame end logical place correspondence mappings table in flash memory storage |
| CN111459844A (en) * | 2019-01-21 | 2020-07-28 | 慧荣科技股份有限公司 | Data storage device and method for accessing logical-to-physical address mapping table |
| WO2020177549A1 (en) * | 2019-03-06 | 2020-09-10 | 阿里巴巴集团控股有限公司 | Data reading and writing method and device |
| CN112099943A (en) * | 2020-08-13 | 2020-12-18 | 深圳云天励飞技术股份有限公司 | Memory allocation method and related equipment |
| CN112882663A (en) * | 2021-03-25 | 2021-06-01 | 湖南国科微电子股份有限公司 | Random writing method, electronic equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436419A (en) * | 2010-09-29 | 2012-05-02 | 三星电子株式会社 | Non-volatile memory systems and methods of managing power of the same |
| CN103064641A (en) * | 2013-02-05 | 2013-04-24 | 威盛电子股份有限公司 | Non-volatile storage device and operating method thereof |
-
2014
- 2014-09-24 CN CN201410494461.9A patent/CN104281535B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436419A (en) * | 2010-09-29 | 2012-05-02 | 三星电子株式会社 | Non-volatile memory systems and methods of managing power of the same |
| CN103064641A (en) * | 2013-02-05 | 2013-04-24 | 威盛电子股份有限公司 | Non-volatile storage device and operating method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108073524A (en) * | 2016-11-15 | 2018-05-25 | 慧荣科技股份有限公司 | Memory management method applicable to data storage device |
| CN107168888A (en) * | 2017-05-19 | 2017-09-15 | 惠州佰维存储科技有限公司 | The mapping table management method and its system of Nand flash memories |
| CN107168888B (en) * | 2017-05-19 | 2020-06-02 | 惠州佰维存储科技有限公司 | Mapping table management method and system of Nand flash memory |
| CN109375877A (en) * | 2018-10-24 | 2019-02-22 | 江苏华存电子科技有限公司 | A kind of method of managing main frame end logical place correspondence mappings table in flash memory storage |
| CN111459844A (en) * | 2019-01-21 | 2020-07-28 | 慧荣科技股份有限公司 | Data storage device and method for accessing logical-to-physical address mapping table |
| WO2020177549A1 (en) * | 2019-03-06 | 2020-09-10 | 阿里巴巴集团控股有限公司 | Data reading and writing method and device |
| CN112099943A (en) * | 2020-08-13 | 2020-12-18 | 深圳云天励飞技术股份有限公司 | Memory allocation method and related equipment |
| CN112882663A (en) * | 2021-03-25 | 2021-06-01 | 湖南国科微电子股份有限公司 | Random writing method, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104281535B (en) | 2017-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104281535A (en) | Method and device for processing mapping tables in memory | |
| CN102541927B (en) | Method and device for realizing data cache | |
| CN101315628B (en) | Internal memory database system and method and device for implementing internal memory data base | |
| CN104238963B (en) | A kind of date storage method, storage device and storage system | |
| CN103154950B (en) | Repeated data deleting method and device | |
| CN105786401A (en) | Data management method and device in server cluster system | |
| CN107766374B (en) | Optimization method and system for storage and reading of massive small files | |
| US20130254240A1 (en) | Method of processing database, database processing apparatus, computer program product | |
| CN107562367B (en) | Method and device for reading and writing data based on software storage system | |
| US20200042538A1 (en) | Methods and apparatus to partition a database | |
| CN103049224A (en) | Method, device and system for importing data into physical tape | |
| CN110109868A (en) | Method, apparatus and computer program product for index file | |
| CN103914483A (en) | File storage method and device and file reading method and device | |
| CN104462127A (en) | Recorded data updating method and device | |
| CN110019111A (en) | Data processing method, device, storage medium and processor | |
| CN105468644A (en) | Method and device for performing query in database | |
| CN102890651B (en) | The method of testing of a kind of contextual data and device | |
| US10929347B2 (en) | Defragmenting files having file blocks in multiple point-in-time copies | |
| CN104461384A (en) | Data write-in method and storage device | |
| US20210349918A1 (en) | Methods and apparatus to partition a database | |
| CN104808953A (en) | Device and method for controlling data storage and mobile terminal | |
| CN104252415B (en) | Method and system for redistributing data | |
| CN110110034A (en) | A kind of RDF data management method, device and storage medium based on figure | |
| CN104537023A (en) | Storage method and device for reverse index records | |
| CN114661243A (en) | Method, device, equipment and medium suitable for adjusting visible capacity of SSD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |