CN104280651B - Test system and semiconductor element - Google Patents
Test system and semiconductor element Download PDFInfo
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- CN104280651B CN104280651B CN201410327047.9A CN201410327047A CN104280651B CN 104280651 B CN104280651 B CN 104280651B CN 201410327047 A CN201410327047 A CN 201410327047A CN 104280651 B CN104280651 B CN 104280651B
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- 238000012360 testing method Methods 0.000 title claims abstract description 146
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 239000000523 sample Substances 0.000 claims abstract description 44
- 230000005540 biological transmission Effects 0.000 claims abstract description 27
- 238000001514 detection method Methods 0.000 claims description 25
- 238000007689 inspection Methods 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012956 testing procedure Methods 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 238000004804 winding Methods 0.000 description 3
- 101100004188 Arabidopsis thaliana BARD1 gene Proteins 0.000 description 2
- 101100328883 Arabidopsis thaliana COL1 gene Proteins 0.000 description 2
- 101100328890 Arabidopsis thaliana COL3 gene Proteins 0.000 description 2
- 101100328886 Caenorhabditis elegans col-2 gene Proteins 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
The present invention discloses a kind of test system and semiconductor elements.The test system, to detect whether that one or more associativity disabled status betide in the transmission path of a tester table and a wafer to be measured during the burned test of wafer scale.An embodiment according to the present invention, the test system include a probe card and n chip.The probe card includes m the first signal contacts, to receive the m test signal from the tester table；N second signal contact, to provide the tester table n test result；With a crosspoint array.The probe card is by multiple probes and the wafer contacts to be measured.In this way, which can detect whether that one or more short circuits or open circuit betide in the transmission path of the tester table and the wafer to be measured.
Description
Technical field
The present invention relates to a kind of test system and a kind of semiconductor elements being implemented in the test system.
Background technology
In traditional integrated circuit (Integrated Circuit, IC) manufacturing process, the IC of multiple dispersions can be with chip
(chip) or the form of crystal grain (dice) is formed on semiconductor wafer (wafer).After the completion of manufacturing process, the wafer meeting
Cutting is to be separated into independent chip.Each chip is then encapsulated into module or is incorporated into larger system.
Due to the defect of single or multiple step in the inborn flaw of wafer or manufacturing process, the crystalline substance after some encapsulation
Piece possibly can not be operated according to desired design.These defects may show in early days or may chip operate a period of time after
It can just show.In order to identify that the chip of these defects, burned (burn-in) step can be implemented on chip.In burned step
In, chip can be heated to a high temperature, and a test controller can statically or dynamically apply one group of bias voltage to selected
So that selected chip has electric current to flow through on chip.After burned step, chip can undergo a Wafer probe (Chip
Probe, CP) testing procedure to be to filter out the chip of defect before packaging.
In traditional wafer scale (wafer level) burned step, chip only receives one group of bias voltage, without passing
Data are returned to test controller.Therefore, which can not confirm whether burned step certainly executes.For example, it is controlling
There may be the state of short circuit or open circuit between device and chip processed so that bias voltage is not transferred to chip.Therefore, burned
Step does not actually accomplish, and controller may judge the chip of defect by accident in subsequent CP testing procedures.
Invention content
One of the objects of the present invention is to provide a kind of test systems, to execute the burned test of a wafer scale.
An embodiment according to the present invention, the test system include a probe card and n chip.Each probe card includes m
First signal contact, n second signal contact and a crosspoint array.These m the first signal contacts come from a survey to receive
M test signal of m the first TCH test channels of commissioning stage, m are a positive integer.These n second signal contact, to provide
For n test result to n the second TCH test channels of the tester table, n is a positive integer.The crosspoint array includes (m+1) a row
It is arranged with n, it is each with n contact per a line to arrange with (m+1) a contact, wherein n contact in a first row
Each is electrically connected in n second signal contact corresponding one, and each of the n contact in one i-th row is electric
Property be connected in m the first signal contacts corresponding one, wherein i is positive integer, and 2≤i≤(m+1).
Another object of the present invention is to provide a kind of semiconductor elements, to execute associativity test.
An embodiment according to the present invention, the semiconductor element include m input pad, a detection circuit and an inspection pad.This
Corresponding one in m test signal of each reception from an outside board in a little m input pads.The detection circuit is used
To receive the input signal from the m input pad to generate an output signal in the inspection pad.The inspection pad is providing this
Output signal to the tester table.
Description of the drawings
Fig. 1 is shown in conjunction with one embodiment of the invention executing the block diagram of the test system of a wafer scale burned test
Fig. 2 shows the planar configuration of the probe card in conjunction with one embodiment of the invention.
Fig. 3 shows the running of the test system when associativity is tested in conjunction with one embodiment of the invention.
Fig. 4 shows the circuit diagram of the detection circuit of the chip in conjunction with one embodiment of the invention.
Fig. 5 shows the sequence diagram when running of the detection circuit in Fig. 4.
Fig. 6 shows the running of the test system when associativity is tested.
Fig. 7 shows the running of the test system when associativity is tested.
Fig. 8 shows the running of the test system when associativity is tested.
Fig. 9 shows the planar configuration of the probe card in conjunction with another embodiment of the present invention.
Figure 10 shows the partial circuit diagram of the chip in conjunction with one embodiment of the invention.
Figure 11 shows the sequence diagram when enable circuit running of Figure 10.
Specific implementation mode
The present invention discloses a test system to execute burned test (the wafer level burn-in of a wafer scale herein
test)." the burned test of wafer scale " herein, which refers to chip, to carry out an associativity (continuity) survey in wafer scale state
Examination then carries out a burned step, finally by a CP testing procedures to filter out defective chip before packaging.
Fig. 1 is shown in conjunction with one embodiment of the invention executing the side of the test system 100 of a wafer scale burned test
Block diagram.As shown in Figure 1, the test system 100 includes a Test System Controller 10, can be an automatic testing equipment
(Automatic Test Equipment, ATE) or a general-use computer.The Test System Controller 10 is logical via one
News winding displacement 12 is connected to a measuring head (test head) 14.
The measuring head 14 may include a pedestal 16, connect a probe card (probe card) 18 whereby.The probe card 18
It is as the interface between the measuring head 14 and a wafer 22 to be measured.The probe card 18 can be via being integrated in the probe card 18
Multiple probes 20 are contacted with the wafer 22 to be measured.
The test system 100 also includes a stage 24 to place the wafer 22 to be measured.As shown in Fig. 2, the probe card 18 is wrapped
Containing multiple pad 18_1 to 18_7.These pads 18_1 to 18_7 is configured to receive the Test System Controller 10 from Fig. 1
Test signal, and test result is passed back to the Test System Controller 10.The probe card 18 also includes a crosspoint array 19, by
Multiple row ROW1, ROW2, ROW3, ROW4, and ROW5 and multiple array COL1, COL2, and COL3 are formed.Such as Fig. 2 institutes
Show, is made of three contacts per a line, and each row are made of five contacts.Contact 19_1 in the crosspoint array 19 is extremely
19_15 is configured to the chip 30,32 and 34 in transmission test signal to the wafer 22 of Fig. 1, and by corresponding spy in Fig. 1
Needle 20 passes test result back.
As shown in Figure 1, in an embodiment of the present invention, before burned step starts, the Test System Controller 10 transmission
One instruction is tested to the measuring head 14 with executing an associativity (continuity).Associativity test is determined in the measuring head 14
Whether faulty state occurs between the wafer 22 to be measured.For example, a probe 20 may damage, and it is brilliant to lead to not connection
The corresponding pad of on piece；Or the pad on chip may be short-circuited to a power cord or ground wire.When a short circuit or an open loop state occur
When on data transfer path, which can not transmit correct bias voltage to chip to be measured, also can not
It is efficiently received test result.Therefore, associativity test can be executed at the beginning to ensure to occur without short circuit or open loop state.
Fig. 3 shows the running of the test system 100 when associativity is tested in conjunction with one embodiment of the invention.Such as Fig. 3 institutes
Show, which includes one group of channel C H1 to CH4, and each channel is responsible for transferring data to corresponding pad in the probe card 18.
It more specifically illustrates, channel C H1 generates the pad 18_1 in the first test signal to the probe card 18；Channel C H2 generates the
Pad 18_2 in two test signals to the probe card 18；Channel C H3 generates the pad in third test signal to the probe card 18
18_3；And channel C H4 generates the pad 18_4 in the 4th test signal to the probe card 18.
As shown in figure 3, due to the contact 19_4,19_5 and 19_6 in the crosspoint array 19 be via a cabling 191 each other
It is electrically connected, the first test signal from channel C H1 can be sent to contact 19_4,19_5 and 19_6 simultaneously.It is similar
Ground, the second test signal from channel C H2 can be sent to contact 19_7,19_8 and 19_9 simultaneously；From the channel
The third test signal of CH3 can be sent to contact 19_10,19_11, and 19_12 simultaneously；And from the 4th of channel C H4 the
Test signal can be sent to contact 19_13,19_14, and 19_15 simultaneously.
As shown in Figure 1, the probe card 18 positioned at 22 top of wafer can be multiple in the probe card 18 via being integrated in
Probe 20 is contacted with the wafer 22 to be measured.These probes 20 are set to be connect with the configuration pad with each chip on the wafer 22 to be measured
It touches.Specifically, as shown in figure 3, in the crosspoint array 19 row COL1 contact 19_4,19_7,19_10 and 19_13 via
Corresponding probe and the pad 30_1,30_2,30_3 on chip 30 in Fig. 1, and 30_4 are electrically connected；The contact 19_5 of COL2 is arranged,
19_8,19_11, and 19_14 are electrical via the pad 32_1,32_2,32_3 on corresponding probe in Fig. 1 and chip 32, and 32_4
Connection；The contact 19_6,19_9,19_12 of COL3, and 19_15 are arranged via the pad 34_ on corresponding probe in Fig. 1 and chip 34
1,34_2,34_3, and 34_4 are electrically connected.
Illustrate the running of the test system 100 when associativity is tested referring to Fig. 1 to Fig. 3.First, the test system
100 generate the channel C H1 to CH4 in parallel test signal to the measuring head 14 via the winding displacement of communication 12.The probe card 18
After receiving the test signal from the measuring head 14, the chip 30 on these signals to the wafer 22 to be measured is transmitted, 32, and
34.After test signal of these wafer receipts from the probe card 18, operated according to these signals.Under this framework, the chip
30 pad 30_1, the pad 32_1 of the chip 32, and the pad 34_1 of the chip 34 can receive the letter of the test from channel C H1 simultaneously
Number；The pad 30_2 of the chip 30, the pad 32_2 of the chip 32, and the pad 34_2 of the chip 34 can be received simultaneously from the channel
The test signal of CH2；The pad 30_3 of the chip 30, the pad 32_3 of the chip 32, and the pad 34_3 of the chip 34 can be received simultaneously
Test signal from channel C H3；The pad 30_4 of the chip 30, the pad 32_4 of the chip 32, and the chip 34 pad 34_4
The test signal from channel C H4 can be received simultaneously.
After receiving the test signal from the probe card 18, a detection circuit can be used to have detected whether an associativity
Disabled status, such as an open circuit or short-circuit state, betide the transmission path between the measuring head 14 and the wafer 22 to be measured.Figure
Inspection of 4 displays in conjunction with the detection circuit 301 of the chip 30 of one embodiment of the invention, the detection circuit 321 of chip 32, and chip 34
The circuit diagram of slowdown monitoring circuit 341.As shown in figure 4, the detection circuit 301 of the chip 30 includes a logic circuit 302, a PMOS crystal
A pipe M1 and NMOS transistor M2.In the present embodiment, the logic circuit 302 is by an AND gate circuit X1, a phase inverter X2, and one
NAND gate circuit X3 and an OR-NOT circuit X4 are formed.The detection of the detection circuit 321 and the chip 34 of the chip 32
The circuit structure of circuit 341 is identical as the detection circuit 321 of the chip 32, therefore the details of circuit will not be described in great detail.
As shown in figure 4, the detection circuit 301 of the chip 30 receives this by these pads 30_1,30_2,30_3 and 30_4
After a little signal L1, L2, L3 and L4, a testing result L5 will produce in remaining pad 30_5.Similarly, detection of the chip 32
After circuit 321 receives these signals L1, L2, L3 and L4 by these pads 32_1,32_2,32_3 and 32_4, in remaining pad 32_
5 will produce a testing result；The detection circuit 341 of the chip 34 receives this by these pads 34_1,34_2,34_3, and 34_4
After a little signal L1, L2, L3 and L4, a testing result will produce in remaining pad 34_5.
Fig. 5 shows the sequence diagram when running of the detection circuit 301 in Fig. 4.As shown in figure 5, before time t1, the test
Signal L1 is located at a logical zero level.When signal L1 is located at logical zero level, PMOS transistor M1 and NMOS transistor in Fig. 4
M2 ends so that the signal on pad 30_5 is suspension joint signal.After time t1, in input signal L2 to L4 it is primary only there are one
Signal changes its logic level.For example, input signal L2 to L4 is respectively positioned on 1 level of logic between times ti and ta.It connects
It, input signal L2 can be converted to logical zero level between moments t 2 and t 3, and other signals L3 and L4 remain unchanged.The inspection
Slowdown monitoring circuit 301 can provide output signal L5 according to the Different Logic level of input signal L2 to L4.The detection circuit 301 it is true
It is as follows to be worth table：
Table 1
| L1 | L2 | L3 | L4 | L5 |
| 0 | X | X | X | Hi-Z |
| 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
By the operation result of table 1, which can detect whether that an open circuit or short-circuit state betide the survey
Try the transmission path between head 14 and the wafer 22 to be measured.For example, when input signal L2 is converted to logical zero level, and its
It, can be in logical zero level according to the operation result output signal L5 of table 1 when his signal L3 and L4 remain unchanged.Therefore, if detection electricity
The signal that road 301 generates is to indicate that the pad 30_2 of the detection circuit 301 may when being located at 1 level of logic rather than logical zero level
It is short-circuited to a power cord, and the signal for padding 30_2 is pulled to 1 level of logic.
As shown in fig. 6, after testing result results from pad 30_5,32_5 and 34_5, these signals can be via in Fig. 1
Probe is sent to the contact 19_1,19_2 in same a line ROW1 in the crosspoint array 19, and 19_3.Due to these contacts 19_
1,19_2, and 19_3 can be electrically connected to these pads 18_5,18_6, and 18_7 individually via cabling.These contacts 19_1,19_
Signal on 2 and 19_3 can be sent to these pads 18_5,18_6 and 18_7, to channel C H5, the CH6 on measuring head 14, and
CH7.In this way, the Test System Controller 10 in Fig. 1 can come from via the measuring head 14 and the winding displacement of communication 12 reception
Chip 30,32, and 34 test result.By these test results are analyzed, whether the Test System Controller 10 is it can be seen that have
Such as an associativity disabled status, such as an open circuit or short-circuit state, betide between the measuring head 14 and the wafer 22 to be measured
Transmission path.
For example, as shown in fig. 7, an associativity disabled status results from the chip 32.In this example, in the chip 32
Pad 32_2 be short-circuited to a power cord (not being painted).As shown in fig. 7, during associativity is tested, channel C H1 transmission is located at
First test signal of 1 level of logic, channel C H2 transmission is positioned at second test signal of logical zero level, the channel
CH3 transmission is located at the third test signal of 1 level of logic, and channel C H4 transmission is positioned at the 4th test of 1 level of logic
Signal.Then, which can be sent to the chip 30 via pad 19_4,19_5 and 19_6, corresponding probe
Pad 30_1, the pad 32_1 of the chip 32, and the pad 34_1 of the chip 34.According to similar fashion, other test signals can be sent to
The corresponding pad of the chip 30, the chip 32, and the chip 34.Therefore, if being generated without associativity disabled status, the inspection of the chip 32
Slowdown monitoring circuit 321 can export logical zero level as shown in the truth table of table 1.
However, in this example since pad 32_2 is short-circuited to the power cord, therefore the letter that detection circuit 321 is received in pad 32_2
Number be 1 level of logic.Therefore, as shown in figure 8, the detection circuit 321 will produce the output signal of 1 level of logic in pad 32_5.
Output signal can then be sent to corresponding probe caused by pad 30_5,32_5 and 34_5, the probe card 18, the test
First 14 channel C H5, CH6 and CH7 eventually arrives at the Test System Controller 10.Output signal due to pad 32_5 and the survey
The result that test system controller 10 is predicted is different, and the Test System Controller 10 is it can be seen that there is an associativity disabled status
Transmission path between channel C H2 and the chip 32.
According to the function mode described above, which can be by changing first, second, third and the
Logic level one of in four test signals detects whether associativity disabled status.When first, second,
When having logic level change one of in the three and the 4th test signal, three test results are can get.Each test result
Indicate whether chip 30,32, and 34 configuration pad receive test signal really.In other words, when the Test System Controller 10 passes through
When generating configuration pad of four parallel test signals to chip 30,32 and 34 by channel C H1, CH2, CH3 and CH4, have
12 test results return to the Test System Controller 10 via channel C H5, CH6, and CH7.
As shown in Figure 7 and Figure 8, in 12 test results, wherein four have indicated whether that one or more associativities fail
Situation betides the transmission path between channel C H1 and the pad 30_1 of the chip 30, is happened at channel C H2 and the chip 30
Pad 30_2 between transmission path, the transmission path being happened between the pad 30_3 of channel C H3 and the chip 30, and occurring
Transmission path between channel C H4 and the pad 30_4 of the chip 30；Wherein four have indicated whether one or more associativities
Disabled status betides the transmission path between channel C H1 and the pad 32_1 of the chip 32, is happened at channel C H2 and the crystalline substance
Transmission path between the pad 32_2 of piece 32, the transmission path being happened between channel C H3 and the pad 32_3 of the chip 32, and
The transmission path being happened between channel C H4 and the pad 32_4 of the chip 32；Remaining four have indicated whether one or more
Associativity disabled status betides the transmission path between channel C H1 and the pad 34_1 of the chip 34, is happened at channel C H2
Transmission path between the pad 34_2 of the chip 34, the transmission being happened between channel C H3 and the pad 34_3 of the chip 34
Path, and it is happened at channel C H4 and the transmission path of the chip 34 padded between 34_4.
As shown in figure 3, the contact 19_4,19_5 and 19_6 in the crosspoint array 19 are electric each other via the electrical cabling 191
Property connection.Since the contact mutually gone together is connected to each other, noise may be mutually coupled.In order to promote vulnerability to jamming, resistance can be arranged
To adjacent contact.Fig. 9 shows the planar configuration of the probe card 18 in conjunction with one embodiment of the invention.As shown in figure 9, a resistance
R1 is set between contact 19_4 and pad 18_1, and a resistance R2 is set between contact 19_5 and pad 18_1, and one
Resistance R3 is set between contact 19_6 and pad 18_1.These resistance R1, R2 and R3 are as current-limiting resistance, to be limited in
One or more contacts are short-circuited to short circuit current when ground wire or power cord.In addition, a resistance R4 is set to pad 18_5 and certain
Between voltage source (such as a ground voltage).Therefore, when in Fig. 4 PMOS transistor M1 and when NMOS transistor M2 cut-off, the pad
18_5 can avoid suspension joint.
As shown in Figure 1, after completing associativity test, betide between the measuring head 14 and these chips 30,32 and 34
Transmission path on associativity disabled status can be detected and exclude, then these chips 30,32 and 34 can carry out burned step
Suddenly.Burned step is related to powering to these chips 30,32 and 34, these chips 30,32 and 34 is heated to accelerate early stage to lose
Imitate the failure speed of chip.After the completion of burned step and subsequent CP testing procedures, that is, the burned test of a wafer scale is completed
Afterwards, which can be cut into independent chip.Having defective chip can be dropped, and other good chips can be assembled into
The element of encapsulation.
As shown in figure 4, the chip 30 includes multiple pad 30_1 to 30_6.These pads 30_1 to 30_6 can be classified as testing cushion
Or joint sheet.These testing cushions are as the configuration pad for being used for testing chip in wafer scale, and these joint sheets are intended for
The configuration pad of conducting wire connection.As described above, these pads 30_1 to 30_5 is for testing the chip 30.Extremely by these pads 30_1
30_5, test signal can be input to the chip 30 and test result can export.
Joint sheet is the lead frame (lead for being connected to an encapsulation by a metal wire in encapsulating engagement step
frame).In order to allow most pad 30_1 to 30_5 to be used as testing cushion and joint sheet simultaneously, needed after the encapsulation of chip 30
Want a logic circuit with the not enable detection circuit 301.Figure 10 shows the part of the chip 30 in conjunction with one embodiment of the invention
Circuit diagram.As shown in Figure 10, which also includes an enable circuit 303 and an internal circuit 305.The enable circuit 303 wraps
(latch) 304 is fastened containing a pull-up element M3 and one.This is fastened 304 and includes a pair of back-to-back phase inverter, wherein phase inverter X6 conducts
(feed-forward) phase inverter is sent before one, and phase inverter X7 is as feedback (feedback) phase inverter.In order to make Figure 10's
Circuit suitably operates, and phase inverter X7 is the weaker phase inverter of a driving capability, therefore weaker compared with having for phase inverter X6
Fan-out capability.
The running of the enable circuit 303 is described as follows.During the burned test of wafer scale, the Test System Controller 10 production
The test signal of life row is to test the chip 30,32 and 34 on the wafer 22 to be measured, as shown in Figure 1.In this situation, exist
The detection circuit 301 and the enable circuit 303 receive the test signal L1 from controller 10 via pad 30_1 in Figure 10, and
Signal L1 has 1 level of logic.Therefore, which can execute in response to the test signal of these pads 30_2 to 30_4
The logical operation of table 1.The test result then can send the Test System Controller 10 back to carry out next step by pad 30_5
Analysis.
After the completion of wafer scale burned test, having defective chip can be dropped, and other good chips can be sealed
Fill step.After the completion of encapsulation step, the joint sheet of chip can be bonded to packaging conductive wire, therefore chip can receive outer member
Signal.As shown in Figure 10, pad 30_1 is used to as testing cushion rather than joint sheet；These pads 30_2 is used to make to 30_5
For testing cushion and joint sheet；And pad 30_6 is used to as joint sheet rather than testing cushion.Therefore, these pads 30_2 to 30_6
It can receive the signal of outer member after packaging, and the internal circuit can be operated accordingly.In order to avoid signal interference, the detection
Circuit 301 can selectively be operated according to the logic level of the signal on pad 30_1.
As shown in Figure 10, during the burned test of wafer scale, since chip 30 connects via corresponding probe and probe card 18
It touches, signal L1 can be pulled to 1 level of logic.After receiving 1 level of logic, which can be according to these pads 30_
2 operate to the signal of 30_4.Due to the weak output driving ability of weak phase inverter X7, the signal on pad 30_1 can overdrive this
The output of weak phase inverter X7, to allow this to fasten 304 change states.However, after the chip 30 encapsulation, pad 30_1 will not be contacted
Outer member, therefore the logic level on pad 30_1 can change and be determined by the enable circuit 303.
Figure 11 shows the sequence diagram when enable circuit 303 of Figure 10 operates.As shown in figure 11, this encapsulated wafer 30 when
Between t0 when power.In time t0, a power supply signal PU is in logical zero level, therefore the PMOS transistor M3 conductings in Figure 10.When
When PMOS transistor M3 conductings, which can be initially to a logical zero level.In time t1, power supply is supplied
VDD has been higher than a critical voltage level, therefore power supply signal PU understands transition to 1 level of logic.When power supply signal PU is reached
When 1 level of logic, PMOS transistor M3 cut-offs, therefore the bolt 304 keeps lock-out state, and continue to provide signal L1 in the logic
0 level.After receiving signal L1, which generates the signal N1 with 1 level of logic and generates with logical zero
The signal N2 of level so that PMOS transistor M1 and NMOS transistor M2 cut-offs.In this way, which can seal
Not enable after dress.
The technology contents and technical characterstic of the present invention have revealed that as above, however those skilled in the art are still potentially based on this hair
Bright teaching and enlightenment and make various replacements and modification without departing substantially from spirit of that invention.Therefore, protection scope of the present invention is answered
It is not limited to embodiment, and should include various replacements and modification without departing substantially from the present invention, and is covered by the claim of the present invention.
Claims (10)
1. a kind of test system, to execute the burned test of a wafer scale, including：
One probe card；
M the first signal contacts, to receive m test signal of the m from a tester table the first TCH test channels, m is
One positive integer；
N second signal contact, to provide n test result to n the second TCH test channels of the tester table, n mono-
Positive integer；With
One crosspoint array, including (m+1) a row and n row, per a line, with n contact, each arrange connects with (m+1) is a
Point, wherein each of n contact in a first row is electrically connected in n second signal contact corresponding one, and
Each of n contact in one i-th row is electrically connected in m the first signal contacts corresponding one, and wherein i is just whole
Number, and 2≤i≤(m+1)；And
N chip, each chip include：
M input pad, wherein each in these input pads, by the m of wherein one row in n row in the crosspoint array
A contact receives in the m test signal from the tester table corresponding one；
One detection circuit, to receive the input signal from the m input pad to generate an output signal in an inspection pad；With
The inspection pad provides n test result by a contact of wherein one row in n in crosspoint array row
One of them is to the tester table.
2. test system according to claim 1, wherein the test system sequentially execute associativity test before packaging,
One burned step and a wafer probe test step.
3. test system according to claim 2, wherein the test system are by one of them in m test signal of change
Logic level to obtain n test result.
4. test system according to claim 3, the wherein tester table determine whether there are one by the n test result
Short circuit betides the transmission path between the probe card and these chips.
5. test system according to claim 3, the wherein tester table determine whether there are one by the n test result
Open circuit betides the transmission path between the probe card and these chips.
6. test system according to claim 1, wherein each of n contact in i-th row are by resistance electricity
Property be connected in m the first signal contacts corresponding one.
7. test system according to claim 1, wherein each in these second signal contacts are by resistance electricity
Property connection one fixed voltage source.
8. test system according to claim 1, the wherein detection circuit include：
One logic circuit, to receive these input signals from the m input pad；
One PMOS transistor has a grid to receive one first output signal from the logic circuit；And
One NMOS transistor has a grid to receive one second output signal from the logic circuit；
Wherein PMOS transistor and the NMOS transistor is electrically connected to the inspection pad.
9. test system according to claim 8, the wherein inspection pad are used to test and engage purposes, this m input
Only to test-purpose one of in pad, and other persons in these m input pad are used to test and engage purposes.
10. test system according to claim 9, the wherein chip include：
One pull-up element, to receive an enabling signal to provide a pull up signal；
One first phase inverter is closed after the wafer package whereby to receive the pull up signal to provide a not enable signal
The PMOS transistor and the NMOS transistor；And
One second phase inverter, to receive the not enable signal to generate the pull up signal；
Wherein first phase inverter has weaker driving capability compared with the second phase inverter.
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| US201361844705P | 2013-07-10 | 2013-07-10 | |
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| US14/315,127 | 2014-06-25 | ||
| US14/315,127 US9575114B2 (en) | 2013-07-10 | 2014-06-25 | Test system and device |
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| JP6515007B2 (en) * | 2015-09-30 | 2019-05-15 | 東京エレクトロン株式会社 | Wafer inspection method and wafer inspection apparatus |
| KR102637795B1 (en) * | 2017-02-10 | 2024-02-19 | 에스케이하이닉스 주식회사 | Semiconductor device |
| CN111044961B (en) * | 2018-10-15 | 2022-06-10 | 吴茂祥 | Test machine self-checking system and test method |
| TWI732326B (en) | 2019-10-29 | 2021-07-01 | 華邦電子股份有限公司 | Short-circuit probe card, wafer test system, and fault detection method for the wafer test system |
| CN113030535A (en) * | 2019-12-09 | 2021-06-25 | 华邦电子股份有限公司 | Short circuit probe card, wafer test system and fault cause detection method of system |
| CN113589140A (en) * | 2021-07-16 | 2021-11-02 | 苏州芯迈智能科技有限公司 | Wafer test system and method of TOF chip |
| CN114152858A (en) * | 2022-02-08 | 2022-03-08 | 广州粤芯半导体技术有限公司 | Electrical test device and test method for cutting channel device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6046943A (en) * | 1998-03-10 | 2000-04-04 | Texas Instuments Incorporated | Synchronous semiconductor device output circuit with reduced data switching |
| CN101501511A (en) * | 2006-06-06 | 2009-08-05 | 佛姆法克特股份有限公司 | Method of expanding tester drive and measurement capability |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100362702B1 (en) * | 2001-01-15 | 2002-11-29 | 삼성전자 주식회사 | Redundant decoder circuit |
| US6911814B2 (en) * | 2003-07-01 | 2005-06-28 | Formfactor, Inc. | Apparatus and method for electromechanical testing and validation of probe cards |
| TWI286606B (en) * | 2004-03-16 | 2007-09-11 | Gunsei Kimoto | Electric signal connecting device, and probe assembly and prober device using it |
-
2014
- 2014-07-10 CN CN201410327047.9A patent/CN104280651B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6046943A (en) * | 1998-03-10 | 2000-04-04 | Texas Instuments Incorporated | Synchronous semiconductor device output circuit with reduced data switching |
| CN101501511A (en) * | 2006-06-06 | 2009-08-05 | 佛姆法克特股份有限公司 | Method of expanding tester drive and measurement capability |
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