CN104280614B - Structure and method for measuring relevant parameters of sidewall thickness of MOS devices - Google Patents
Structure and method for measuring relevant parameters of sidewall thickness of MOS devices Download PDFInfo
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Abstract
The invention provides a method for measuring relevant parameters of the sidewall thickness of MOS devices. The method comprises the steps that the resistance of each MOS device array in at least four MOS device arrays is measured, wherein each MOS device array comprises at least two equidistantly arrayed MOS devices, a first lead-out part, a second lead-out part and a third lead-out part; the MOS devices are equal in channel width and channel length and each comprise sidewalls which are equal in width and are located on the two sides of a grid electrode; source regions or drain regions of the two MOS devices on the outermost side of each MOS device array are led out through the corresponding first lead-out part and the second corresponding lead-out part respectively; the grid electrodes of all the MOS devices are connected together and led out through the third lead-out parts, and different MOS device arrays are unequal in at least one of device quantity, channel length and device distance but equal in channel width; moreover, the first lead-out part and the second lead-out part of each MOS device array have the same structure; according to measuring results, the magnitude of resistance underneath the sidewalls is calculated.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of measurement MOS device side wall thicknesses
The structures and methods of relevant parameter.
Background technology
Metal oxide semiconductor transistor include grid, be located at grid both sides substrate in source electrode, drain electrode,
Conducting channel below grid, and the gate oxide between described conducting channel and grid.In grid
Side wall is formed with the side wall of all around gate.On the one hand, side wall can be used for protecting grid；On the other hand,
Grid can prevent heavy dose source electrode and drain electrode injection get too close to conducting channel so that it may happen that
Turn between source, leakage.
Semiconductor fabrication develops to higher technology node, with VLSI（Very Large Scale
Integration, super large-scale integration）In technology（Especially in fin structure or three grid knot
The 3-D structure such as structure）, the continuous reduction of device size, lead to the size of grid less and less, below grid
Substrate in conducting channel shorter and shorter, the side wall therefore, it is possible to reduce leakage current between source and drain seems particularly
Important.
Need a kind of method simply and effectively measuring MOS device side wall thicknesses relevant parameter at present.
Content of the invention
In one aspect, the present invention provides a kind of method of measurement MOS device side wall thicknesses relevant parameter,
Including：
Measure the resistance of each of at least four MOS device arrays MOS device array, wherein
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS device
Part has identical channel width and length, and all includes the side wall of the same widths positioned at grid both sides；
First and second extensions, respectively by the source of outermost for MOS device array two MOS device
Area or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction,
Different MOS device arrays each other in number of devices, channel length and device pitch at least it
Different and channel width is identical on one；And the first and second lead divisions of each MOS device array
Divide and there is identical construction；
Calculate the size of resistance under side wall according to measurement result.
On the other hand, the present invention provides a kind of structure for measuring MOS device side wall thicknesses relevant parameter,
Including：
At least four MOS device arrays, wherein
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS device
Part has identical channel width and length, and all includes the side wall of the same widths positioned at grid both sides；
First and second extensions, respectively by the source of outermost for MOS device array two MOS device
Area or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction, wherein
Different MOS device arrays each other in number of devices, channel length and device pitch at least it
Different and channel width is identical on one；And the first and second lead divisions of each MOS device array
Divide and there is identical construction.
The method of the embodiment of the present invention can simply, practicably detect related to MOS device side wall thicknesses
Parameter.
Brief description
By reading the detailed description that non-limiting example is made made with reference to the following drawings, this
Bright other features, objects and advantages will become more apparent upon：
Fig. 1 is the stream of the method for the measurement MOS device side wall thicknesses relevant parameter according to the embodiment of the present invention
Journey schematic diagram；
Fig. 2 is for measuring the test of MOS device side wall thicknesses relevant parameter according to the embodiment of the present invention
The schematic top plan view of one specific embodiment of structure；
Fig. 3 is the generalized section along AA ' for the test structure according to Fig. 3；
In accompanying drawing, same or analogous reference represents same or analogous part.
Specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright embodiment is described in detail.
Embodiments of the invention are described below in detail, the example of described embodiment is shown in the drawings, wherein
Same or similar label represents same or similar element or has same or like function from start to finish
Element.Embodiment below with reference to Description of Drawings is exemplary, is only used for explaining the present invention, and
It is not construed as limiting the claims.
Following disclosure provides many different embodiments or example for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the part and setting of specific examples is described.When
So, they are only merely illustrative, and purpose does not lie in the restriction present invention.Additionally, the present invention can be not
With repeat reference numerals in example and/or letter.This repeat to be for purposes of simplicity and clarity, its
Body does not indicate the relation between discussed various embodiment and/or setting.Additionally, the invention provides each
Plant the example of specific technique and material, but those of ordinary skill in the art can be appreciated that other techniques
Applicable property and/or other materials use.In addition, fisrt feature described below is in second feature
It " on " structure can include the first and second features be formed as directly contact embodiment it is also possible to include
Other feature is formed at the embodiment between the first and second features, and such first and second features may
It is not directly contact.It should be noted that part illustrated in the accompanying drawings is not drawn necessarily to scale.This
Bright eliminate the description to known assemblies and treatment technology and process to avoid being unnecessarily limiting the present invention.
The method of the side wall thicknesses detection that the present invention provides, by measurement through the different test knot designing
Structure, it is possible to obtain the all-in resistance of each test structure simultaneously obtains test from the all-in resistance calculating of different test structures
Various pieces resistance value respectively in structure.For example：Under device spacer region resistance, grid（Channel region）Electricity
Resistance under resistance, end resistance and side wall.It is hereby achieved that resistance under the side wall related to side wall thicknesses.
With reference to Fig. 1, embodiments of the invention provide a kind of side of measurement MOS device side wall thicknesses relevant parameter
Method, including：
Measure the resistance of each of at least four MOS device arrays MOS device array, wherein
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS device
Part has identical channel width and length, and all includes the side wall of the same widths positioned at grid both sides；
First and second extensions, respectively by the source of outermost for MOS device array two MOS device
Area or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction,
Different MOS device arrays each other in number of devices, channel length and device pitch at least it
Different and channel width is identical on one；And the first and second lead divisions of each MOS device array
Divide and there is identical construction；
Calculate the size of resistance under side wall according to measurement result.
With reference to figs. 2 to Fig. 3, according to one embodiment of present invention, each MOS device array includes：
At least one active area on a semiconductor substrate（100）；
The grid of at least two equidistant arrangements（200）, on described Semiconductor substrate, perpendicular to
Described active area（100）, and connected by grid connecting portion；
Side wall（210）, positioned at each grid（200）Both sides；
First and second contact plungers（300）, respectively by described active area（100）Both sides draw；
First and second metal lines（400）, connect described first and second contact plungers respectively（300）；
3rd contact plunger, described grid connecting portion is drawn；
3rd metal line（400）, connect described second contacting metal（300）.
Below with reference to Fig. 1, in conjunction with the test structure of Fig. 2 to Fig. 3, describe the method for the present invention in detail.
Step S101, the resistance of each of measurement at least four MOS device arrays MOS device array.
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS device
Part has identical channel width and length, and all includes the side wall of the same widths positioned at grid both sides；
First and second extensions, respectively by the source of outermost for MOS device array two MOS device
Area or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction.
Fig. 2 and Fig. 3 shows an exemplary top view for MOS device array and sectional view, at other
In embodiment, MOS device array can also have different constructions.As illustrated, the MOS in this embodiment
Device array includes：At least one active area 100 on a semiconductor substrate, 6 shown in the present embodiment
The equidistantly active area 100 of arrangement.In other embodiments, can there is more or less active area.
The grid 200 of at least two equidistant arrangements, on described Semiconductor substrate, perpendicular to described active
Area 100, and connected by grid connecting portion 201.Side wall 210, positioned at the both sides of each grid 200.First
With the second contact plunger 300,301, respectively the both sides of described active area 100 are drawn；First and second gold medals
Belong to wiring 400,401, connect described first and second contact plungers 300,301 respectively；3rd contact is inserted
Plug 500, described grid connecting portion is drawn；3rd metal line 600, connects described 3rd contact plunger
500.
In structure shown in Fig. 2 and Fig. 3, the position of each grid 200 and active area 100 intersection forms one
Individual MOS transistor.Because MOS transistor width is active area 100 on the direction that grid 200 extends
Same grid 200, primarily to increasing detection electric current, therefore, can be covered in effect by the increase of quantity
The multiple MOS transistors covering multiple active areas 100 formation are considered as a big MOS transistor.This area skill
Art personnel are appreciated that the active area 100 that only one extends can also implement the present invention.
The MOS transistor that different grids 200 are formed（Or big MOS transistor mentioned above）Deng between
Away from arrangement, there is identical channel width and length, and all include the identical width positioned at grid 200 both sides
The side wall of degree.
As shown in figure 3, the leakage of the first contact plunger 300, the first metal line 400 and rightmost side MOS device
Area constitutes the first extension.Second contact plunger 301, the second metal line 401 and leftmost side MOS device
The source region of part constitutes the second extension.First and second extensions are respectively by MOS device array outermost
The source region of two MOS device of side or drain region are drawn.
Grid connecting portion 201, the 3rd contact plunger 500 and the 3rd metal line 600 constitute the 3rd lead division
Point, the grid of all MOS device is linked together extraction.In measurement as described below, the 3rd draws
Go out part and apply the magnitude of voltage that identical is more than threshold voltage, and measure MOS device when being operated in linear zone
Array is from the first extension to the resistance of the second extension.
As shown in figure 3, all-in resistance R of this MOS device arraytotalIncluding the first extension and the second extraction
Partial resistance Rend, the resistance R of the spacer region between MOS devicesd, resistance R under gridug, and and MOS
Resistance R under the related parameter side wall of the side wall thicknesses of devicespacer.
Embodiments of the invention pass through the different MOS device array through design for the measurement, obtain each MOS
The all-in resistance of device array.Different MOS device arrays can be in the channel length of MOS device, MOS
Different in the quantity of the spacing between device and MOS device.And it is total from different MOS device arrays
Resistance calculations obtain various pieces resistance value respectively in test structure.For example：Change with device interval
Device spacer region resistance Rsd, with the grid of changes in channel length（Channel region）Resistance Rug, first extraction
Part and the resistance R of the second extensionendAnd under the parameter side wall related to the side wall thicknesses of MOS device
Resistance Rspacer.
In general, all-in resistance R of above-mentioned MOS device arraytotalCan be written as equation below：
Rtotal=2*Rend+（N-1）*Rsd+N*Rug+2*N*Rspacer（1）
Wherein, N is the number of MOS device or above-mentioned " big MOS device " in MOS device array.
Namely the number of grid 200.For example, 5 grids shown in Fig. 2 and Fig. 3.By design, keep Rend
Constant, for example keep the construction of the first and second extensions constant, and change Rsd, for example, pass through to change
The space D of MOS device；Change Rug, for example, pass through to change channel length L of MOS device；And/or change
Become quantity N of grid, can obtain changeless related to side wall thicknesses by matching test data
Resistance value Rspacer.
For different MOS device arrays, keep the construction of the first and second extensions constant, and
Using the bias of identical grid voltage and the first and second extensions in test process（For example make device
Always work in linear zone）.In formula（1）Middle 2*RendFor constant.Due to wall thickness on the upside of same chip
Spend essentially identical, therefore 2*N*RspacerAlso it is constant.RsdLinear function R for device pitch Dsd=rsd*D；
RugLinear function R for channel length Lug=rug* L, formula（1）Can be rewritten as：
Rtotal=2*Rend+（N-1）*rsd*D+N*rug*L+2*N*Rspacer（2）
Wherein grid quantity N, device pitch D and channel length L are all the design parameters that can know.Cause
This, for solving Rend, rsd, rug, and RspacerThe resistance of at least four MOS device arrays only need to be measured,
These MOS device arrays are each other in number of devices（In the situation that there are multiple active areas in the application
Lower finger grid quantity）, at least one device pitch and channel length are upper there is different, and other specification phase
With.
Step S102, calculates the size of resistance under side wall according to measurement result.Specifically can be according to survey
All-in resistance R of each MOS device array in amount for example, at least four MOS device arrays of resulttotal1,
Rtotal2, Rtotal3, Rtotal4Etc. and the known parameters number of devices of each MOS device array, device pitch
With channel length N1、D1、L1, N2、D2、L2, N3、D3、L3, N4、D4、L4Etc., solve
By formula（2）At least four equations obtaining, obtain parameter Rend, rsd, rug, and Rspacer.
According to embodiments of the invention, can effectively detect the parameter related to the thickness of side wall, i.e. side
Resistance R under wallspacer.
Although be described in detail it should be understood that without departing from the present invention with regard to example embodiment and its advantage
Spiritual and defined in the appended claims protection domain in the case of, these embodiments can be carried out respectively
Plant change, substitutions and modifications.For other examples, those of ordinary skill in the art it should be readily appreciated that
While keeping in the scope of the present invention, the order of processing step can change.
Additionally, the range of application of the present invention be not limited to the specific embodiment described in specification technique,
Mechanism, manufacture, material composition, means, method and step.From the disclosure, as this
The those of ordinary skill in field will readily appreciate that, at present having existed or will develop later
Technique, mechanism, manufacture, material composition, means, method or step, wherein they execute and the present invention
The result that the function that is substantially the same of corresponding embodiment of description or acquisition are substantially the same, can according to the present invention
To apply to them.Therefore, claims of the present invention are intended to these techniques, mechanism, system
Make, material composition, means, method or step are included in its protection domain.
Claims (4)
1. a kind of method of measurement MOS device side wall thicknesses relevant parameter, including：
Measure the resistance of each of at least four MOS device arrays MOS device array, according to measurement
The size of resistance under the resistance calculations side wall of the MOS device array going out；Wherein
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS
Device has identical channel width and length, and all includes the side of the same widths positioned at grid both sides
Wall；
First and second extensions, respectively by outermost for MOS device array two MOS device
Source region or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction,
Different MOS device arrays each other in number of devices, channel length and device pitch at least it
Different and channel width is identical on one；And the first and second lead divisions of each MOS device array
Divide and there is identical construction.
2. method according to claim 1, wherein each MOS device array include：
At least one active area (100) on a semiconductor substrate；
The grid (200) of at least two equidistant arrangements, on described Semiconductor substrate, perpendicular to
Described active area (100), and connected by grid connecting portion；
Side wall (210), positioned at the both sides of each grid (200)；
The both sides of described active area (100) are drawn by the first and second contact plungers (300,301) respectively
Go out；
First and second metal lines (400,401), connect respectively described first and second contact plungers (300,
301)；
3rd contact plunger (500), described grid connecting portion is drawn；
3rd metal line (600), connects described 3rd contact plunger (500).
3. a kind of structure for measuring MOS device side wall thicknesses relevant parameter, including：
At least four MOS device arrays, wherein
Each MOS device array includes：The MOS device of at least two equidistant arrangements, described MOS
Device has identical channel width and length, and all includes the side of the same widths positioned at grid both sides
Wall；
First and second extensions, respectively by outermost for MOS device array two MOS device
Source region or drain region are drawn；And
3rd extension, the grid of all MOS device is linked together extraction, wherein
Different MOS device arrays each other in number of devices, channel length and device pitch at least it
Different and channel width is identical on one；And the first and second lead divisions of each MOS device array
Divide and there is identical construction.
4. structure according to claim 3, wherein each MOS device array include：
At least one active area (100) on a semiconductor substrate；
The grid (200) of at least two equidistant arrangements, on described Semiconductor substrate, perpendicular to
Described active area (100), and connected by grid connecting portion；
Side wall (210), positioned at the both sides of each grid (200)；
The both sides of described active area (100) are drawn by the first and second contact plungers (300,301) respectively
Go out；
First and second metal lines (400,401), connect respectively described first and second contact plungers (300,
301)；
3rd contact plunger (500), described grid connecting portion is drawn；
3rd metal line (600), connects described 3rd contact plunger (500).
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376625A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102945841A (en) * | 2012-11-22 | 2013-02-27 | 上海集成电路研发中心有限公司 | Structure and method for testing effective channel length of metal oxide semiconductor (MOS) transistor |
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| KR100343653B1 (en) * | 2000-09-22 | 2002-07-11 | 윤종용 | Semiconductor device with metal silicide layer and method of manufacturing the same |
| US8896066B2 (en) * | 2011-12-20 | 2014-11-25 | Intel Corporation | Tin doped III-V material contacts |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376625A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102945841A (en) * | 2012-11-22 | 2013-02-27 | 上海集成电路研发中心有限公司 | Structure and method for testing effective channel length of metal oxide semiconductor (MOS) transistor |
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