CN104270585A - CMOS image sensor data read-write control method - Google Patents
CMOS image sensor data read-write control method Download PDFInfo
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- CN104270585A CN104270585A CN201410550715.4A CN201410550715A CN104270585A CN 104270585 A CN104270585 A CN 104270585A CN 201410550715 A CN201410550715 A CN 201410550715A CN 104270585 A CN104270585 A CN 104270585A
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Abstract
A CMOS image sensor data read-write control method includes the steps that a cache device is used for completing odd-even separation of data, only useful data are cached, and not all data need to be cached. The CMOS image sensor data read-write control method has the technical advantages that conversion between line-by-line data and odd-even interlaced data is achieved by adopting a double-SRAM structure, hardware requirements are greatly reduced, and on-chip integration of the cache device can be achieved on a CMOS image sensor.
Description
Technical field
The present invention relates to a kind of cmos image sensor data processing technique, particularly relate to a kind of cmos image sensor data read-write control method.
Background technology
Along with the quickening of security protection and IT technological incorporation paces, current security protection industry is in from simulation-to-digital, process from isolated system to web-based sharing direction that change from, and the equipment such as high-definition camera become the wind vane of security protection industry development.Imageing sensor is as the parts of high-definition camera core the most, mainly contain CCD(Charge Couple Device, charge coupled device) and CMOS(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) two types.
Along with the develop rapidly of cmos image sensor technology and capturing of a correlation technique difficult problem, compared with traditional C CD imageing sensor, cmos image sensor relies on its low cost, low-power consumption, high integration and responds fast advantage, will advantageously under more high-resolution, be more suitable for the big data quantity feature of high-definition monitoring.Therefore, cmos image sensor will have very wide market prospects.
At present, the television system standard of international popular mainly contains NTSC, PAL and SECAM tri-kinds of standards.TSC-system formula is the colourcast standard formulated by National Television System Committee nineteen fifty-two, and the countries such as the Western Hemisphere country such as the U.S., Canada and TaiWan, China, Japan, Korea S, Philippine adopt this standard; Pal mode is the color television standard formulated by West Germany in 1962, some Western European countries such as Germany, Britain, and the country such as Singapore, China's Mainland and Hong Kong, Australia, New Zealand adopts this standard; Sequential Color and Memory system formula is the color television standard formulated by France in 1966, France, and some countries such as Eastern Europe and the Middle East adopt this standard.Three kinds of main flow television system standards all have employed interleaved mode, what interlacing scan adopted is a formatted data, first scan odd field, then even field is scanned, again odd even two field data is merged into a frame, interlaced data frame frequency the is become half of data frame frequency line by line, interlaced data line period has become the twice in data line cycle line by line, and odd even interlacing scan has become the basis of television system display.
Under normal circumstances, in order to realize the compatibility with television system standard, external video process chip be used to by the frame format of sensor devices line by line data be converted to odd even interlaced data, to adapt to PAL, NTSC and SECAM television system exports, Problems existing is: existingly turn interlacing technology line by line, many employings be that chip exterior is based on the method for the complete above data of two frames being carried out to buffer memory, not only occupy a large amount of chip areas, be difficult to carry out on sheet integrated, and the frequent data item read-write operation of a large amount of sram cell makes chip power-consumption also increase thereupon, along with further developing of system integration, realize turning integrated by significant on the microminiaturization of interlacing function and sheet line by line, the integrated of cmos image sensor systemic-function can not only be improved, and compared with traditional solution, less area will be had, lower power consumption and lower cost.
Summary of the invention
For the problem in background technology, the present invention proposes a kind of cmos image sensor data read-write control method, comprise the multiframe data that cmos image sensor exports, wherein, frame data is made up of multiple continuous print data line, its innovation is: involved hardware comprises two SRAM memory, and the memory capacity of single SRAM memory is the data volume that individual data is capable, and two SRAM memory are designated as memory one and memory two respectively; Described read/writing control method comprises:
The multiframe data exported by cmos image sensor by output order are numbered in turn, and the frame data being numbered odd number are designated as strange frame data, and the frame data being numbered even number are designated as even frame data; In frame data, to be numbered in turn by multiple continuous print data line by putting in order, the data line being numbered odd number in strange frame data is designated as strange field data, and the data line being numbered even number in even frame data is designated as even field data; When cmos image sensor exports strange frame data, corresponding time domain is designated as odd field, and when cmos image sensor exports even frame data, corresponding time domain is designated as even field;
When cmos image sensor exports data, under odd field condition, the strange field data being numbered 2n+1 in memory a pair strange frame data carries out read-write operation, and memory two carries out read-write operation to the strange field data being numbered 2n-1 in strange frame data, wherein, n is the odd number from 1;
When cmos image sensor exports data, under even field condition, the even field data being numbered 2m in memory one antithesis frame data carries out read-write operation, and the even field data being numbered 2m-2 in memory two antithesis frame data carries out read-write operation, wherein, m is the even number from 2;
The 1st data behavior the 1st strange field data in 1st frame data, the 2nd data behavior the 1st the even field data in the 2nd frame data; Be numbered the data line being numbered odd number in the data line of even number and even frame data in strange frame data, do not deal with.
Principle of the present invention is: from sensing principle and image-forming principle, the present invention and prior art indifference, and innovation of the present invention is to change the buffer memory means that cmos image sensor exports data, those skilled in the art should be clear, in prior art, when exporting data to cmos image sensor and carrying out buffer memory, usually be all that all buffer memory is out for all data of first being exported by cmos image sensor, and then by late-class circuit, the data after buffer memory are converted to odd even interlaced data, because needs all carry out caching process to all data, in order to ensure the efficiency processed and the odd even feature realizing data, the buffer quantity needed is more, hardware volume is larger, if buffer is carried out on sheet integrated on cmos image sensor, not only technology difficulty is larger, and cmos image sensor size will be caused to increase, therefore generally buffer storage and cmos image sensor are independently arranged in prior art, the core thinking of the present invention program is: in prior art, data are line by line converted to the process of odd even interlaced data by late-class circuit, it is in fact also the process of a data sorting, for continuous print two frame data, when carrying out that data turn the process of odd even interlaced data line by line, the data line being numbered even number in former frame is removed, simultaneously, the data line being numbered odd number in a rear frame is removed, then the frame data completed again are synthesized by being numbered the data line being numbered even number in the data line of odd number and a rear frame in former frame, removed data line is completely useless, in view of this, inventor considers, since these data lines are completely useless, buffer memory can not be carried out completely to it, and only caching process is carried out to the part data needed for follow-up formation odd even interlaced data, so just can reduce required buffer quantity, the physical size of buffer storage is reduced, extremely be beneficial on the sheet of buffer storage on cmos image sensor integrated.For the problem how unwanted data to be removed, under the solution of the present invention thinking, those skilled in the art can adopt multiple implementation, and wherein the comparatively preferred control mode of one is as table tennis read-write operation of the prior art.
In order to realize the synchronous of SRAM memory read-write sequence and corresponding read/write address, preferably, two counters are adopted to be respectively memory one and memory two generates read/write address; When counter generates read/write address, read the half that address pointer translational speed is write address pointer translational speed.
Advantageous Effects of the present invention is: adopt two SRAM structure to realize the conversion of data and odd even interlaced data line by line, greatly reduce hsrdware requirements, makes buffer storage can be integrated on cmos image sensor upper slice.
Accompanying drawing explanation
Fig. 1, data flowchart of the present invention (illustrate only the data flow under odd field condition in figure, the data flow under even field condition is similar with it);
Fig. 2, of the present invention pair of sram cache structure working principle schematic diagram;
Fig. 3, line by line data turn odd even interlaced data principle schematic;
Address synchronization principle schematic that Fig. 4, SRAM read (writing);
Fig. 5, table tennis read-write theory schematic diagram;
The preferred Read-write Catrol sequential chart of Fig. 6, one of the present invention.
Embodiment
A kind of cmos image sensor data read-write control method, comprise the multiframe data that cmos image sensor exports, wherein, frame data is made up of multiple continuous print data line, its innovation is: involved hardware comprises two SRAM memory, the memory capacity of single SRAM memory is the data volume that individual data is capable, and two SRAM memory are designated as memory one and memory two respectively; Described read/writing control method comprises:
The multiframe data exported by cmos image sensor by output order are numbered in turn, and the frame data being numbered odd number are designated as strange frame data, and the frame data being numbered even number are designated as even frame data; In frame data, to be numbered in turn by multiple continuous print data line by putting in order, the data line being numbered odd number in strange frame data is designated as strange field data, and the data line being numbered even number in even frame data is designated as even field data; When cmos image sensor exports strange frame data, corresponding time domain is designated as odd field, and when cmos image sensor exports even frame data, corresponding time domain is designated as even field;
When cmos image sensor exports data, under odd field condition, the strange field data being numbered 2n+1 in memory a pair strange frame data carries out read-write operation, and memory two carries out read-write operation to the strange field data being numbered 2n-1 in strange frame data, wherein, n is the odd number from 1;
When cmos image sensor exports data, under even field condition, the even field data being numbered 2m in memory one antithesis frame data carries out read-write operation, and the even field data being numbered 2m-2 in memory two antithesis frame data carries out read-write operation, wherein, m is the even number from 2;
The 1st data behavior the 1st strange field data in 1st frame data, the 2nd data behavior the 1st the even field data in the 2nd frame data; Be numbered the data line being numbered odd number in the data line of even number and even frame data in strange frame data, do not deal with.
Further, two counters are adopted to be respectively memory one and memory two generates read/write address; When counter generates read/write address, read the half that address pointer translational speed is write address pointer translational speed.
Implement for the ease of those skilled in the art, below in conjunction with accompanying drawing, the present invention be further explained:
See Fig. 1, the frame that cmos image sensor produces line by line data inputs from 001, through parity field conversion 002, data are line by line converted to the interlaced data of parity field, the read/write address of correspondence is synchronized in SRAM by address synchronization 003, realize the addressing to each unit of SRAM, SRAM rattles read-write 004 under parity field read-write sequence and read/write address control, complete and the table tennis read-write cache of above-mentioned parity field interlaced data is operated, interlaced data selects reading 005 the odd even interlaced data in SRAM to be read chronologically, and export in odd even interlaced data the odd even interlaced data that 006 place realizes output and television system compatibility.
See Fig. 2, the data line by line 103 of input are under the control of two SRAM Read-write Catrol sequential 105, complete the judgement of parity field, simultaneously under SRAM reads the condition of (writing) address synchronization 106, odd field or even field according to it, SRAM memory 101 and SRAM memory 102 carry out read-write operation 104 under the control of two SRAM Read-write Catrol sequential 105, because parity field data only extract odd-numbered line in data line by line or even number line, the total read-write operation number of times of read-write operation 104 is n/2 time, then under the control of two SRAM Read-write Catrol sequential 105, required interlaced data 108 is exported.
See Fig. 3, data are imported in two SRAM structured data cache module 202 line by line, transducer SENSOR data generating module 201 produce frame data first frame extract odd-numbered line as first, namely the odd field in PAL/NTSC television system module 203, transducer SENSOR data generating module 201 produce frame data second frame extract even number line as second, i.e. the even field of PAL/NTSC television system module 203.By that analogy, transducer SENSOR data generating module 201 produce frame data the 1st, 3,5,7 frames as the odd field of PAL/NTSC television system module 203, transducer SENSOR data generating module 201 produce frame data the 2nd, 4,6,8 frames are as the even field of PAL/NTSC television system module 203.After conversion, in PAL/NTSC television system module 203, the line period of interlaced data has become 64 microseconds.Achieving line period in the frame in transducer SENSOR data generating module 201 line by line data to PAL/NTSC television system module 203 is 64 microseconds, the conversion of the television system data of parity field interlacing.
See Fig. 4, in order to realize the read-write operation shown in SRAM1 read-write sequence 301 and SRAM2 read-write sequence 302, utilize counter principle, the generation of corresponding read/write address is completed by reading address generator 303 and write address generator 304, wherein, in figure, dash area is the live part of read/write address, the duration of reading address is the twice of write address duration, namely the address pointer translational speed reading address is the half of write address address pointer translational speed, to adapt to the interlaced data line period of television system.Then shown in SRAM1 read/write address synchronous 305 and SRAM2 read/write address synchronous 306, address synchronization is carried out.When SRAM1 carries out read operation, address n will be read and be synchronized to SRAM1, when SRAM1 carries out write operation, write address m+1 will be synchronized to SRAM1; When SRAM2 carries out write operation, write address m is synchronized to SRAM1, when SRAM2 carries out read operation, address n+1 will be read and be synchronized to SRAM2.By that analogy, what complete SRAM read-write sequence reads (writing) address synchronization.
See Fig. 5, odd field SRAM1(SRAM2) read sequential as shown in 401, when data are odd field, SRAM reads sequential: SRAM1 is without operation, and SRAM2 reads the 1st row, and SRAM1 reads the 3rd row, SRAM2 reads the 5th row, SRAM1 reads the 7th row, and by that analogy, memory SRAM1 and SRAM2 alternately reads odd row data; Odd field SRAM1(SRAM2) write sequential as indicated at 402, when data are odd field, SRAM reads sequential and is: SRAM2 writes the 1st row, SRAM1 writes the 3rd row, and SRAM2 writes the 5th row, and SRAM1 writes the 7th row, SRAM2 writes the 9th row, and by that analogy, memory SRAM1 and SRAM2 alternately writes odd row data; Even field SRAM1(SRAM2) read sequential as shown by 403, when data are even field, SRAM reads sequential and is: SRAM1 is without operation, SRAM2 reads the 2nd row, and SRAM1 reads the 4th row, and SRAM2 reads the 6th row, SRAM1 reads eighth row, and by that analogy, memory SRAM1 and SRAM2 alternately reads even number of lines certificate; Even field SRAM1(SRAM2) write sequential as shown at 404, when data are even field, SRAM reads sequential: SRAM2 writes the 2nd row, SRAM1 writes the 4th row, SRAM2 writes the 6th row, and SRAM1 writes eighth row, and SRAM2 writes the 10th row, by that analogy, memory SRAM1 and SRAM2 alternately write even number of lines certificate.
There is high level pulse see Fig. 6, FSYNC frame-synchronizing impulse 501, represent the beginning of frame data, until next high level pulse occurs, represent the end of frame data.Shown in FIELD field system chronizing impulse 502, frame data contain parity field two field data, and namely when FIELD field system chronizing impulse 502 is high level, expression current field is odd field, and when FIELD field system chronizing impulse 502 is low level, expression current field is even field.Shown in FIELD field sequential 503, parity field contains the capable and blank lines of corresponding valid data respectively, parity field interlaced data be only included in valid data capable in.Shown in read-write state signal RW_EN sequential 504, when RW_EN signal value is 2 ' b01, memory SRAM1 does not carry out any operation, and memory SRAM2 carries out the write operation to Current Datarow; When RW_EN signal value is 2 ' b10, memory SRAM1 carries out the write operation to Current Datarow, and memory SRAM2 carries out the read operation to lastrow data; When RW_EN signal value is 2 ' b11, memory SRAM1 carries out the read operation to lastrow data, and memory SRAM2 carries out the write operation to Current Datarow; When RW_EN signal value is other values such as 2 ' b00, memory SRAM1 and memory SRAM2 does not carry out any operation.The sequential of read-write state control signal RW_EN is: the RW_EN value of first read-write cycle is 2 ' b01, the RW_EN value of second read-write cycle is 2 ' b10, the RW_EN value of the 3rd read-write cycle is 2 ' b11, the RW_EN value of the 4th read-write cycle is 2 ' b10, the RW_EN value of the 5th read-write cycle is 2 ' b11, the RW_EN value maintenance 2 ' b11 of last read-write cycle, and cross over the field blanking stage till new one is arrived, then restart the new read-write state Control timing sequence of.Under the control of read-write state signal RW_EN sequential 504, as shown in interlaced data output timing 505, odd even interlaced data exports and is read out.
Claims (2)
1. a cmos image sensor data read-write control method, comprise the multiframe data that cmos image sensor exports, wherein, frame data is made up of multiple continuous print data line, it is characterized in that: involved hardware comprises two SRAM memory, the memory capacity of single SRAM memory is the data volume that individual data is capable, and two SRAM memory are designated as memory one and memory two respectively; Described read/writing control method comprises:
The multiframe data exported by cmos image sensor by output order are numbered in turn, and the frame data being numbered odd number are designated as strange frame data, and the frame data being numbered even number are designated as even frame data; In frame data, to be numbered in turn by multiple continuous print data line by putting in order, the data line being numbered odd number in strange frame data is designated as strange field data, and the data line being numbered even number in even frame data is designated as even field data; When cmos image sensor exports strange frame data, corresponding time domain is designated as odd field, and when cmos image sensor exports even frame data, corresponding time domain is designated as even field;
When cmos image sensor exports data, under odd field condition, the strange field data being numbered 2n+1 in memory a pair strange frame data carries out read-write operation, and memory two carries out read-write operation to the strange field data being numbered 2n-1 in strange frame data, wherein, n is the odd number from 1;
When cmos image sensor exports data, under even field condition, the even field data being numbered 2m in memory one antithesis frame data carries out read-write operation, and the even field data being numbered 2m-2 in memory two antithesis frame data carries out read-write operation, wherein, m is the even number from 2;
The 1st data behavior the 1st strange field data in 1st frame data, the 2nd data behavior the 1st the even field data in the 2nd frame data; Be numbered the data line being numbered odd number in the data line of even number and even frame data in strange frame data, do not deal with.
2. cmos image sensor data read-write control method according to claim 1, is characterized in that: adopt two counters to be respectively memory one and memory two generates read/write address; When counter generates read/write address, read the half that address pointer translational speed is write address pointer translational speed.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307366A (en) * | 2000-01-29 | 2001-08-08 | 全视技术有限公司 | Monolithic colour metal-oxide-semiconductor imaging sensor and adjacent line readout method |
| CN1719890A (en) * | 2005-08-08 | 2006-01-11 | 北京中星微电子有限公司 | Apparatus for implementing video frequency sequential to interlaced conversion and converting method |
| CN1719889A (en) * | 2005-08-08 | 2006-01-11 | 北京中星微电子有限公司 | Apparatus for implementing video frequency sequential to interlaced conversion and converting method |
| CN1878307A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Method for improving SDRAM bus efficiency in video decoder |
| CN101505368A (en) * | 2008-02-07 | 2009-08-12 | 株式会社理光 | Progressive-to-interlace conversion method, image processing apparatus, and imaging apparatus |
| CN101771498A (en) * | 2008-12-30 | 2010-07-07 | 易视芯科技(北京)有限公司 | System and method for expanding bit interleaving memories |
| CN101986693A (en) * | 2010-10-27 | 2011-03-16 | 格科微电子（上海）有限公司 | Image sensor, working method thereof and display device |
-
2014
- 2014-10-17 CN CN201410550715.4A patent/CN104270585A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307366A (en) * | 2000-01-29 | 2001-08-08 | 全视技术有限公司 | Monolithic colour metal-oxide-semiconductor imaging sensor and adjacent line readout method |
| CN1719890A (en) * | 2005-08-08 | 2006-01-11 | 北京中星微电子有限公司 | Apparatus for implementing video frequency sequential to interlaced conversion and converting method |
| CN1719889A (en) * | 2005-08-08 | 2006-01-11 | 北京中星微电子有限公司 | Apparatus for implementing video frequency sequential to interlaced conversion and converting method |
| CN1878307A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Method for improving SDRAM bus efficiency in video decoder |
| CN101505368A (en) * | 2008-02-07 | 2009-08-12 | 株式会社理光 | Progressive-to-interlace conversion method, image processing apparatus, and imaging apparatus |
| CN101771498A (en) * | 2008-12-30 | 2010-07-07 | 易视芯科技(北京)有限公司 | System and method for expanding bit interleaving memories |
| CN101986693A (en) * | 2010-10-27 | 2011-03-16 | 格科微电子（上海）有限公司 | Image sensor, working method thereof and display device |
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