CN102811321A - Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels - Google Patents
Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels Download PDFInfo
- Publication number
- CN102811321A CN102811321A CN2012102410181A CN201210241018A CN102811321A CN 102811321 A CN102811321 A CN 102811321A CN 2012102410181 A CN2012102410181 A CN 2012102410181A CN 201210241018 A CN201210241018 A CN 201210241018A CN 102811321 A CN102811321 A CN 102811321A
- Authority
- CN
- China
- Prior art keywords
- row
- pixel
- accumulator
- voltage
- pel array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a complementary metal oxide semiconductor (CMOS) image sensor. In order to reduce the kTC noise of 3-transmisistor (3T) pixels greatly and achieve a good imaging effect by a time delay integration (TDI)-type CMOS image sensor by combining the own advantages of the 3T pixel, the technical scheme adopted by the invention is that in the CMOS image sensor for the low-noise 3T pixels, a pixel array is provided with N rows of pixels and one row of pseudo-pixels; the one row of pseudo-pixels does not sense light and outputs a constant voltage; in the overall array of N+1 rows of pixels, the pseudo-pixels are positioned in the first row or the N+1 row; all lines of the pixel array are operated at the same time; an accumulator array is provided with N rows of accumulators; the lines of the accumulator array are the same as those of the pixel array; and all lines of the accumulator arrays are also operated at the same time. The CMOS image sensor for the low-noise 3T pixels is mainly used for designing and manufacturing image sensors.
Description
Technical field
The present invention relates to the method for a kind of reduction complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor noise, particularly a kind of reduction time delays integration (TDI) type cmos image sensor noise method.Specifically, relate to low noise 3T pixel cmos image sensor.
Background technology
Imageing sensor can convert the light signal that camera lens obtains to and be easy to the electrical signal storing, transmit and handle.Imageing sensor can be divided into face formation and linear array type according to working method.The operation principle of face formation imageing sensor is to be pel array that two-dimensional array arranges object to be taken obtaining two-dimensional image information, and the operation principle of linear array type imageing sensor is to be pel array that one dimensional linear array arranges through the mode of object scanning shoot is obtained two-dimensional image information.Various fields such as linear array type imageing sensor is widely used in its special working method and takes photo by plane, aerial image, machine vision and imaging of medical.But because object is moving all the time during the pixel exposure of online formation imageing sensor; Therefore the time for exposure of pixel seriously is subject to the translational speed of the relative subject of linear array type imageing sensor; Especially under high-speed motion low-light (level) applied environment the signal to noise ratio of (for example aerial image) linear array type imageing sensor (Signal to Noise Ratio SNR) can become very low.For solving the low problem of SNR; Someone has proposed the time delays integration, and (it can increase the SNR and the sensitivity of line scan image sensor for Time Delay Integration, TDI) technology; It is with its special scan mode; By same target is carried out multiexposure, multiple exposure, realize very high SNR and sensitivity, therefore be specially adapted under the environment of high-speed motion low-light (level).The pel array that the basic principle of TDI is to use the face battle array to arrange is worked with the mode of linear array scanning; And then the pixel that can realize different rows is carried out multiexposure, multiple exposure to the same object in moving; And the result that will at every turn make public adds up; Equivalence has prolonged the exposure time of integration of pixel to object, therefore can significantly promote SNR and sensitivity.
The TDI technology be the earliest through charge coupled device (Charge Coupled Device, CCD) imageing sensor is realized, ccd image sensor also is a desirable device of realizing the TDI technology, it can realize that muting signal adds up.But because there are shortcomings such as the big integrated level of power consumption is low in ccd image sensor; Its application in every field is at present all being substituted by CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) imageing sensor gradually.
Fig. 1 can simply describe the course of work of TDI imageing sensor.The n level TDI imageing sensor one total capable pixel of n, each pixel all can produce corresponding signal in an exposure cycle: for CCD type tdi sensor, what produce in the pixel is charge signal; For CMOS type tdi sensor, what produce in the pixel is voltage signal.The course of work of TDI imageing sensor is following: a certain first directly output of the signal that in first exposure cycle, produces of row pixel that lists, but the signal plus that in second exposure cycle, produces with second pixel of same column.By that analogy, read again after the signal of the pixel of TDI imageing sensor last column (n is capable) generation and a front n-1 signal add up.In the TDI imageing sensor; The amplitude of output signal is adding up of n pixel integration electric charge; Promptly be equivalent to the interior signal that is produced of a pixel n times exposure cycle; Amplitude output signal has enlarged n doubly; And the amplitude of noise has only enlarged
doubly, so signal to noise ratio can improve
doubly.
Use cmos device to realize that the structure of TDI function is suggested, these structures relate generally to numeric field scheme or the analog domain scheme that adds up that adds up.Two samplings (DS) and signal that these two kinds of structures all relate to the reading of signal in the pixel, signal add up.Their difference is whether be converted into digital quantity before signal adds up.
Pixel cell commonly used has 3 pipe active pixels (3T) and 4 pipe active pixels (4T) in the cmos image sensor.The 4T pixel is compared the 3T pixel, has introduced surperficial clamper layer and electric charge and has shifted control valve, can realize correlated-double-sampling (CDS), therefore aspect reduction dark current and the kTC noise greater advantage is being arranged.But the 4T pixel also has some inferior positions of self.Compare the 3T pixel, the fill factor, curve factor of 4T pixel is lower; Photogenerated charge need get into electric charge-voltage conversion node through a transfer pipeline, and the incomplete transfer of electric charge can cause the smearing of final image in this process; Make the 4T pixel, need carefully optimize some technological process and parameter, this process relates to the compatibility issue with the universal CMOS technological process, and longer to the cycle of process optimization and adjustment, can cause the raising of production cost.Therefore, if can the kTC noise level of 3T pixel be reduced, use the 3T pixel to realize that the TDI function has very big using value.
Summary of the invention
The present invention is intended to overcome the deficiency of prior art, significantly reduces the kTC noise of 3T pixel, in conjunction with the advantage of 3T pixel self; Make TDI type cmos image sensor can obtain imaging effect preferably; For achieving the above object, the technical scheme that the present invention takes is low noise 3T pixel cmos image sensor; Pel array has capable pixel of N and 1 row dummy pixel, and 1 row dummy pixel does not carry out sensitization and exports constant voltage; In the capable pel array of whole N+1, dummy pixel be positioned at the 1st the row or N+1 capable; Each row of pel array are operated simultaneously; Accumulator array has the capable accumulator of N, and columns is identical with pel array; Each row of accumulator are also operated simultaneously.
The row of pixel is read order according to N+1, N, N-1, N-2 ... 3,2,1, N+1, N, N-1 ... Order carry out, in readout time, the signal voltage S of this row pixel and resetting voltage R priority is read at each row; < N+1, the resetting voltage R of the capable pixel of K+1 and the signal voltage S of the capable pixel of K carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of K for K; For the capable pixel of N+1, the resetting voltage of the 1st row pixel and the signal voltage of the capable pixel of N+1 carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of N+1;
The order that adds up of two sampled signals is: N+1, N, N-1 ... 2,1, N+1, N, N-1 ... Two sampled signals of row pixel are admitted to the 1st, 2,3 successively ... N, 1,2,3,4 ... In the row accumulator; After accumulator was admitted to two sampled signals of the capable pixel of N+1, this row accumulator was read and is resetted, and prepared the operation that adds up next time; After accumulator was admitted to two sampled signals of the capable pixel of non-N+1, the operation that only adds up of this row accumulator was not read and reset operation.
Pel array is the pel array of 4 row, 128 row, and pel array is made up of 3T type active pixel cell; Accumulator array is made up of 4 row, 128 row simulation accumulators; The capable gate tube that 4 row pixels of same row are all passed through separately links to each other according to bus with columns; In addition; Each bar columns all passes through a row according to bus and selects Guan Yuyi constant voltage to link to each other; This constant voltage is made as 0.8 times of supply voltage of pel array; This voltage can be produced by reference circuit, and through a constant voltage is connected columns according on the bus via the row gate tube, pel array constitutes 5 row, 128 row; Constant voltage of introducing and corresponding row gate tube are delegation's dummy pixel, and the tail that dummy pixel is arranged in pel array is capable.
Technical characterstic of the present invention and effect:
The present invention proposes a kind of method of the 3T of reduction pixel TDI type cmos image sensor noise, and this method has made full use of the working method of TDI, in conjunction with improved sequential and accumulate mode, can significantly reduce the kTC noise of 3T pixel.Method of the present invention makes the 3T pixel have practical value more in the application of TDI type cmos image sensor.
Description of drawings
Fig. 1 TDI type imageing sensor operation principle sketch map.
Fig. 2 tradition 3T pixel TDI type cmos image sensor read the sequential sketch map.
The cumulative process sketch map of Fig. 3 tradition 3T pixel TDI type cmos image sensor.
Fig. 4 realizes the accumulator state that correlated-double-sampling is required.
Fig. 5 introduces pel array and the accumulator array sketch map behind the dummy pixel.
The improved 3T pixel of Fig. 6 TDI type cmos image sensor read the sequential sketch map.
The cumulative process sketch map of the improved 3T pixel of Fig. 7 TDI type cmos image sensor.
Embodiment
TDI type cmos image sensor adopts the mode of drum-type exposure more, and promptly each row signal of pel array is read successively.For the pel array with the capable pixel of N, in the process of the relative subject motion of transducer, the image of object projects the 1st, 2,3 successively ... N-1 is in the capable pixel of N.Optional read order for " 1,2,3 ... N-1, N, 1,2,3 ... " or " N, N-1, N-2 ... 3,2,1, N, N-1, N-2 ... ".For the synchronism that guarantees to add up, read sequential for first kind, need in a transit time, carry out adding up for N+1 time, this mode is called over-sampling; Accordingly, read sequential for second kind, need in a transit time, carry out adding up for N-1 time, be called and owe sampling.The method of the reduction 3T pixel TDI type cmos image sensor that proposes among the present invention adopts second kind of playback mode.
In order to eliminate the stationary phase noise of CMOS CMOS active pixel sensor; Need to realize two samplings; Promptly obtain the resetting voltage of pixel and the signal voltage (being designated hereinafter simply as signal voltage) of integration finish time simultaneously, two voltages are done difference and can significantly be reduced the stationary phase noise.For the 3T pixel, photosensitive area (photodiode) has just begun the accumulation of optical charge after the end that resets, up to the arrival of reset operation next time.Fig. 2 provided each row pixel signal voltage and resetting voltage read sequential.Be example with 4 row pixels among Fig. 2, transverse axis is a time shaft, corresponding respectively the 1st to the 4th row pixel of top-down 4 groups of waveforms, and high level represent read operation, and S and R be respective signal and reading of resetting respectively.The size of numeral represent the sequencing of time shaft, and numeral is more little, represent this operation generation more early.
Pel array of the present invention has capable physical picture element of N and 1 row dummy pixel, and 1 row dummy pixel does not carry out the constant voltage of sensitization and pixel output.In the capable pel array of whole N+1, dummy pixel be positioned at the 1st the row or N+1 capable.Each row of pel array are operated simultaneously.Accumulator array has the capable accumulator of N, and columns is identical with pel array.Each row of accumulator are also operated simultaneously.
The row of pixel of the present invention is read order according to N+1, N, N-1, N-2 ... 3,2,1, N+1, N, N-1 ... Order carry out, in readout time, the signal voltage S of this row pixel and resetting voltage R priority is read at each row.< N+1, the resetting voltage R of the capable pixel of K+1 and the signal voltage S of the capable pixel of K carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of K for K; For the capable pixel of N+1, the resetting voltage of the 1st row pixel and the signal voltage of the capable pixel of N+1 carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of N+1.
The order that adds up of the two sampled signals of the present invention is: N+1, N, N-1 ... 2,1, N+1, N, N-1 ... Two sampled signals of row pixel are admitted to the 1st, 2,3 successively ... N, 1,2,3,4 ... In the row accumulator.After accumulator was admitted to two sampled signals of the capable pixel of N+1, this row accumulator was read and is resetted, and prepared the operation that adds up next time.After accumulator was admitted to two sampled signals of the capable pixel of non-N+1, the operation that only adds up of this row accumulator was not read and reset operation.
The readout time of considering each row pixel is all very short, and common way is: successively gather the signal voltage and the resetting voltage of pixel, utilize these two signals to carry out two sampling operations.Can introduce the kTC noise during owing to reset; And in the above-mentioned double sampling method; The kTC noise that comprises in resetting voltage that collects and the signal voltage is uncorrelated, and therefore this double sampling method can not be eliminated the kTC noise that resets and introduce, and promptly this pair sampling is not a correlated-double-sampling.Specific explanations is following:
The magnitude of voltage of reading after once resetting like R2 representative, in order to embody the noise that reset operation is introduced, i.e. kTC noise, can R2 be represented with following formula:
R2=VR+Vnoise2
Wherein VR is an average of all resetting voltages; Also can think a desired value to resetting voltage; Vnoise is a fluctuation on the VR basis, because the noise that each reset operation is introduced is different, therefore represents the size of the reset noise that contains among the R2 with Vnoise2.
After this resetted, pixel began to carry out integration, promptly accepted illumination and produced photoelectron, and the photoelectron of generation will make the pixel output voltage reduce.Like Fig. 2, if with this row pixel during this period of time in the voltage variety note that causes of illumination be Vlight9, the signal voltage S9 that when integration finishes, obtains so can be expressed as:
S9=VR+Vnoise2-Vlight9
R2-S9=Vlight9
Therefore, if use the difference of R2 and S9 to come the useful signal voltage of represent pixel in the above-mentioned time, then can eliminate the influence of reset noise fully.And if use the method for gathering resetting voltage behind the first acquired signal voltage, use the difference of S9 and R10 to come the useful signal voltage of represent pixel in the above-mentioned time, then can introduce bigger noise.Because R10 is resetting of after having gathered signal S9, having carried out, its noise contribution that contains is different from the noise contribution that S9 contains.
R10=VR+Vnoise10
R10-S9=Vnoise10-Vnoise2+Vlight9
Therefore as stated, for the first row pixel, the noise that can draw down column signal has correlation:
R2 and S9, R10 and S17, R18 and S25, R26 and S33, R34 and S41, R42 and S49, R50 and S57, R58 and S65 or the like.For other row pixels, in like manner can push away to such an extent that have a signal pairing of correlation.
For the satisfied synchronism that adds up, signal S1, S7, S13 and S19 will get into same accumulator, and signal S9, S15, S21 and S27 will get into same accumulator.If it is use the method for gathering resetting voltage behind the first acquired signal voltage, then as shown in Figure 3.Square frame is from left to right represented accumulator respectively 1,2, No. 3, is used to deposit the signal that is added up.Mark in the square frame signal that is added up, added up with difference quilt in accumulator of signal voltage S1 like " R2-S1 " expression resetting voltage R2.After accumulator carried out adding up for 4 times, accumulator was with final accumulation result output, and accumulator empties and prepare the operation that adds up next time then.The box indicating of vertically arranging same accumulator at twice adjacent signal value that empties between the operation to be added up.As: R2-S1, R8-S7, R14-S13 and R20-S19; By being added up, when Adder1 accomplishes after the adding up of this 4 signals, accumulator empties and in the ensuing time, has accomplished R26-S25 in accumulator Adder1; R32-S31, R38-S37 and R44-S43 add up.The order that signal gets into accumulator also marks in Fig. 3, and shown in arrow, the signal after two samplings successively gets into Adder1, Adder2 and Adder3, and then repeat this order.
In order to realize correlated-double-sampling to reduce the kTC noise, two semaphore requests that carry out two samplings have correlation.Signal S9 for example, S15, S21 and S27 will get into same accumulator, and in order to realize correlated-double-sampling, require the matching operation with it of following reset signal, that is: R2-S9, R8-S15, R14-S21, R20-S27 will get into same accumulator.Provided among Fig. 4 and realized the required signal of correlated-double-sampling, and, they have been placed in the corresponding accumulator according to the requirement of the synchronism that adds up.
Above-mentioned signal will add up in accumulator, also will consider actual feasibility.Correlated-double-sampling need be operated two signals of appearance continuous in time, above-mentioned 4 pairs of totally 8 signals, wherein have 3 pairs totally 6 signals can realize appearance continuous in time; They are R8 and S9; R14 and S15, R20 and S21, but R2 and S27 do not have the characteristic of appearance continuous in time.
In order to realize this adding up, the present invention proposes a kind of accumulation method of equivalence, promptly introduce the voltage V0 (as shown in Figure 5) of an approximately constant, and the two sequential of sampling and adding up of adjustment, realized correlated-double-sampling.Promptly introduce two operation: R2-V0 and V0-S27, through adding up, the V0 that just can disappear only is left this useful signal of R2-S27 to these signals in accumulator.It is as shown in Figure 6 to read sequential, and the signal that is deposited in the accumulator is as shown in Figure 7.
As shown in Figure 6, the constant voltage V0 of introducing can be regarded as the delegation's dummy pixel in the pel array, and its output does not change with light intensity.Therefore, for pel array shown in Figure 5, can think that it has 5 row pixels, thinks that promptly its TDI progression is 5.In fact, effective TDI progression of this pel array is 4, and the dummy pixel of introducing can have certain influence to the resolution of pel array, but when the progression of TDI is very big, and it is relatively little many that this influence can become.As: adopt the accumulation method among the present invention, when total TDI progression was 64 grades, effectively TDI progression was 63 grades, and the variation of this resolution of being brought by dummy pixel can be ignored.
As shown in Figure 7.The signal that accumulator adds up at every turn all is to go up adjacent two resetting voltages and signal voltage by the time to subtract each other and obtain, and this mode is very little to the change of readout time.From the pilot process that adds up, each cumulative signal does not obtain through correlated-double-sampling, but the signal that finally obtains in the whole accumulator is to be similar to the kTC noise of offsetting cumulative signal in the middle of each.
Clear for the object of the invention, technical scheme and advantage are more seen, will describe in detail further embodiment of the present invention below.
This instance adopts the pel array of 4 row, 128 row, and pel array is made up of 3T type active pixel cell.Accumulator array is made up of 4 row, 128 row simulation accumulators.The capable gate tube that 4 row pixels of same row are all passed through separately links to each other according to bus with columns.In addition, each bar columns all passes through a row according to bus and selects Guan Yuyi constant voltage continuous, and this instance is made as this constant voltage 0.8 times of supply voltage of pel array, and this voltage can be produced by reference circuit.
Through a constant voltage is connected columns according on the bus via the row gate tube, can regard pel array as 5 row 128 row.Constant voltage of introducing and corresponding row gate tube can be regarded delegation's dummy pixel as, and this instance is capable with the tail that this dummy pixel is arranged in pel array, promptly serve as the 5th row pixel of pel array.Pel array read sequential according to 5 row pixel design, reading of each row adopted 5,4,2,3,1,5,4 ... Order.In the readout time of every row, successively read output signal voltage and resetting voltage.Capable for dummy pixel, think that what read for the first time is signal voltage, the resetting voltage of reading for the second time.Carry out two signals of CDS operation, be respectively from the preceding resetting voltage of once reading with from a back read output signal voltage.Like Fig. 6 and shown in Figure 7, when selecting the 2nd, 1,5,4 row pixels successively, obtain corresponding signal voltage and resetting voltage respectively, they are: S1 and R2, V0 and V0, S3 and R4, S5 and R6.That carries out CDS operation is respectively R2 and V0, V0 and S3, and R4 and S5, their difference has got into accumulator Adder1 respectively as the input signal of accumulator, Adder2 and Adder3.So add up, up to accumulator accomplished add up for 5 times after, accumulator is exported final result, and empties accumulator data, prepares the operation that adds up next time.
Need to prove:
1. the constant voltage in this instance can be set at other numerical value, and its production method also is not limited to utilize reference circuit to produce.
2. the dummy pixel of mentioning in this instance does not influence under the prerequisite of other pixel normal alignment and other control circuit operate as normal, and this dummy pixel can be positioned at any possible position of chip.
3. that mentions in this instance reads sequential, regards dummy pixel as the 5th row pixel and reads, and this instance also can be regarded dummy pixel as the 1st row pixel and read.In fact, for the pel array with the capable actual pixels of N, the dummy pixel of introducing (introduce after the dummy pixel, think that pel array has the capable pixel of N+1) can regard the 1st row as or the capable pixel of N+1 is read.
Claims (3)
1. a low noise 3T pixel cmos image sensor is characterized in that, pel array has capable pixel of N and 1 row dummy pixel, and 1 row dummy pixel does not carry out sensitization and exports constant voltage; In the capable pel array of whole N+1, dummy pixel be positioned at the 1st the row or N+1 capable; Each row of pel array are operated simultaneously; Accumulator array has the capable accumulator of N, and columns is identical with pel array; Each row of accumulator are also operated simultaneously.
2. low noise 3T pixel cmos image sensor as claimed in claim 1; It is characterized in that; The row of pixel is read order according to N+1, N, N-1, N-2 ... 3,2,1, N+1, N, N-1 ... Order carry out; In readout time, the signal voltage S of this row pixel and resetting voltage R are successively read at each row; < N+1, the resetting voltage R of the capable pixel of K+1 and the signal voltage S of the capable pixel of K carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of K for K; For the capable pixel of N+1, the resetting voltage of the 1st row pixel and the signal voltage of the capable pixel of N+1 carry out two sampling operations, and the difference of these two voltages is admitted in the corresponding accumulator as two sampled signals of the capable pixel of N+1;
The order that adds up of two sampled signals is: N+1, N, N-1 ... 2,1, N+1, N, N-1 ... Two sampled signals of row pixel are admitted to the 1st, 2,3 successively ... N, 1,2,3,4 ... In the row accumulator; After accumulator was admitted to two sampled signals of the capable pixel of N+1, this row accumulator was read and is resetted, and prepared the operation that adds up next time; After accumulator was admitted to two sampled signals of the capable pixel of non-N+1, the operation that only adds up of this row accumulator was not read and reset operation.
3. low noise 3T pixel cmos image sensor as claimed in claim 1 is characterized in that, pel array is the pel array of 4 row, 128 row, and pel array is made up of 3T type active pixel cell; Accumulator array is made up of 4 row, 128 row simulation accumulators; The capable gate tube that 4 row pixels of same row are all passed through separately links to each other according to bus with columns; In addition; Each bar columns all passes through a row according to bus and selects Guan Yuyi constant voltage to link to each other; This constant voltage is made as 0.8 times of supply voltage of pel array; This voltage can be produced by reference circuit, and through a constant voltage is connected columns according on the bus via the row gate tube, pel array constitutes 5 row, 128 row; Constant voltage of introducing and corresponding row gate tube are delegation's dummy pixel, and the tail that dummy pixel is arranged in pel array is capable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241018.1A CN102811321B (en) | 2012-07-12 | 2012-07-12 | Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241018.1A CN102811321B (en) | 2012-07-12 | 2012-07-12 | Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102811321A true CN102811321A (en) | 2012-12-05 |
| CN102811321B CN102811321B (en) | 2014-09-24 |
Family
ID=47234888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210241018.1A Expired - Fee Related CN102811321B (en) | 2012-07-12 | 2012-07-12 | Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102811321B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106464820A (en) * | 2014-05-15 | 2017-02-22 | 株式会社福微视 | TDI line image sensor |
| US11212474B2 (en) | 2014-05-15 | 2021-12-28 | Vieworks Co., Ltd. | Bidirectional TDI line image sensor |
| CN113938626A (en) * | 2021-09-30 | 2022-01-14 | 中国科学院长春光学精密机械与物理研究所 | TDI-CMOS detector and compressed sensing imaging method applying same |
| CN115086633A (en) * | 2022-06-16 | 2022-09-20 | 天津商业大学 | Assembly line charge accumulation type pixel suitable for push-broom type three-dimensional image sensor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079830A1 (en) * | 2006-09-28 | 2008-04-03 | Cypress Semiconductor Corporation | Time delayed integration CMOS image sensor with zero desynchronization |
| CN101296330A (en) * | 2007-04-23 | 2008-10-29 | 索尼株式会社 | Solid-state image pickup device, a method of driving the same, a signal processing method for the same |
| US20110205100A1 (en) * | 2009-02-19 | 2011-08-25 | Cmosis Nv | Analog-to-digital conversion in pixel arrays |
| CN102256070A (en) * | 2010-05-17 | 2011-11-23 | 原子能和代替能源委员会 | Image sensor in cmos technology with high video capture rate |
-
2012
- 2012-07-12 CN CN201210241018.1A patent/CN102811321B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079830A1 (en) * | 2006-09-28 | 2008-04-03 | Cypress Semiconductor Corporation | Time delayed integration CMOS image sensor with zero desynchronization |
| CN101296330A (en) * | 2007-04-23 | 2008-10-29 | 索尼株式会社 | Solid-state image pickup device, a method of driving the same, a signal processing method for the same |
| US20110205100A1 (en) * | 2009-02-19 | 2011-08-25 | Cmosis Nv | Analog-to-digital conversion in pixel arrays |
| CN102256070A (en) * | 2010-05-17 | 2011-11-23 | 原子能和代替能源委员会 | Image sensor in cmos technology with high video capture rate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106464820A (en) * | 2014-05-15 | 2017-02-22 | 株式会社福微视 | TDI line image sensor |
| CN106464820B (en) * | 2014-05-15 | 2019-05-03 | 株式会社福微视 | TDI row imaging sensor |
| US11212474B2 (en) | 2014-05-15 | 2021-12-28 | Vieworks Co., Ltd. | Bidirectional TDI line image sensor |
| CN113938626A (en) * | 2021-09-30 | 2022-01-14 | 中国科学院长春光学精密机械与物理研究所 | TDI-CMOS detector and compressed sensing imaging method applying same |
| CN115086633A (en) * | 2022-06-16 | 2022-09-20 | 天津商业大学 | Assembly line charge accumulation type pixel suitable for push-broom type three-dimensional image sensor |
| CN115086633B (en) * | 2022-06-16 | 2023-09-26 | 天津商业大学 | Charge accumulation pixel structure suitable for push-broom three-dimensional image sensor assembly line |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102811321B (en) | 2014-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102801930B (en) | Low-power-consumption time delay integral type CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor | |
| CN103259985B (en) | Cmos image sensor, pixel cell and control method thereof | |
| CN1823532B (en) | Image sensor with charge binning | |
| CN101742132B (en) | Solid state imaging device | |
| US9438839B2 (en) | Solid state imaging apparatus and imaging system using the same | |
| CN101291389B (en) | Data transfer circuit, solid-state imaging device, and camera system | |
| CN106454164B (en) | Charge mixes cumulative type CMOS-TDI imaging sensor with number | |
| CN101919238A (en) | High dynamic range image sensor with reduced line memory for color interpolation | |
| CN102685403B (en) | Method for expanding dynamic range of time-delay integration-complementary metal oxide semiconductor (TDI-CMOS) image sensor | |
| CN104822034A (en) | Solid State Imaging Apparatus And Imaging System | |
| CN102449999A (en) | Imager having global and rolling shutter processes | |
| CN102209209A (en) | Solid-state imaging device and camera system | |
| CN105979173A (en) | Compensation for dual conversion gain high dynamic range sensor | |
| CN104272719B (en) | Solid camera head | |
| CN102811321B (en) | Complementary metal oxide semiconductor (CMOS) image sensor for low-noise 3-transistor (3T) pixels | |
| CN101771801A (en) | Solid-state imaging device and driving control method | |
| CN103312992B (en) | Signal transmission system, photoelectric conversion device and image picking system | |
| JP5263239B2 (en) | Solid-state imaging device and imaging apparatus | |
| CN109040632A (en) | Readout circuit and sensing device | |
| CN106464820A (en) | TDI line image sensor | |
| CN103312999B (en) | Imaging device | |
| CN102740007B (en) | active image sensing circuit and sensing method thereof | |
| CN107231534A (en) | Pixel output level control device and use its cmos image sensor | |
| CN105516625A (en) | Pixel merging read-out circuit structure for CMOS (Complementary Metal Oxide Semiconductor) image sensor and signal processing read-out method | |
| CN106686324B (en) | Pixel structure, cmos image sensor and its imaging method of cmos image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140924 Termination date: 20210712 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |