CN104269364B - A kind of method for detecting ion trap injection pattern and being influenced on device performance - Google Patents
A kind of method for detecting ion trap injection pattern and being influenced on device performance Download PDFInfo
- Publication number
- CN104269364B CN104269364B CN201410441471.6A CN201410441471A CN104269364B CN 104269364 B CN104269364 B CN 104269364B CN 201410441471 A CN201410441471 A CN 201410441471A CN 104269364 B CN104269364 B CN 104269364B
- Authority
- CN
- China
- Prior art keywords
- ion trap
- type ion
- type
- device performance
- spacing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention relates to IC manufacturing fields, a kind of more particularly to method for detecting ion trap injection pattern and being influenced on device performance, by the semi-conductive substrate for providing a removal oxidization isolation layer, and observe the bright dark degree to form the metal contact hole on NMOS transistor and each source electrode of PMOS transistor, drain electrode, the brightness anomalous variation of metal contact hole occurs by further analyzing to judge the spacing of following P ion trap and N ion traps, influence when can analyze the generation ion trap pattern offset of different ions trap spacing to device performance.
Description
Technical field
The present invention relates to IC manufacturing fields more particularly to a kind of detection ion trap to inject pattern to device performance
The method of influence.
Background technology
In existing technical field, the basis of information technology is all unfolded around a field-effect transistor, and with
Constantly advancing for information technology, the increasingly maturation of integrated circuit technology performance.
The process that circuit manufacturing process on existing chip all includes hundreds of steps is broadly divided into photoetching, etching, cleaning, thin
Several big module processes such as film growth and ion implanting, therefore with the development of integrated circuit technology and the continuous contracting of characteristic size
Small, the distribution of on-chip circuitry also becomes increasingly complex, and under such high density distribution situation, specifically works as IC manufacturing
Influencing each other between transistor also can be increasing when technique occurs abnormal, finally influences whether the yield of product.Such as Fig. 1 institutes
Show, when device size constantly reduces, the spacing of two transistors mutually placed becomes close on chip, leads to N-type and P ion
The distance between trap also becomes less and less, so once being injected not into the silicon materials corresponding to it using ion implantation technology
It changes with the pattern that occurs abnormal variation during the ion of type and dosage and may result in ion trap, so as to make variety classes
The counterdiffusion of ion phase and eventually lead to the performance failure of chip.However the pattern of ion trap appearance exception is in production technology
Compare and be difficult to what is found, need just reflect in final electrical testing, therefore once appearance exception may be often
The production of device causes high risk hidden danger.
The invention belongs to silicon substrate photoreceiver technical fields for Chinese patent (CN102593132A), are related to a kind of based on standard
CMOS technology lamination difference double-photoelectric detector, including：MSM types photodetector, the double photodiode type being in vertical distribution
Photodetector and positioned at separation layer between the two, wherein, double photodiode type photodetector is produced on silicon substrate
On PSUB, using P+/N traps knot as work diode, N traps/Psub knots are as shielding diode, positioned at lower section, cathode P+
It distributes alternately with anode N+, the cathode P+ quantity between each two anode N+ is 3~4；MSM(metal-semiconductor-
Metal, metal semiconductor metal) type photodetector is produced on low-doped polysilicon (poly).Photoelectricity provided by the invention
Detector can be obtained the mutually isolated photo-signal of two-way by input optical signal all the way；Improve light injection efficiency；Make to be based on
The photoreceiver of standard CMOS process obtains enough responsivenesses in the case where ensureing bandwidth and frequency characteristic.
The light injection efficiency of the photodetector is improved by the method for the patent, by measuring P ion trap and N ions
The mutually isolated photo-signal of trap monitors the normal operating conditions of two traps, monitors whether two traps occur pattern exception at any time, together
Reason, which is applied in transistor, can also measure whether P ion trap abnormal working condition occurs with N ion traps, but operate
It is more complicated, it is higher while also abnormal good to device with the appearance of N ion traps pattern without determining P ion trap to obtain information costs
The influence of rate.
Invention content
In view of the above problems, the present invention provides a kind of method for detecting ion trap injection pattern and being influenced on device performance.It is logical
Crossing this method can measure whether P ion trap abnormal working condition occurs with N ion traps and solution operational means is more multiple
Miscellaneous, acquisition information costs are higher, while also without determining that the abnormal shadow to yield of devices occur in P ion trap and N ion traps pattern
The defects of ringing.
Technical solution is used by the present invention solves above-mentioned technical problem：
A kind of method for detecting ion trap injection pattern and being influenced on device performance, wherein, the side
Method includes：
Step S1, distinguish doped p-type ion and N-type ion in a substrate, form multiple and different ion trap groups, it is described each
Ion trap group includes adjacent a p-type ion trap and a N-type ion trap, and p-type ion trap and N-type in any ion trap group
Spacing between ion trap is different from the spacing of N-type ion trap compared with the p-type ion trap in other remaining ions trap groups；
Step S2, in making a NMOS transistor in the p-type ion trap, in making a PMOS in the N-type ion trap
Transistor；
Step S3, the metal in source electrode that the NMOS transistor and PMOS transistor respectively include, drain electrode is formed
Contact hole；
Step S4, observe in each ion trap group the source electrode of the p-type ion trap of neighbouring PMOS transistor or drain electrode with it is neighbouring
The bright dark variation of the source electrode or the metal contact hole in drain electrode of the N-type ion trap of NMOS transistor；
Wherein, by observing the bright dark variation of the metal contact hole, the pattern of p-type ion trap or N-type ion trap is detected
Change the P not adversely affected to device performance, the minimum safe spacing of N-type ion trap.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, the P ion trap and the N
The equal proportion amplification on the basis of manufacturing process intermediate ion trap spacing minimum range of spacing between ion trap forms the ion trap group.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, the magnification ratio is positive and negative
50%.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, in step S1, noted using ion
Enter method and variety classes and the p-type ion of various dose and N-type ion are injected separately into the substrate.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, in step S1, noted using ion
Enter method and variety classes or the p-type ion of various dose and N-type ion are injected separately into the substrate.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, it is seen by an electron microscope
Examine the bright dark variation of the source electrode, metal contact hole in drain electrode.
The method that above-mentioned detection ion trap injection pattern influences device performance, wherein, if a wherein ion trap group
The bright of metal contact hole does not change secretly, and the metal contact hole of ion trap group adjacent thereto it is bright it is dark change, then
The distance between bright dark p-type ion trap and N-type ion trap not occurred included by the ion trap group changed of metal contact hole is i.e.
Minimum safe spacing for ion trap diffusion.
Above-mentioned technical proposal has the following advantages that or advantageous effect：
A kind of method for detecting ion trap injection pattern and being influenced on device performance disclosed by the invention, passes through one removal of design
The Semiconductor substrate of oxidization isolation layer, and observe the metal to be formed in the source of NMOS transistor and PMOS transistor, drain electrode
The bright dark degree of contact hole judges the offset of ion trap to the negative effect of device performance and detects not cause the negative effect
Two traps between minimum spacing.And by further analyzing the P below the brightness anomalous variation that metal contact hole occurs
The spacing of ion trap and N ion traps can analyze different ions trap spacing and occur when ion trap pattern deviates to device performance
Influence.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is transistor cross-sectional view of the prior art；
Fig. 2 is transistor cross-sectional view in the embodiment of the present invention；
Fig. 3 is intermediate ion trap group schematic diagram of the embodiment of the present invention；
Fig. 4 is that the metal contact hole in the embodiment of the present invention in normal ion trap group is in bright dark feature schematic diagram；
Fig. 5 is the transistor cross-sectional view of intermediate ion trap of embodiment of the present invention pattern offset；
Fig. 6 is the schematic diagram of the metal contact hole brightness exception in intermediate ion trap group of the embodiment of the present invention.
Specific embodiment
A kind of method for detecting ion trap injection pattern and being influenced on device performance, including：Doped p-type is distinguished in a substrate
Ion and N-type ion, form multiple ion trap groups, and each ion trap group includes adjacent a p-type ion trap and a N-type ion
Trap, and the spacing between p-type ion trap in any ion trap group and N-type ion trap is compared with the p-type in other remaining ions trap groups
Ion trap is different from the spacing of N-type ion trap；In making a NMOS transistor in p-type ion trap, in making one in N-type ion trap
PMOS transistor；Form the metal contact hole being located on the NMOS transistor and each source electrode of PMOS transistor, drain electrode；Observation is each
The source electrode of the p-type ion trap of neighbouring PMOS transistor or drain electrode and the N-type ion trap of neighbouring NMOS transistor in ion trap group
The bright dark variation of source electrode or the metal contact hole in drain electrode.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
Specifically as shown in figs. 1 to 6, doped p-type ion and N-type ion first in semi-conductive substrate, form several
The ion trap group of quantity.As shown in Fig. 2, include adjacent a p-type ion trap 1 and a N-type ion trap 2 in any ion trap group
(the p-type ion trap 1 and N-type ion trap 2 are a part for the substrate, and STI (Shallow Trench are not filled by between two traps
Isolation, shallow trench isolation) structure 7).
In a kind of optional but non-limiting embodiment, a number of ion trap group is formed in Semiconductor substrate, such as
Fig. 3, and using them as multiple monitoring groups or test group (a1、a2...an-m...an), wherein n is more than m and is that non-zero is natural
Number, and test group (a1、a2...an-m...an) in p-type ion trap 1 and the spacing of N-type ion trap 2 it is different.It is several at this
In the test group of quantity, the test group of pre-set minimum range size is assumed to be an-m(the p-type ion trap in the test group
Pn-mWith N-type ion trap Nn-mSpacing the minimum range size of intermediate ion trap is manufactured for technique), and the root on the basis of the test group
Positive and negative X% according to P, N-type ion trap spacing dimension amplifies successively, and the spacing formed between p-type ion trap 1 and N-type ion trap 2 is distinguished
For (b1、b2...bn-m...bn) above-mentioned test group (a1、a2...an-m...an)。
Such as it embodies as follows：With in p-type ion trap 1 and the test group of the positive and negative equal proportion amplification of 2 spacing dimension of N-type ion trap
an-mWith previous test group an-m-1In Pn-m-1、Nn-m-1The spacing of trap additionally reduces X% i.e. bn-m(1-X%) is surveyed with the latter
Examination group an-m+1In Pn-m+1、Nn-m+1The spacing of trap additionally increases X% i.e. bn-m (1+X%).A kind of optional but unrestricted
In embodiment, the n-th-m test group an-mWith previous test group an-m-1In p-type ion trap 1 and N-type ion trap 2 spacing volume
Outer reduction X% (X=50), with the latter test group an-m+1In p-type ion trap 1 and the spacing of N-type ion trap 2 additionally increase
X% (X=50) and so on, forms structure as shown in Figure 3.
In an embodiment of the present invention, preferably using ion implantation injected in the Semiconductor substrate variety classes with
The ion of various dose forms test group (a1、a2...an-m...an), as shown in Figure 3：The implantation concentration into the Semiconductor substrate
Phosphorus and boron ion for j form phosphorus N-type ion trap and boron p-type ion trap or implantation concentration is k's into the Semiconductor substrate
Arsenic and boronation fluorine ion form arsenic N-type ion trap and boronation fluorine p-type ion trap.The specific concentration of wherein above-mentioned ion and type root
It is set according to the demand of production technology, is not merely fixed on certain certain value, as long as the object of the invention can be reached.
Then, making devices such as NMOS transistor in the p-type ion trap 1 in above-mentioned Fig. 2, and in N-type ion trap 2
The device of making such as PMOS transistor；It is formed simultaneously each 4 both sides of grid, source in the NMOS transistor and PMOS transistor
Metal contact hole 3 on pole 5 and drain electrode 6.
Further, it is brilliant that the drain electrode 6 of the p-type ion trap 1 of neighbouring PMOS transistor and neighbouring NMOS in each test group are observed
The bright dark variation of metal contact hole 3 on the source electrode 5 of the N-type ion trap 2 of body pipe.
As shown in figure 4, normal test group (a1、a2...an-m...an) in p-type ion trap (P1、P2...Pn-m...Pn)
Corresponding metal contact hole 3 is in light tone, N-type ion trap (N1、N2...Nn-m...Nn) corresponding metal contact hole 3 is in dead color, root
According to this principle, in an embodiment of the present invention, by observing the bright dark variation of metal contact hole 3, detection p-type ion trap 1 or N
P that the pattern variation of type ion trap 2 does not adversely affect device performance, the minimum spacing of N-type ion trap.
The test group (a in a kind of optional but non-limiting embodiment1、a2...an-m...anIf) in using ion
The offset of test group intermediate ion trap pattern occurs in this step of injection technology, for example, certain for closing on NMOS transistor as shown in Figure 5
One N-type ion trap pattern shifts (extra N-type ion trap offset object 8).
Further, pass through the electron microscope observation test group (a1、a2...an-m...an) in p-type ion trap 1 and N
The bright dark variation of metal contact hole 3 on 2 corresponding source electrode 5 of type ion trap, drain electrode 6, in an embodiment of the present invention, grid
4 pairs of p-type ion traps 1 or 2 source electrode 5 of N-type ion trap have blanketing effect with drain electrode 6：I.e. using ion implantation in p-type from
When sub- trap 1 and N-type ion trap 2 carry out above-mentioned ion implanting, due to test group (a1、a2...an-m...an) in grid 4 every
The area of ion trap from after is gradually reduced (i.e. A in Fig. 61-AnIn the area of ion trap be gradually reduced or spacing (b1、
b2...bn-m...bn) become larger)), since the dosage of its entire ion implanting is larger, P, N-type ion trap spacing compared with
Hour is more easy to observe the offset of ion trap pattern and the influence to device performance.
Preferably, the spacing (b between p-type ion trap 1 and N-type ion trap 21、b2...bn-m...bn) become larger
The bright dark variation of the corresponding metal contact hole 3 of direction observation, if for example, as shown in fig. 6, test group (a1、a2...an-m) in
Only there is abnormal i.e. neighbouring NMOS in the bright dark variation of the metal contact hole 3 in the drain electrode of p-type ion trap 16 of neighbouring PMOS transistor
Metal contact hole 3 on the source electrode 5 of the N-type ion trap 2 of transistor in dead color, but with the p-type of neighbouring PMOS transistor from
Metal contact hole 3 in the drain electrode 6 of sub- trap 1 becomes dark-coloured by light tone, illustrates the test group (a1、a2...an-m) in p-type ion trap
Spacing (b between 1 and N-type ion trap 21、b2...bn-m) born caused by the performance of device under ion trap pattern drift condition
The influence in face；If at the same time test group (an-m+1...an) in neighbouring PMOS transistor p-type ion trap 1 drain electrode 6 on
The bright dark variation of metal contact hole 3 does not occur the metal on the source electrode 5 of the N-type ion trap 2 of abnormal i.e. neighbouring NMOS transistor
For contact hole 3 in dead color, the metal contact hole 3 in drain electrode 6 with the p-type ion trap 1 of neighbouring PMOS transistor illustrates this in light tone
Test group (an-m+1...an) in spacing (b between p-type ion trap 1 and N-type ion trap 2n-m+1...bn) inclined in ion trap pattern
In the case of shifting negative impact is not caused to the performance of device.Therefore the pattern variation of detection p-type ion trap 1 or N-type ion trap 2
The P that is not adversely affected to device performance, the minimum spacing of N-type ion trap are bn-m+1, equally on the other hand no matter
How much is ion trap pattern offset, as long as ensureing that p-type ion trap 1 and the spacing of N-type ion trap 2 are at least bn-m+1.
Pass through the technology of the present invention, under detection ion implanting conditions that can be online, p-type ion trap 1 and N-type ion trap 2
Influence of the pattern variation to transistor device performance occurs, and the brightness of metal contact hole 3 occurs by further analyzing
P ion trap 1 and the spacing of N ion traps 2 below anomalous variation, can analyze different ions trap spacing and ion trap pattern occurs
To the influence of device performance during offset.
In conclusion a kind of method for detecting ion trap injection pattern and being influenced on device performance disclosed by the invention, passes through
Design one removal oxidization isolation layer semi-conductive substrate, and observe to be formed positioned at the source of NMOS transistor and PMOS transistor,
The bright dark degree of metal contact hole in drain electrode judges the offset of ion trap to the negative effect of device performance and detects not make
Minimum spacing between two traps of the negative effect.And the brightness that metal contact hole occurs by further analyzing is abnormal
Change the spacing of following P ion trap and N ion traps, when can analyze the generation ion trap pattern offset of different ions trap spacing
Influence to device performance.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications of true intention and range for covering the present invention as.It is weighing
The range and content of any and all equivalence, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (6)
- A kind of 1. method for detecting ion trap injection pattern and being influenced on device performance, which is characterized in that the method includes：Step S1, distinguish doped p-type ion and N-type ion in a substrate, form multiple ion trap groups, each ion trap group is equal Including adjacent a p-type ion trap and a N-type ion trap, and between p-type ion trap in any ion trap group and N-type ion trap Spacing it is different from the spacing of N-type ion trap compared with the p-type ion trap in other remaining ions trap groups；Step S2, in making a NMOS transistor in the p-type ion trap, in making a PMOS crystal in the N-type ion trap Pipe；Step S3, the metal formed in source electrode that the NMOS transistor and PMOS transistor respectively include, drain electrode contacts Hole；Step S4, it is brilliant that the source electrode of the p-type ion trap of neighbouring PMOS transistor or drain electrode and neighbouring NMOS in each ion trap group are observed The bright dark variation of the source electrode or the metal contact hole in drain electrode of the N-type ion trap of body pipe；Wherein, by observing the bright dark variation of the metal contact hole, the pattern variation of p-type ion trap or N-type ion trap is detected The P that is not adversely affected to device performance, the minimum safe spacing of N-type ion trap；If wherein the bright of the metal contact hole of an ion trap group does not change secretly, and the metal of ion trap group adjacent thereto connects Contact hole it is bright it is dark change, then the bright dark p-type ion trap and N not occurred included by the ion trap group changed of metal contact hole The distance between type ion trap is the minimum safe spacing of ion trap diffusion.
- 2. the method that detection ion trap injection pattern influences device performance as described in claim 1, which is characterized in that described Spacing between p-type ion trap and the N-type ion trap equal proportion on the basis of manufacturing process intermediate ion trap spacing minimum range is put The ion trap group is formed greatly.
- 3. the method that detection ion trap injection pattern influences device performance as claimed in claim 2, which is characterized in that described Magnification ratio is positive and negative 50%.
- 4. the method that detection ion trap injection pattern influences device performance as described in claim 1, which is characterized in that step In S1, variety classes and the p-type ion of various dose and N-type ion are injected separately into the substrate using ion implantation.
- 5. the method that detection ion trap injection pattern influences device performance as described in claim 1, which is characterized in that step In S1, variety classes or the p-type ion of various dose and N-type ion are injected separately into the substrate using ion implantation.
- 6. the method that detection ion trap injection pattern influences device performance as described in claim 1, which is characterized in that pass through The bright dark variation of source electrode described in one electron microscope observation, the metal contact hole in drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410441471.6A CN104269364B (en) | 2014-09-01 | 2014-09-01 | A kind of method for detecting ion trap injection pattern and being influenced on device performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410441471.6A CN104269364B (en) | 2014-09-01 | 2014-09-01 | A kind of method for detecting ion trap injection pattern and being influenced on device performance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104269364A CN104269364A (en) | 2015-01-07 |
| CN104269364B true CN104269364B (en) | 2018-06-22 |
Family
ID=52160875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410441471.6A Active CN104269364B (en) | 2014-09-01 | 2014-09-01 | A kind of method for detecting ion trap injection pattern and being influenced on device performance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104269364B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577149B2 (en) * | 2001-01-05 | 2003-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for addressable failure site test structure |
| CN102142383A (en) * | 2010-02-03 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN102768968A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for detecting diffusivity of wellblock implantation ions in different concentrations |
| CN102915939A (en) * | 2012-10-08 | 2013-02-06 | 上海华力微电子有限公司 | Method for detecting migration distance of carriers in ion well under optical radiation |
| CN103247550A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | Test module and method for monitoring processing procedure stability |
-
2014
- 2014-09-01 CN CN201410441471.6A patent/CN104269364B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577149B2 (en) * | 2001-01-05 | 2003-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for addressable failure site test structure |
| CN102142383A (en) * | 2010-02-03 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN102768968A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for detecting diffusivity of wellblock implantation ions in different concentrations |
| CN102915939A (en) * | 2012-10-08 | 2013-02-06 | 上海华力微电子有限公司 | Method for detecting migration distance of carriers in ion well under optical radiation |
| CN103247550A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | Test module and method for monitoring processing procedure stability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104269364A (en) | 2015-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102944196B (en) | A kind of method detecting circularity of circular contact hole of semiconductor | |
| US7939348B2 (en) | E-beam inspection structure for leakage analysis | |
| CN104733343B (en) | Grid oxide layer defect inspection method and element leakage detection method | |
| CN107566764A (en) | The photoelectric door and its manufacture method of preceding illuminated infrared image sensor | |
| CN104377143B (en) | A kind of method of test MOS device trap resistance | |
| JP5751531B2 (en) | Semiconductor substrate evaluation method, semiconductor substrate for evaluation, semiconductor device | |
| CN104269364B (en) | A kind of method for detecting ion trap injection pattern and being influenced on device performance | |
| CN107316823A (en) | A kind of detection method of ion implanting layer pattern register partial difference | |
| CN103645197B (en) | The detection method of chip defect | |
| Marcelot et al. | Exploration of pinned photodiode radiation hardening solutions through TCAD simulations | |
| CN103943527B (en) | The method using Test Constructure of detection etching polysilicon gate defect | |
| US9935021B2 (en) | Method for evaluating a semiconductor wafer | |
| CN104201128B (en) | A kind of method that test pattern size influences on ion trap pattern | |
| TWI472782B (en) | Semiconctor device inspecting method and semiconctor device inspecting method system | |
| KR0161736B1 (en) | Measuring method of leakage current | |
| JP5652379B2 (en) | Semiconductor substrate evaluation method and semiconductor substrate for evaluation | |
| Gaucher et al. | Characterization of plasma etching process damage in HgCdTe | |
| US9976981B2 (en) | Device for detecting chemical/physical phenomenon having a diffusion layer formed between an input charge control region and a sensing region on a substrate | |
| CN107293503B (en) | Test structure, preparation method and the test method of shared contact hole circuit defect | |
| CN107507786A (en) | Contact hole tack coat exception defect inspection method on a kind of polysilicon | |
| CN103904000A (en) | Method for testing polycrystalline silicon bottom bridging defect through capacitor contrast test structure | |
| CN108172526A (en) | A kind of detection method for detecting polysilicon and short circuit whether occur | |
| CN103887195B (en) | Use the method that ion punctures the detection not enough defect of polysilicon bottom etching | |
| KR100705215B1 (en) | Image sensor with Test pattern and the method for Test | |
| CN103887196B (en) | The method using wicket graphics test structure detection polysilicon bottom bridging defect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |