CN104269364A - Method for detecting influences of ion trap injection form on device performance - Google Patents
Method for detecting influences of ion trap injection form on device performance Download PDFInfo
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- CN104269364A CN104269364A CN201410441471.6A CN201410441471A CN104269364A CN 104269364 A CN104269364 A CN 104269364A CN 201410441471 A CN201410441471 A CN 201410441471A CN 104269364 A CN104269364 A CN 104269364A
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- ion trap
- type ion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention relates to the field of integrated circuit manufacture, in particular to a method for detecting the influences of ion trap injection form on device performance. The method includes the steps that a semiconductor substrate with an oxide isolation layer removed is provided, the brightness degrees of metal contact holes formed in the source electrodes and the drain electrodes of NMOS transistors and PMOS transistors are observed, the interval between a P ion trap and an N ion trap below the metal contact holes is judged by further analyzing the abnormal brightness change of the metal contact holes, and the influences of ion trap form excursion of different ion trap intervals on the device performance can be analyzed.
Description
Technical field
The present invention relates to IC manufacturing field, refer more particularly to a kind of method detecting ion trap injection pattern and device performance is affected.
Background technology
In existing technical field, the basis of information technology is all launched round a field-effect transistor, and constantly advancing along with information technology, the more and more maturation of integrated circuit technology performance.
Circuit manufacturing process on existing chip all comprises the operation of hundreds of step, mainly be divided into several large module processes such as photoetching, etching, cleaning, film growth and ion implantation, therefore along with the development of integrated circuit technology and constantly reducing of characteristic size, the distribution of on-chip circuitry also becomes increasingly complex, under high density distribution situation like this, influencing each other specifically when integrated circuit fabrication process occurs abnormal between transistor also can be increasing, finally can have influence on the yield of product.As shown in Figure 1, when device size constantly reduces, on chip, the spacing of the transistor that two are placed mutually becomes very near, the distance between N-type and P ion trap is caused also to become more and more less, so occur that abnormal variation may cause the pattern of ion trap to change once the ion adopting ion implantation technology to inject variety classes and dosage in the silicon materials corresponding to it, thus make different types of Ion Phase counterdiffusion and finally cause the performance failure of chip.But the pattern of ion trap occurs that abnormal comparison in production technology is difficult to find, needs just can reflect in final testing electrical property, therefore once occur extremely the production of often device to cause high risk hidden danger.
Chinese patent (CN102593132A) the invention belongs to silica-based optical receiver technical field, relate to a kind of based on standard CMOS process lamination difference double-photoelectric detector, comprise: the MSM type photodetector be in vertical distribution, double photodiode type photodetector and the separator be positioned between the two, wherein, double photodiode type photodetector is produced on silicon substrate PSUB, use P+/N trap knot as work diode, N trap/Psub knot is as shielding diode, be positioned at below, its negative electrode P+ and anode N+ distributes alternately, negative electrode P+ quantity between every two anode N+ is 3 ~ 4, MSM (metal-semiconductor-metal, metal semiconductor metal) type photodetector is produced on low-doped polysilicon (poly).Photodetector provided by the invention, can obtain the mutually isolated photo-signal of two-way by a road input optical signal; Improve light injection efficiency; The optical receiver based on standard CMOS process is made to obtain enough responsivenesses when ensureing bandwidth sum frequency characteristic.
The light injection efficiency of this photodetector is improve by the method for this patent, by measuring P ion trap and the mutually isolated photo-signal of N ion trap, monitor the normal operating conditions of two traps, monitor two traps at any time and whether pattern occurs extremely, in like manner be applied to can also to measure P ion trap in transistor and whether N ion trap occurs abnormal operating state, but operation more complicated, obtaining information cost is higher, does not also determine that the abnormal impact on yield of devices appears in P ion trap and N ion trap pattern simultaneously.
Summary of the invention
In view of the above problems, the invention provides a kind of method detecting ion trap injection pattern and device performance is affected.P ion trap can be measured and whether N ion trap occurs abnormal operating state by the method, and solve operational means more complicated, obtaining information cost is higher, does not also determine that the abnormal defect on the impact of yield of devices appears in P ion trap and N ion trap pattern simultaneously.
The present invention solves the problems of the technologies described above adopted technical scheme:
Detect the method that ion trap injection pattern affects device performance, wherein, described side
Method comprises:
Step S1, in a substrate respectively doped p-type ion and N-type ion, form multiple different ion trap group, described each ion trap group includes an adjacent P type ion trap and a N-type ion trap, and P type ion trap in arbitrary ion trap group is different compared with the spacing of the P type ion trap in other remaining ions trap groups and N-type ion trap from the spacing between N-type ion trap;
Step S2, in described P type ion trap, make a nmos pass transistor, in described N-type ion trap, make a PMOS transistor;
Step S3, form the source electrode, the metal contact hole in drain electrode that are positioned at described nmos pass transistor and PMOS transistor and comprise separately;
The bright dark change of step S4, the source electrode observing in each ion trap group the P type ion trap of contiguous PMOS transistor or drain electrode and the source electrode of N-type ion trap or the metal contact hole on draining that are close to nmos pass transistor;
Wherein, by observing the bright dark change of described metal contact hole, the pattern change detecting P type ion trap or N-type ion trap does not cause the P of negative effect, the minimum safe spacing of N-type ion trap to device performance.
Above-mentioned detection ion trap injects the method that pattern affects device performance, and wherein, the spacing between described P ion trap and described N ion trap to be amplified for benchmark equal proportion with manufacturing process intermediate ion trap spacing minimum range and formed described ion trap group.
Above-mentioned detection ion trap injects the method that pattern affects device performance, and wherein, described magnification ratio is positive and negative 50%.
Above-mentioned detection ion trap injects the method that pattern affects device performance, wherein, in step S1, adopts ion implantation in described substrate, inject P type ion and the N-type ion of variety classes and various dose respectively.
Above-mentioned detection ion trap injects the method that pattern affects device performance, wherein, in step S1, adopts ion implantation in described substrate, inject P type ion and the N-type ion of variety classes or various dose respectively.
Above-mentioned detection ion trap injects the method that pattern affects device performance, wherein, by the bright dark change of the metal contact hole in source electrode, drain electrode described in an electron microscope observation.
Above-mentioned detection ion trap injects the method that pattern affects device performance, wherein, if wherein secretly there is not change in the bright of metal contact hole of an ion trap group, and the bright dark appearance change of the metal contact hole of the ion trap group be adjacent, then secretly there is not the minimum safe spacing that the P type ion trap included by ion trap group of change and the distance between N-type ion trap are ion trap diffusion in the bright of metal contact hole.
Technique scheme tool has the following advantages or beneficial effect:
A kind of method detecting ion trap injection pattern and device performance is affected disclosed by the invention, by designing the Semiconductor substrate of a removal oxidization isolation layer, and observe the bright dark degree forming the metal contact hole be positioned in the source of nmos pass transistor and PMOS transistor, drain electrode, judge that the skew of ion trap detects the minimum spacing between two traps not causing this negative effect to the negative effect of device performance.And the spacing of the P ion trap passed through below the further brightness ANOMALOUS VARIATIONS analyzing generation metal contact hole and N ion trap, the impact on device performance when different ions trap spacing generation ion trap pattern offsets can be analyzed.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is transistor cross-sectional view of the prior art;
Fig. 2 is transistor cross-sectional view in the embodiment of the present invention;
Fig. 3 is embodiment of the present invention intermediate ion trap group schematic diagram;
Fig. 4 is the metal contact hole in the embodiment of the present invention in normal ion trap group is bright dark feature schematic diagram;
Fig. 5 is the transistor cross-sectional view of embodiment of the present invention intermediate ion trap pattern skew;
Fig. 6 is the schematic diagram of the metal contact hole brightness exception in embodiment of the present invention intermediate ion trap group.
Embodiment
A kind of method detecting ion trap injection pattern and device performance is affected, comprise: difference doped p-type ion and N-type ion in a substrate, form multiple ion trap group, each ion trap group includes an adjacent P type ion trap and a N-type ion trap, and P type ion trap in arbitrary ion trap group is different compared with the spacing of the P type ion trap in other remaining ions trap groups and N-type ion trap from the spacing between N-type ion trap; In P type ion trap, make a nmos pass transistor, in N-type ion trap, make a PMOS transistor; Form the metal contact hole be positioned in described nmos pass transistor and each source electrode of PMOS transistor, drain electrode; To observe in each ion trap group the bright dark change of the source electrode of the P type ion trap of contiguous PMOS transistor or drain electrode and the source electrode of N-type ion trap or the metal contact hole on draining that are close to nmos pass transistor.
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
Specifically as shown in figs. 1 to 6, first doped p-type ion and N-type ion in semi-conductive substrate, form the ion trap group of some quantity.As shown in Figure 2, (this P type ion trap 1 and N-type ion trap 2 are a part for this substrate to include an adjacent P type ion trap 1 and a N-type ion trap 2 in arbitrary ion trap group, STI (Shallow Trench Isolation, shallow trench isolation from) structure 7 is not filled) between two traps.
Optional but in nonrestrictive embodiment, form the ion trap group of some quantity in Semiconductor substrate, as Fig. 3, and using them as multiple monitoring group or test group (a in one
1, a
2... a
n-m... a
n), wherein n is greater than m and is non-zero natural number, and test group (a
1, a
2... a
n-m... a
n) in P type ion trap 1 different with the spacing of N-type ion trap 2.In the test group of this some quantity, the test group of pre-set minimum range size is assumed to be a
n-m(the P type ion trap P in this test group
n-mwith N-type ion trap N
n-mspacing be the minimum range size of manufacture technics intermediate ion trap), and with this test group for the positive and negative X% of benchmark according to P, N-type ion trap spacing dimension amplifies successively, the spacing formed between P type ion trap 1 and N-type ion trap 2 is respectively (b
1, b
2... b
n-m... b
n) above-mentioned test group (a
1, a
2... a
n-m... a
n).
Such as embody as follows: a in the test group of amplifying with P type ion trap 1 and the positive and negative equal proportion of N-type ion trap 2 spacing dimension
n-mwith previous test group a
n-m-1in P
n-m-1, N
n-m-1the spacing of trap additionally reduces X% and b
n-m(1-X%), with a rear test group a
n-m+1in P
n-m+1, N
n-m+1the spacing of trap additionally increases X% and bn-m (1+X%).Optional but in nonrestrictive embodiment in one, the n-th-m test group a
n-mwith previous test group a
n-m-1in P type ion trap 1 additionally reduce X% (X=50), with a rear test group a with the spacing of N-type ion trap 2
n-m+1in P type ion trap 1 additionally increase X% (X=50) with the spacing of N-type ion trap 2 and by that analogy, form structure as shown in Figure 3.
In an embodiment of the present invention, the preferred ion adopting ion implantation to inject variety classes and various dose in this Semiconductor substrate, forms test group (a
1, a
2... a
n-m... a
n), as shown in Figure 3: in this Semiconductor substrate, implantation concentration is that the phosphorus of j and boron ion form phosphorus N-type ion trap and boron P type ion trap, or be that the arsenic of k and boronation fluorine ion form arsenic N-type ion trap and boronation fluorine P type ion trap to implantation concentration in this Semiconductor substrate.Wherein the concrete concentration of above-mentioned ion and kind set according to the demand of production technology, are not merely fixed on certain certain value, as long as can reach the object of the invention.
Then, making devices such as nmos pass transistor in the P type ion trap 1 in above-mentioned Fig. 2, and the device such as PMOS transistor made in N-type ion trap 2; Form the metal contact hole 3 be arranged in this nmos pass transistor and PMOS transistor each grid 4 both sides, source electrode 5 and drain electrode 6 simultaneously.
Further, the bright dark change of the metal contact hole 3 on the drain electrode 6 of the P type ion trap 1 of contiguous PMOS transistor in each test group and the source electrode 5 of the N-type ion trap 2 of contiguous nmos pass transistor is observed.
As shown in Figure 4, (a of test group normally
1, a
2... a
n-m... a
n) in P type ion trap (P
1, P
2... P
n-m... P
n) corresponding metal contact hole 3 in light tone, N-type ion trap (N
1, N
2... N
n-m... N
n) corresponding metal contact hole 3 is in dark-coloured, according to this principle, in an embodiment of the present invention, by observing the bright dark change of metal contact hole 3, the pattern change detecting P type ion trap 1 or N-type ion trap 2 does not cause the P of negative effect, the minimum spacing of N-type ion trap to device performance.
At optional but this test group (a in nonrestrictive embodiment of one
1, a
2... a
n-m... a
nif) in adopt in ion implantation technology this step the skew of test group intermediate ion trap pattern occur, such as, a certain N-type ion trap pattern closing on nmos pass transistor as shown in Figure 5 offsets (unnecessary N-type ion trap offsets thing 8).
Further, by this test group of an electron microscope observation (a
1, a
2... a
n-m... a
n) in P type ion trap 1 source electrode 5 corresponding with N-type ion trap 2, the metal contact hole 3 on 6 that drains bright dark change, in an embodiment of the present invention, grid 4 pairs of P type ion traps 1 or N-type ion trap 2 source electrode 5 have blanketing effect with drain electrode 6: namely when adopting ion implantation to carry out above-mentioned ion implantation in P type ion trap 1 and N-type ion trap 2, due to test group (a
1, a
2... a
n-m... a
n) in grid 4 isolate after the area of ion trap reduce (i.e. A in Fig. 6 gradually
1-A
nin the area of ion trap reduce gradually, or spacing (b
1, b
2... b
n-m... b
n) become large gradually)), because the dosage of its whole ion implantation is comparatively large, therefore more easily observe the skew of ion trap pattern and the impact on device performance when P, N-type ion trap spacing are less.
Preferably, with the spacing (b between P type ion trap 1 and N-type ion trap 2
1, b
2... b
n-m... b
n) become gradually large direction observe corresponding to the bright dark change of metal contact hole 3, such as, as shown in Figure 6, if test group (a
1, a
2... a
n-m) in the bright dark change of metal contact hole 3 that drains on 6 of the P type ion trap 1 of only contiguous PMOS transistor there is the abnormal i.e. N-type ion trap 2 of contiguous nmos pass transistor source electrode 5 on metal contact hole 3 in dark-coloured, but become dark-coloured with the metal contact hole 3 in the drain electrode 6 of the P type ion trap 1 of contiguous PMOS transistor by light tone, this test group (a is described
1, a
2... a
n-m) middle spacing (b between P type ion trap 1 and N-type ion trap 2
1, b
2... b
n-m) under ion trap pattern drift condition on the negative impact that the performance of device causes; If meanwhile test group (a
n-m+1... a
n) in contiguous PMOS transistor P type ion trap 1 drain electrode 6 on the bright dark change of metal contact hole 3 there is not the abnormal i.e. N-type ion trap 2 of contiguous nmos pass transistor source electrode 5 on metal contact hole 3 in dark-coloured, with the metal contact hole 3 in the drain electrode 6 of the P type ion trap 1 of contiguous PMOS transistor in light tone, this test group (a is described
n-m+1... a
n) middle spacing (b between P type ion trap 1 and N-type ion trap 2
n-m+1... b
n) under ion trap pattern drift condition, negative impact is not caused on the performance of device.Therefore the pattern change detecting P type ion trap 1 or N-type ion trap 2 does not cause the P of negative effect to device performance, the minimum spacing of N-type ion trap is b
n-m+1, no matter ion trap pattern side-play amount is how many equally on the other hand, as long as ensure that P type ion trap 1 is at least b with the spacing of N-type ion trap 2
n-m+1.
By technology of the present invention, under detection ion implanting conditions that can be online, there is pattern and change impact on transistor device performance in P type ion trap 1 and N-type ion trap 2, and pass through further to analyze the P ion trap 1 below the brightness ANOMALOUS VARIATIONS that metal contact hole 3 occurs and the spacing of N ion trap 2, the impact on device performance when different ions trap spacing generation ion trap pattern offsets can be analyzed.
In sum, a kind of method detecting ion trap injection pattern and device performance is affected disclosed by the invention, by designing the semi-conductive substrate of a removal oxidization isolation layer, and observe the bright dark degree forming the metal contact hole be positioned in the source of nmos pass transistor and PMOS transistor, drain electrode, judge that the skew of ion trap detects the minimum spacing between two traps not causing this negative effect to the negative effect of device performance.And the spacing of the P ion trap passed through below the further brightness ANOMALOUS VARIATIONS analyzing generation metal contact hole and N ion trap, the impact on device performance when different ions trap spacing generation ion trap pattern offsets can be analyzed.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (7)
1. detect the method that ion trap injection pattern affects device performance, it is characterized in that, described method comprises:
Step S1, in a substrate respectively doped p-type ion and N-type ion, form multiple ion trap group, each described ion trap group includes an adjacent P type ion trap and a N-type ion trap, and P type ion trap in arbitrary ion trap group is different compared with the spacing of the P type ion trap in other remaining ions trap groups and N-type ion trap from the spacing between N-type ion trap;
Step S2, in described P type ion trap, make a nmos pass transistor, in described N-type ion trap, make a PMOS transistor;
Step S3, form the source electrode, the metal contact hole in drain electrode that are positioned at described nmos pass transistor and PMOS transistor and comprise separately;
The bright dark change of step S4, the source electrode observing in each ion trap group the P type ion trap of contiguous PMOS transistor or drain electrode and the source electrode of N-type ion trap or the metal contact hole on draining that are close to nmos pass transistor;
Wherein, by observing the bright dark change of described metal contact hole, the pattern change detecting P type ion trap or N-type ion trap does not cause the P of negative effect, the minimum safe spacing of N-type ion trap to device performance.
2. the method detecting ion trap injection pattern and device performance is affected as claimed in claim 1, it is characterized in that, the spacing between described P ion trap and described N ion trap to be amplified for benchmark equal proportion with manufacturing process intermediate ion trap spacing minimum range and is formed described ion trap group.
3. the method detecting ion trap injection pattern and affect device performance as claimed in claim 2, it is characterized in that, described magnification ratio is positive and negative 50%.
4. the method detecting ion trap injection pattern and affect device performance as claimed in claim 1, is characterized in that, in step S1, adopt ion implantation in described substrate, inject P type ion and the N-type ion of variety classes and various dose respectively.
5. the method detecting ion trap injection pattern and affect device performance as claimed in claim 1, is characterized in that, in step S1, adopt ion implantation in described substrate, inject P type ion and the N-type ion of variety classes or various dose respectively.
6. the method detecting ion trap injection pattern and affect device performance as claimed in claim 1, is characterized in that, by the bright dark change of the metal contact hole in source electrode, drain electrode described in an electron microscope observation.
7. the method detecting ion trap injection pattern and device performance is affected as claimed in claim 1, it is characterized in that, if wherein secretly there is not change in the bright of metal contact hole of an ion trap group, and the bright dark appearance change of the metal contact hole of the ion trap group be adjacent, then secretly there is not the minimum safe spacing that the P type ion trap included by ion trap group of change and the distance between N-type ion trap are ion trap diffusion in the bright of metal contact hole.
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2014
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6577149B2 (en) * | 2001-01-05 | 2003-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for addressable failure site test structure |
| CN102142383A (en) * | 2010-02-03 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN102768968A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for detecting diffusivity of wellblock implantation ions in different concentrations |
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| CN103247550A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | Test module and method for monitoring processing procedure stability |
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