CN104253016B - The method for improving high resistant production capacity - Google Patents
The method for improving high resistant production capacity Download PDFInfo
- Publication number
- CN104253016B CN104253016B CN201310259759.7A CN201310259759A CN104253016B CN 104253016 B CN104253016 B CN 104253016B CN 201310259759 A CN201310259759 A CN 201310259759A CN 104253016 B CN104253016 B CN 104253016B
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- China
- Prior art keywords
- polysilicon layer
- high resistant
- metering
- prepared
- electric capacity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
Abstract
The present invention provides a kind of method for improving high resistant production capacity.During the method prepares high resistant in being included in polycrystalline silicon deposit boiler tube, after preparation completes the first polysilicon layer, the cleaning of lasting Preset Time is carried out to the upper surface of the first polysilicon layer using acidic liquid；Electric capacity middle dielectric layer is prepared in the upper surface of the first polysilicon layer through cleaning；The second polysilicon layer, and the impurity element that injection second is measured on second polysilicon layer are prepared on the electric capacity middle dielectric layer；Second metering is more than the first metering, during first metering is prepared the high resistant of similar resistance not clean to the upper surface of first polysilicon layer, the metering of the impurity element that needs are injected on second polysilicon layer.Cleaning of the present invention by the increase acidic liquid before electric capacity middle dielectric layer is prepared, and in the generation technique of the follow-up injection metering for increasing impurity element, provide the production capacity that polycrystalline silicon deposit boiler tube prepares high resistant.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of method for improving high resistant production capacity.
Background technology
In complementary metal oxide semiconductors (CMOS)（ComplementaryMetalOxideSemiconductor；Referred to as：
CMOS）In technique, high resistant is usually to be made using polysilicon in deposit boiler tube, and deposit boiler tube includes multiple cassettes
For making high resistant.Due to reasons such as polycrystalline silicon deposit furnace tube temperature uniformity and airflow homogeneities, in the crystalline substance of fire door cassette
The film layer of circle growth is thicker, and relatively thin with stove tail in stove, so just causes in a long body of heater, not all of boat position
Production requirement can be met.
For example, application including the deposit boiler tube of the cassettes of at least 6 placement wafers making during the high resistant of 1K ohms, operation
One stove only has No. 2 boat potential energies to meet production requirement, understands the resistance of the high resistant that No. 2 boat positions are produced in 800-1200 by test
Fluctuate in the range of ohm, this is specification line, is considered as beyond this range product unqualified.Generally, in addition to No. 2 boat positions
The high resistant that other boat positions make easily exceeds prescribed limit, is unsatisfactory for generating requirement, limits production capacity.
The content of the invention
For the defect of prior art, the present invention provides a kind of method for improving high resistant production capacity, including：
During high resistant is prepared in polycrystalline silicon deposit boiler tube, prepare on the silicon chip of each boat position and complete the first polysilicon
After layer, the cleaning of lasting Preset Time is carried out to the upper surface of the first polysilicon layer on each boat position using acidic liquid；
Electric capacity middle dielectric layer is prepared in the upper surface of the first polysilicon layer through cleaning；
The second polysilicon layer is prepared on the electric capacity middle dielectric layer, and second is injected on second polysilicon layer
The impurity element of metering；Second metering is more than the first metering, and first metering is not for first polysilicon layer
Upper surface is cleaned and during being prepared the high resistant of similar resistance, is needed the impurity injected on second polysilicon layer
The metering of element.
The method of the raising high resistant production capacity that the present invention is provided, by increasing Acidic Liquid before electric capacity middle dielectric layer is prepared
The cleaning of body, and in the generation technique of the follow-up injection metering for increasing impurity element, provide the preparation of polycrystalline silicon deposit boiler tube high
The production capacity of resistance.
Description of the drawings
Fig. 1 is the embodiment of the method schematic flow sheet that the present invention improves high resistant production capacity；
Fig. 2 is the embodiment of the present invention through cleaning and not cleaned high resistant resistance contrast schematic diagram；
Fig. 3 is embodiment of the present invention electric capacity uniformity contrast schematic diagram；
Fig. 4 is No. 2 boat position high resistant resistance fluctuation schematic diagrams of the embodiment of the present invention；
Fig. 5 is No. 3 boat position high resistant resistance fluctuation schematic diagrams of the embodiment of the present invention.
Specific embodiment
When prior art application polycrystalline silicon deposit boiler tube prepares high resistant, because of factors such as temperature homogeneity and airflow homogeneities
Affect, the high resistant of one stove only one of which boat position of operation can meet production requirement.Test shows that the high resistant for making 1K ohms is adjacent every
Individual boat interdigit differs 50 ohm, and the high resistant of only No. 2 boat positions meets requirement, therefore limits the high resistant product of polycrystalline silicon deposit boiler tube
Energy.Defect of the present invention for prior art, there is provided a solution is transformed to semiconductor device technological process, advanced
The cleaning of row acid solution, and increase high resistant injection metering to improve the high resistant production capacity of polycrystalline silicon deposit boiler tube follow-up.
Fig. 1 is the embodiment of the method schematic flow sheet that the present invention improves high resistant production capacity, and the method is to prior art application
Polycrystalline silicon deposit boiler tube prepares the technological process of production of high resistant and is improved, specifically as shown in figure 1, the method includes：
Step 101, prepare high resistant in polycrystalline silicon deposit boiler tube during, prepare on the silicon chip of each boat position and complete the
After one polysilicon layer, the clear of lasting Preset Time is carried out to the upper surface of the first polysilicon layer on each boat position using acidic liquid
Wash；
During high resistant being prepared in polycrystalline silicon deposit boiler tube, arrange on each boat position in deposit boiler tube first and close
Suitable silicon chip, and carry out an oxygen, then prepares the first polysilicon layer on silicon chip.Flow process made above and prior art
Preparation flow is identical, and here is omitted.
In the embodiment of the present invention, after preparation completes the first polysilicon layer, electric capacity middle dielectric layer is not directly prepared, and
It is that first the upper surface of the first polysilicon layer on each boat position is cleaned, specifically can carries out continuing using acidic liquid pre-
If the cleaning of time.Preferably, acidic liquid can be Fluohydric acid..The embodiment of the present invention is by applying Fluohydric acid. to the first polycrystalline
The upper surface of silicon layer is cleaned, can be by electric capacity that the is upper surface of the first polysilicon layer more smooth, preparing thereon then
Middle dielectric layer also will be more smooth, it is to avoid electric capacity middle dielectric layer uneven distribution occurs in the high resistant for generating out, or even occurs
The defect in dew hole.
Will further, the persistent period of the cleaning carried out using acidic liquid, can be according to practical situation and empirical value
Set.
Step 102, the upper surface of the first polysilicon layer cleaned in process prepare electric capacity middle dielectric layer；
After the completion of cleaning to the first polysilicon layer using acidic liquid, continue in the first polysilicon layer through cleaning
Upper surface prepare electric capacity middle dielectric layer.The flow process for preparing electric capacity middle dielectric layer is same as the prior art, no longer goes to live in the household of one's in-laws on getting married herein
State.
Step 103, the second polysilicon layer is prepared on the electric capacity middle dielectric layer, and on second polysilicon layer
The impurity element of the second metering of injection；Second metering is more than the first metering, and first metering is not for more than described first
The upper surface of crystal silicon layer is cleaned and during being prepared the high resistant of similar resistance, needs to note on second polysilicon layer
The metering of the impurity element for entering.
After preparation completes electric capacity middle dielectric layer, continue the second polysilicon layer is prepared on electric capacity middle dielectric layer, and to
The impurity element such as phosphonium ion of the second metering of injection on second polysilicon layer.
It should be noted that after the first polysilicon layer of preparation in the prior art, electric capacity middle dielectric layer is directly prepared,
And in the technological process for continuing prepare the second polysilicon layer, it is also desirable to implanted dopant element, such as root on the second polysilicon layer
Injection metering is needed for the first metering, i.e., the injection on the second polysilicon layer in prior art according to the resistance of high resistant to be produced
The impurity element of the first metering can meet the production requirement of high resistant resistance.
In due to the embodiment of the present invention, will be using Fluohydric acid. to the first polysilicon layer before electric capacity middle dielectric layer is prepared
Cleaned, therefore the resistance of the high resistant that the resistance value ratio for causing high resistant overall is not carried out hydrofluoric acid clean and prepared will height.Cause
This, in order to meet production requirement, the overall resistance of high resistant is lowered, therefore to the second polysilicon in the embodiment of the present invention
On layer during implanted dopant element, increase the injection metering resistance overall to reduce high resistant.As the first metering is not right
The upper surface of the first polysilicon layer is cleaned and during being prepared the high resistant of similar resistance, is needed on the second polysilicon layer
The metering of the impurity element of injection, therefore the second metering injected in the embodiment of the present invention is more than the first metering.
By the injection metering for increasing impurity element so that elevated resistance decrease before, so as to meet production requirement；And
And further, by above-mentioned technological process polycrystalline silicon deposit boiler tube by have at least two boat positions production come high resistant will expire
Sufficient production requirement, so as to the production capacity of the high resistant of raising.
Below in conjunction with an instantiation, the method for the raising high resistant production capacity provided by the embodiment of the present invention is discussed in detail.
The embodiment of the present invention needs to produce high resistant of the resistance for 1K ohms.Idiographic flow includes：In polycrystalline silicon deposit boiler tube
In each boat position on silicon chip is set, the first polysilicon layer is prepared on silicon chip.
Fig. 2 is that the embodiment of the present invention passes through cleaning and not cleaned high resistant resistance contrast schematic diagram, as shown in Figure 2（Figure
Middle Y-axis represents resistance, and left figure is that right figure is the schematic diagram without over cleaning through the schematic diagram for cleaning）, preparing in the middle of electric capacity
Hydrofluoric acid clean is added 120 seconds before dielectric layer（Or the longer time）, high resistant can be made integrally to be higher by 100 ohm.After cleaning is introduced,
Electric capacity middle dielectric layer is prepared on first polysilicon layer, and the second polysilicon layer is prepared on electric capacity middle dielectric layer, then to
Two polysilicon layers inject phosphonium ion.Fig. 3 is embodiment of the present invention electric capacity uniformity contrast schematic diagram, as shown in Figure 3（Y-axis in figure
Electric capacity is represented, left figure is the schematic diagram of the present invention, and right figure is the schematic diagram of prior art）, the embodiment of the present invention is compared to existing
Technology increases 10% implantation dosage on the whole, and as the concentration of phosphonium ion becomes big, electric capacity uniformity can improve.Can by upper figure
See that increase by 120 seconds electric capacity uniformities of hydrofluoric acid clean can be improved, high resistant can be higher 100 ohm than not doing the high resistant that cleans, so handle
1K high resistants implantation dosage is changed into 2.2E15 from 2.1E15 is every square centimeter, as concentration becomes big so high resistant can become uniform.Fig. 4 is
No. 2 boat position high resistant resistance fluctuation schematic diagrams of the embodiment of the present invention, Fig. 5 are that No. 3 boat position high resistant resistance fluctuations of the embodiment of the present invention are shown
It is intended to, from Fig. 4 and Fig. 5, the high resistant resistance fluctuation of No. 2 and No. 3 boat positions in acceptability limit, therefore be able to can be doubled
High resistant operation production capacity.
Finally it should be noted that：Various embodiments above only to illustrate technical scheme, rather than a limitation；To the greatest extent
Pipe has been described in detail to the present invention with reference to foregoing embodiments, it will be understood by those within the art that：Its according to
So the technical scheme described in foregoing embodiments can be modified, or which part or all technical characteristic are entered
Row equivalent；And these modifications or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology
The scope of scheme.
Claims (5)
1. it is a kind of improve high resistant production capacity method, it is characterised in that include：
During high resistant is prepared in polycrystalline silicon deposit boiler tube, prepare on the silicon chip of each boat position and complete the first polysilicon layer
Afterwards, the cleaning of lasting Preset Time is carried out using acidic liquid to the upper surface of the first polysilicon layer on each boat position；
Electric capacity middle dielectric layer is prepared in the upper surface of the first polysilicon layer through cleaning；
The second polysilicon layer is prepared on the electric capacity middle dielectric layer, and injection second is measured on second polysilicon layer
Impurity element；Second metering is more than the first metering, and first metering is upper table not to first polysilicon layer
Face is cleaned and during being prepared the high resistant of similar resistance, is needed the impurity element injected on second polysilicon layer
Metering.
2. method according to claim 1, it is characterised in that the acidic liquid is Fluohydric acid..
3. method according to claim 1 and 2, it is characterised in that the Preset Time is more than or equal to 120 seconds.
4. method according to claim 1 and 2, it is characterised in that second metering is more by 10% than the first metering.
5. method according to claim 1 and 2, it is characterised in that the impurity element is phosphonium ion.
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| CN201310259759.7A CN104253016B (en) | 2013-06-26 | 2013-06-26 | The method for improving high resistant production capacity |
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| CN201310259759.7A CN104253016B (en) | 2013-06-26 | 2013-06-26 | The method for improving high resistant production capacity |
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| CN104253016A CN104253016A (en) | 2014-12-31 |
| CN104253016B true CN104253016B (en) | 2017-04-05 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| CN102468127A (en) * | 2010-11-03 | 2012-05-23 | 北大方正集团有限公司 | Method for cleaning wafer in double polycrystalline capacitance process |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100436050B1 (en) * | 2001-08-24 | 2004-06-12 | 주식회사 하이닉스반도체 | Method of fabricating capacitor |
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- 2013-06-26 CN CN201310259759.7A patent/CN104253016B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| CN102468127A (en) * | 2010-11-03 | 2012-05-23 | 北大方正集团有限公司 | Method for cleaning wafer in double polycrystalline capacitance process |
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| CN104253016A (en) | 2014-12-31 |
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Effective date of registration: 20220721 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |