CN104252324A - System and method for dynamically simulating VGA (Video Graphic Array) signals - Google Patents
System and method for dynamically simulating VGA (Video Graphic Array) signals Download PDFInfo
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Abstract
The invention relates to a system and a method for dynamically simulating VGA (Video Graphic Array) signals. The system comprises a VGA interface, a controllable switching circuit, a simulation load, a software control module, a signal control interface and a VGA driving module, wherein the software control module is used for sending an output signal instruction to the VGA driving module and judging whether the signal is normally output or not; when the signal is normally output, enabling the software control module to output a first control instruction to the controllable switching circuit through the signal control interface so as to disconnect the simulation load; when the signal is not normally output, enabling the software control module to output a second control instruction to the controllable switching circuit so as to connect the simulation load. The simulation load can be connected without using pins of the VGA interface, so that the output image quality is improved; furthermore, by virtue of dynamically simulating the load, so that the load loading time is quite short, and the possibility that the simulation load influences the VGA driving module is reduced.
Description
Technical field
The present invention relates to computer realm, particularly relate to a kind of system and method for dynamic similation Video Graphics Array signal.
Background technology
VGA(Video Graphics Array, Video Graphics Array) be a kind of video transmission standard that IBM released with PS/2 machine in 1987, there is the advantages such as resolution is high, display speed is fast, various colors, be widely used in color monitor field.USB interface is the video display translation interface that field of personal computers is most widely used, and adopts 15 pin connected modes of asymmetric distribution, has 15 pins.Traditional USB interface, when interface is set to zero load (namely not having display apparatus to access), no signal exports, now access display again, often cause picture signal to export not in time or not output image signal, usually use fictitious load mode to allow USB interface when even without still output image signal always when access display device for this reason.
Tradition uses fictitious load mode to be by resistance one end ground connection, 1 of the other end and USB interface, 2, to connect respectively between 3 pin a gate-controlled switch circuit, the control signal of gate-controlled switch connects 6 of USB interface respectively, 7, 8 pin, when VGA does not access display device, control signal does not have low level to access, gate-controlled switch circuit is in channel status, resistance is switched on, display driver thinks display device still on interface, output image signal, when VGA accesses display device, control signal has low level to access, gate-controlled switch circuit is in off-state, 1 of USB interface, 2, 3 signals directly access display load, output image signal simultaneously.
But, tradition uses in fictitious load mode, when USB interface does not access display device, the long-time fictitious load of resistance causes driver unstable, and owing to need judge whether display device accesses, 6,7,8 pin access analogue load circuits of VGA signal, can cause image quality decrease when exporting high-resolution image, as water ripples shake and smear situation appear in picture.
Summary of the invention
Based on this, be necessary the problem causing driver instability for the image quality decrease exported in existing fictitious load mode and long-time fictitious load, provide a kind of and can improve output image quality and reduce fictitious load to the system affecting the dynamic similation Video Graphics Array signal of probability of VGA driver module.
In addition, there is a need to the problem causing driver instability for the image quality decrease exported in existing fictitious load mode and long-time fictitious load, provide a kind of and can improve output image quality and reduce fictitious load to the method affecting the dynamic similation Video Graphics Array signal of probability of VGA driver module.
A kind of system of dynamic similation Video Graphics Array signal, comprise Video Graphics Array interface, gate-controlled switch circuit and fictitious load, one end ground connection of described fictitious load, the other end is connected with the three primary colours pin of described Video Graphics Array interface is electric respectively by described gate-controlled switch circuit, the system of described dynamic similation Video Graphics Array signal also comprises signal control interface, software control module and Video Graphics Array driver module, described software control module is connected with described Video Graphics Array driver module, and described software control module is connected with the signal control end of described gate-controlled switch circuit by described signal control interface, described Video Graphics Array driver module is connected with described Video Graphics Array interface,
Described software control module is used for sending output signal instruction to described Video Graphics Array driver module, and judges whether signal normally exports;
When described signal normally exports, described software control module exports the first steering order to disconnect described fictitious load by described signal control interface to described gate-controlled switch circuit;
When described signal does not normally export, described software control module exports the second steering order to be communicated with described fictitious load by described signal control interface to described gate-controlled switch circuit.
Wherein in an embodiment, described gate-controlled switch circuit is metal-oxide-semiconductor, triode, thyristor, IGBT pipe or relay.
Wherein in an embodiment, when described gate-controlled switch circuit is N-channel MOS pipe, N-type triode or N-type IGBT pipe, described first steering order is low level instruction, and described second steering order is high level instruction;
When described gate-controlled switch circuit is P channel MOS tube, P type triode or P type IGBT pipe, described first steering order is high level instruction, and described second steering order is low level instruction.
Wherein in an embodiment, described signal control interface is universal input/output interface.
Wherein in an embodiment, described gate-controlled switch circuit comprises three N-channel MOS pipes, be respectively the first N-channel MOS pipe, the second N-channel MOS pipe and the 3rd N-channel MOS pipe, described fictitious load comprises three resistance, is respectively the first resistance, the second resistance and the 3rd resistance;
The source electrode of described first N-channel MOS pipe is by described first resistance eutral grounding, and drain electrode is electrically connected with the red primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The source electrode of described second N-channel MOS pipe is by described second resistance eutral grounding, and drain electrode is electrically connected with the green primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The source electrode of described 3rd N-channel MOS pipe is by described 3rd resistance eutral grounding, and drain electrode is electrically connected with the blue primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface.
Wherein in an embodiment, the drain electrode of described three metal-oxide-semiconductors is connected respectively by stabilivolt with grid.
A method for dynamic similation Video Graphics Array signal, comprising:
One Video Graphics Array interface is provided, gate-controlled switch circuit, fictitious load, signal control interface, software control module and Video Graphics Array driver module, one end ground connection of described fictitious load, the other end is connected with the three primary colours pin of described Video Graphics Array interface is electric respectively by described gate-controlled switch circuit, described software control module is connected with described Video Graphics Array driver module, and described software control module is connected with the signal control end of described gate-controlled switch circuit by described signal control interface, described Video Graphics Array driver module is connected with described Video Graphics Array interface,
Obtain input instruction, send output signal instruction according to described input instruction to described Video Graphics Array driver module;
Judge whether signal normally exports, if, then export the first steering order to disconnect described fictitious load by described signal control interface to described gate-controlled switch circuit, if not, then the second steering order is exported to be communicated with described fictitious load by described signal control interface to described gate-controlled switch circuit.
Wherein in an embodiment, described gate-controlled switch circuit is metal-oxide-semiconductor, triode, thyristor, IGBT pipe or relay.
Wherein in an embodiment, when described gate-controlled switch circuit is N-channel MOS pipe, N-type triode or N-type IGBT pipe, described first steering order is low level instruction, and described second steering order is high level instruction;
When described gate-controlled switch circuit is P channel MOS tube, P type triode or P type IGBT pipe, described first steering order is high level instruction, and described second steering order is low level instruction.
Wherein in an embodiment, described method also comprises:
Described gate-controlled switch circuit comprises three N-channel MOS pipes, be respectively the first N-channel MOS pipe, the second N-channel MOS pipe and the 3rd N-channel MOS pipe, described fictitious load comprises three resistance, be respectively the first resistance, the second resistance and the 3rd resistance, described signal control interface is universal input/output interface;
By the source electrode of described first N-channel MOS pipe by described first resistance eutral grounding, drain electrode is electrically connected with the red primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
By the source electrode of described second N-channel MOS pipe by described second resistance eutral grounding, drain electrode is electrically connected with the green primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
By the source electrode of described 3rd N-channel MOS pipe by described 3rd resistance eutral grounding, drain electrode is electrically connected with the blue primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The drain electrode of described three metal-oxide-semiconductors is connected respectively by stabilivolt with grid.
The system and method for above-mentioned dynamic similation Video Graphics Array signal, the problem of driver instability is caused for the image quality decrease exported in existing fictitious load mode and long-time fictitious load, software control module is adopted to export the first steering order or the second steering order to signal control interface, control the disconnection of gate-controlled switch circuit with closed, disconnect with control simulation load or be communicated with, do not need the stitch access fictitious load using USB interface, improve the quality of output image, and Dynamic model load makes the load load time very short, reduce fictitious load and probability is affected on VGA driver module.
Accompanying drawing explanation
Fig. 1 is the structural representation of the system of dynamic similation Video Graphics Array signal in an embodiment;
Fig. 2 is the pin schematic diagram of USB interface;
The circuit structure diagram that Fig. 3 is fictitious load, gate-controlled switch circuit, USB interface are connected with signal control interface;
Fig. 4 is the process flow diagram of the method for dynamic similation Video Graphics Array signal in an embodiment.
Embodiment
Below in conjunction with specific embodiment and accompanying drawing, the technical scheme to the system and method for dynamic similation Video Graphics Array signal is described in detail, to make it clearly.
As shown in Figure 1, be the structural representation of system of dynamic similation Video Graphics Array signal in an embodiment.The system of this dynamic similation Video Graphics Array signal, comprises fictitious load 102, gate-controlled switch circuit 104, Video Graphics Array interface 106, signal control interface 108, software control module 110 and Video Graphics Array driver module 112.
Wherein, one end ground connection of fictitious load 102, the other end is connected with the three primary colours pin (R1, G2, B3) of USB interface 106 is electric respectively by gate-controlled switch circuit 104; Software control module 110 is connected with VGA driver module 112, and is connected with the signal control end of gate-controlled switch circuit 104 by signal control interface 108, and VGA driver module 112 is connected with USB interface 106.
Software control module 110 is for sending output signal instruction to VGA driver module, and judge whether signal normally exports, when signal normally exports, software control module 110 exports the first steering order to disconnect fictitious load 102 by signal control interface 108 to gate-controlled switch circuit 104; When signal does not normally export, software control module 110 exports the second steering order to be communicated with fictitious load 102 by signal control interface 108 to gate-controlled switch circuit 104.
Concrete, when signal normally exports, software control module 110 exports the first steering order by signal control interface 108 to gate-controlled switch circuit 104, and according to the first steering order, control gate-controlled switch circuit 104 and be in off-state, thus disconnect fictitious load 102; When signal does not normally export, software control module 110 exports the second steering order by signal control interface 108 to gate-controlled switch circuit 104, and according to the second steering order, control gate-controlled switch circuit 104 and be in closure state, thus be communicated with fictitious load 102, VGA driver module 112 is thought, and USB interface 106 accesses display device, and is exported by signal.
Fictitious load 102 can be the resistance of 75 ohm, also can be the resistance of other resistances.
Gate-controlled switch circuit 104 can be metal-oxide-semiconductor, triode, relay, IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) manage or thyristor, also can be the components and parts that other realize switching function.When gate-controlled switch circuit 104 is N-channel MOS pipe, N-type triode or N-type IGBT, then the first steering order is low level instruction, and the second steering order is high level instruction.When gate-controlled switch circuit 104 is P channel MOS tube, P type triode or P type IGBT pipe, then the first steering order is high level instruction, and the second steering order is low level instruction.When gate-controlled switch circuit 104 is relay, by pilot relay size of current pilot relay break-make.When gate-controlled switch circuit 104 is thyristor, control the gate voltage of thyristor, conducting during positive voltage, disconnects during negative voltage.
As shown in Figure 2, USB interface 106 has 15 pins, is divided into three rows, often arranges 5.1st pin is red primary, the 2nd pin is green primary, the 3rd pin is blue primary, the 4th pin is address code, the 5th pin is self-test, the 6th pin be redly, the 7th pin is greenery patches, the 8th pin is blue ground, 9th pin for retaining, the 10th pin for digitally, the 11st pin is address code (ID0 display indicate position 0), 12nd pin is that address code (ID1 display indicates position 1), the 13rd pin are for going synchronously, 14th pin is field synchronization, and the 15th pin is address code (ID3 or display indicate position 3).
As shown in Figure 3, be circuit structure diagram that fictitious load 102, gate-controlled switch circuit 104, USB interface 106 are connected with signal control interface 108.In Fig. 3, fictitious load 102 comprises 3 resistance, is respectively the first resistance R171, the second resistance R172 and the 3rd resistance R173, gate-controlled switch circuit 104 comprises three N-channel MOS pipes, is respectively the first N-channel MOS pipe Q7, the second N-channel MOS pipe Q8 and the 3rd N-channel MOS pipe Q9.
The source electrode of the first N-channel MOS pipe Q7 is by the first resistance R171 ground connection, and the drain electrode of the first N-channel MOS pipe Q7 is electrically connected with the red primary pin (the 1st pin) of the three primary colours pin of USB interface 106, and the grid of the first N-channel MOS pipe Q7 is connected with signal control interface 108.The drain electrode of the first N-channel MOS pipe Q7 is connected respectively by stabilivolt with grid.
The source electrode of the second N-channel MOS pipe Q8 is by the second resistance R172 ground connection, and the drain electrode of the second N-channel MOS pipe Q8 is electrically connected with the green primary pin (the 2nd pin) of the three primary colours pin of USB interface 106, and the grid of the second N-channel MOS pipe Q8 is connected with signal control interface 108.The drain electrode of the second N-channel MOS pipe Q8 is connected respectively by stabilivolt with grid.
The source electrode of the 3rd N-channel MOS pipe Q9 is by the 3rd resistance R173 ground connection, and the drain electrode of the 3rd N-channel MOS pipe Q9 is electrically connected with the blue primary pin (the 3rd pin) of the three primary colours pin of USB interface 106, and the grid of the 3rd N-channel MOS pipe Q9 is connected with signal control interface 108.The drain electrode of the 3rd N-channel MOS pipe Q9 is connected respectively by stabilivolt with grid.
Signal control interface 108 can be GPIO(General Purpose Input Output, universal input/output interface) or other input/output interfaces etc.
In addition, in Fig. 3, three metal-oxide-semiconductor grids connect GPIO interface by the 4th resistance R175, and by shunt capacitance C903 and C904 ground connection.The resistance of the 4th resistance R175 is 1 kilo-ohm, and the electric capacity of electric capacity C904 is 10 microfarads, and voltage is 6.3 volts, and the electric capacity of electric capacity C904 is 0.1 microfarad, and voltage is 16 volts.
In addition, software control module 110 and VGA drive control module 112 are controlled by operating system.This operating system can be LIUNX, WINDOWS, UNIX or other operating system.Driving under the corresponding platform that VGA driver module 112 provides for display adapter for hardware device manufacturer.
The system of above-mentioned dynamic similation Video Graphics Array signal, the problem of driver instability is caused for the image quality decrease exported in existing fictitious load mode and long-time fictitious load, software control module is adopted to export the first steering order or the second steering order to signal control interface, control the disconnection of gate-controlled switch circuit with closed, disconnect with control simulation load or be communicated with, do not need the stitch access fictitious load using USB interface, improve the quality of output image, and Dynamic model load makes the load load time very short, reduce fictitious load and probability is affected on VGA driver module.
As shown in Figure 4, be the method for dynamic similation Video Graphics Array signal in an embodiment, comprise:
Step S402, one Video Graphics Array interface is provided, gate-controlled switch circuit, fictitious load, signal control interface, software control module and Video Graphics Array driver module, one end ground connection of this fictitious load, the other end is connected with the three primary colours pin of this Video Graphics Array interface is electric respectively by this gate-controlled switch circuit, this software control module is connected with this Video Graphics Array driver module, and this software control module is connected with the signal control end of this gate-controlled switch circuit by this signal control interface, this Video Graphics Array driver module is connected with this Video Graphics Array interface.
Step S404, obtains input instruction, sends output signal instruction according to this input instruction to Video Graphics Array driver module.
Step S406, judges whether signal normally exports, and if so, performs step S408, if not, performs step S410.
Step S408, exports the first steering order to disconnect this fictitious load by this signal control interface to this gate-controlled switch circuit.
Step S410, exports the second steering order to be communicated with this fictitious load by this signal control interface to this gate-controlled switch circuit.
In the present embodiment, gate-controlled switch circuit 104 can be metal-oxide-semiconductor, triode, relay, IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) manage or thyristor, also can be the components and parts that other realize switching function.This gate-controlled switch circuit is N-channel MOS pipe, N-type triode or N-type IGBT, and this first steering order is low level instruction, and this second steering order is high level instruction.
In other embodiments, when this gate-controlled switch circuit is P channel MOS tube, P type triode or P type IGBT, this first steering order is high level instruction, and this second steering order is low level instruction.
Further, the method for above-mentioned dynamic similation Video Graphics Array signal, also comprises:
This gate-controlled switch circuit comprises three N-channel MOS pipes, be respectively the first N-channel MOS pipe, the second N-channel MOS pipe and the 3rd N-channel MOS pipe, this fictitious load comprises three resistance, be respectively the first resistance, the second resistance and the 3rd resistance, this signal control interface can be universal input/output interface;
By the source electrode of this first N-channel MOS pipe by this first resistance eutral grounding, drain electrode is electrically connected with the red primary pin of the three primary colours pin of this Video Graphics Array interface, and grid is connected with this signal control interface;
By the source electrode of this second N-channel MOS pipe by this second resistance eutral grounding, drain electrode is electrically connected with the green primary pin of the three primary colours pin of this Video Graphics Array interface, and grid is connected with this signal control interface;
By the source electrode of the 3rd N-channel MOS pipe by the 3rd resistance eutral grounding, drain electrode is electrically connected with the blue primary pin of the three primary colours pin of this Video Graphics Array interface, and grid is connected with this signal control interface;
The drain electrode of these three metal-oxide-semiconductors is connected respectively by stabilivolt with grid.
The method of above-mentioned dynamic similation Video Graphics Array signal, the problem of driver instability is caused for the image quality decrease exported in existing fictitious load mode and long-time fictitious load, adopt and export the first steering order or the second steering order to signal control interface, control the disconnection of gate-controlled switch circuit with closed, disconnect with control simulation load or be communicated with, do not need the stitch access fictitious load using USB interface, improve the quality of output image, and Dynamic model load makes the load load time very short, reduce fictitious load and probability is affected on VGA driver module.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. the system of a dynamic similation Video Graphics Array signal, comprise Video Graphics Array interface, gate-controlled switch circuit and fictitious load, one end ground connection of described fictitious load, the other end is connected with the three primary colours pin of described Video Graphics Array interface is electric respectively by described gate-controlled switch circuit, it is characterized in that, the system of described dynamic similation Video Graphics Array signal also comprises signal control interface, software control module and Video Graphics Array driver module, described software control module is connected with described Video Graphics Array driver module, and described software control module is connected with the signal control end of described gate-controlled switch circuit by described signal control interface, described Video Graphics Array driver module is connected with described Video Graphics Array interface,
Described software control module is used for sending output signal instruction to described Video Graphics Array driver module, and judges whether signal normally exports;
When described signal normally exports, described software control module exports the first steering order to disconnect described fictitious load by described signal control interface to described gate-controlled switch circuit;
When described signal does not normally export, described software control module exports the second steering order to be communicated with described fictitious load by described signal control interface to described gate-controlled switch circuit.
2. the system of dynamic similation Video Graphics Array signal according to claim 1, is characterized in that, described gate-controlled switch circuit is metal-oxide-semiconductor, triode, thyristor, IGBT pipe or relay.
3. the system of dynamic similation Video Graphics Array signal according to claim 1, it is characterized in that, when described gate-controlled switch circuit is N-channel MOS pipe, N-type triode or N-type IGBT pipe, described first steering order is low level instruction, and described second steering order is high level instruction;
When described gate-controlled switch circuit be P channel MOS tube or P type triode or P type IGBT pipe time, described first steering order is high level instruction, and described second steering order is low level instruction.
4. the system of dynamic similation Video Graphics Array signal according to claim 1, is characterized in that, described signal control interface is universal input/output interface.
5. the system of dynamic similation Video Graphics Array signal according to claim 1, it is characterized in that, described gate-controlled switch circuit comprises three N-channel MOS pipes, be respectively the first N-channel MOS pipe, the second N-channel MOS pipe and the 3rd N-channel MOS pipe, described fictitious load comprises three resistance, is respectively the first resistance, the second resistance and the 3rd resistance;
The source electrode of described first N-channel MOS pipe is by described first resistance eutral grounding, and drain electrode is electrically connected with the red primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The source electrode of described second N-channel MOS pipe is by described second resistance eutral grounding, and drain electrode is electrically connected with the green primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The source electrode of described 3rd N-channel MOS pipe is by described 3rd resistance eutral grounding, and drain electrode is electrically connected with the blue primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface.
6. the system of dynamic similation Video Graphics Array signal according to claim 5, is characterized in that, the drain electrode of described three metal-oxide-semiconductors is connected respectively by stabilivolt with grid.
7. a method for dynamic similation Video Graphics Array signal, comprising:
One Video Graphics Array interface is provided, gate-controlled switch circuit, fictitious load, signal control interface, software control module and Video Graphics Array driver module, one end ground connection of described fictitious load, the other end is connected with the three primary colours pin of described Video Graphics Array interface is electric respectively by described gate-controlled switch circuit, described software control module is connected with described Video Graphics Array driver module, and described software control module is connected with the signal control end of described gate-controlled switch circuit by described signal control interface, described Video Graphics Array driver module is connected with described Video Graphics Array interface,
Obtain input instruction, send output signal instruction according to described input instruction to described Video Graphics Array driver module;
Judge whether signal normally exports, if, then export the first steering order to disconnect described fictitious load by described signal control interface to described gate-controlled switch circuit, if not, then the second steering order is exported to be communicated with described fictitious load by described signal control interface to described gate-controlled switch circuit.
8. the method for dynamic similation Video Graphics Array signal according to claim 7, is characterized in that, described gate-controlled switch circuit is metal-oxide-semiconductor, triode, thyristor, IGBT pipe or relay.
9. the method for dynamic similation Video Graphics Array signal according to claim 7, it is characterized in that, when described gate-controlled switch circuit is N-channel MOS pipe, N-type triode or N-type IGBT pipe, described first steering order is low level instruction, and described second steering order is high level instruction;
When described gate-controlled switch circuit is P channel MOS tube, P type triode or P type IGBT pipe, described first steering order is high level instruction, and described second steering order is low level instruction.
10. the method for dynamic similation Video Graphics Array signal according to claim 7, it is characterized in that, described method also comprises:
Described gate-controlled switch circuit comprises three N-channel MOS pipes, be respectively the first N-channel MOS pipe, the second N-channel MOS pipe and the 3rd N-channel MOS pipe, described fictitious load comprises three resistance, be respectively the first resistance, the second resistance and the 3rd resistance, described signal control interface is universal input/output interface;
By the source electrode of described first N-channel MOS pipe by described first resistance eutral grounding, drain electrode is electrically connected with the red primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
By the source electrode of described second N-channel MOS pipe by described second resistance eutral grounding, drain electrode is electrically connected with the green primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
By the source electrode of described 3rd N-channel MOS pipe by described 3rd resistance eutral grounding, drain electrode is electrically connected with the blue primary pin of the three primary colours pin of described Video Graphics Array interface, and grid is connected with described signal control interface;
The drain electrode of described three metal-oxide-semiconductors is connected respectively by stabilivolt with grid.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107293270A (en) * | 2016-04-05 | 2017-10-24 | 深圳市亿威尔信息技术股份有限公司 | The sustainable display system normally shown of VGA signals |
| CN116609706A (en) * | 2023-07-19 | 2023-08-18 | 北京同方艾威康科技有限公司 | VGA image quality nondestructive disconnection detection method |
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| CN201237888Y (en) * | 2008-08-07 | 2009-05-13 | 深圳市神舟电脑股份有限公司 | Interface circuit for implementing VGA input/output function of computer integrated machine |
| CN103425561A (en) * | 2012-05-25 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | VGA interface test device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201237888Y (en) * | 2008-08-07 | 2009-05-13 | 深圳市神舟电脑股份有限公司 | Interface circuit for implementing VGA input/output function of computer integrated machine |
| CN103425561A (en) * | 2012-05-25 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | VGA interface test device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107293270A (en) * | 2016-04-05 | 2017-10-24 | 深圳市亿威尔信息技术股份有限公司 | The sustainable display system normally shown of VGA signals |
| CN116609706A (en) * | 2023-07-19 | 2023-08-18 | 北京同方艾威康科技有限公司 | VGA image quality nondestructive disconnection detection method |
| CN116609706B (en) * | 2023-07-19 | 2023-09-19 | 北京同方艾威康科技有限公司 | VGA image quality nondestructive disconnection detection method |
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