CN104242990B

CN104242990B - power line carrier communication chip

Info

Publication number: CN104242990B
Application number: CN201310254111.0A
Authority: CN
Inventors: 金江晓; 潘松; 沈力为; 陈光胜
Original assignee: Shanghai Eastsoft Microelectronics Co Ltd
Current assignee: Shanghai Eastsoft Microelectronics Co Ltd
Priority date: 2013-06-24
Filing date: 2013-06-24
Publication date: 2016-05-18
Anticipated expiration: 2033-06-24
Also published as: CN104242990A

Abstract

The invention provides a kind of power line carrier communication chip, comprise MCU, control module, OFDM processing module and AFE; Between MCU and OFDM processing module, be provided with first memory, between OFDM processing module and AFE, be provided with second memory; MCU, for being sent to first memory by transmission data; Control module is used for controlling OFDM processing module and obtains transmission data from first memory, also for controlling the transmission data of AFE from second memory obtains modulation treatment; OFDM processing module, for obtain transmission data from first memory, and carries out being sent to second memory after modulation treatment to sending data; AFE, for the transmission data from second memory obtains modulation treatment, and carries out being sent to the coupling circuit being connected with power line carrier communication chip after digital-to-analogue conversion to modulating transmission data after treatment. The invention solves the low problem of power line carrier communication chip data processing speed in prior art.

Description

Power line carrier communication chip

Technical field

The present invention relates to the communication technology, relate in particular to a kind of power line carrier communication chip.

Background technology

For meet intelligent grid construction to power line carrier communication at reliability, real-time, transfer rate, channel self-adaptingThe higher requirements in aspect such as property, OFDM (OrthogonalFrequencyDivisionMultiplexing, withLower abbreviation OFDM) technology is as current state-of-the-art physical layer frequency multiplexing technique,, under noisy channels environment, possesses solely with itSpecial performance advantage, has become the mainstream technology of power line carrier communication of new generation, according to the difference of application by special OFDMThe application system that modulation /demodulation module composition is special, with microprocessor (MicroControllerUnit, hereinafter to be referred as MCU),Data storage and analog front-end module cooperatively interacted and power line between communicate by letter.

In prior art, power line carrier communication integrated chip MCU, OFDM carrier communication module and AFE(analog front end)(AnalogFrontEnd, hereinafter to be referred as AFE), MCU is stored in the data of transmission in the memory of system, carries through OFDMWave communication module is sent to power line by AFE after transmission data are processed; Or receive from power line by AFEData, OFDM carrier communication module is stored in intrasystem memory after treatment to the data that receive, and MCU is from systemIn interior memory, obtain reception data after treatment.

But in prior art, it is low that power line carrier communication chip reads or store data efficiency from system storage,And can only after frame data are finished dealing with, just can carry out the processing of next frame data, cause power line carrier communication chipData processing speed, efficiency of transmission and hardware resource utilization are low.

Summary of the invention

The invention provides a kind of power line carrier communication chip, for solving prior art power line carrier communication chipFrom system storage, read or store low the asking of data processing speed, data transmission efficiency and hardware resource utilization causingTopic.

The invention provides a kind of power line carrier communication chip, comprising: Micro-processor MCV, control module, orthogonal frequency division multiplexingWith OFDM processing module, AFE(analog front end) AFE; Between described MCU and described OFDM processing module, be provided with first memory, described inBetween OFDM processing module and described AFE, be provided with second memory;

Described MCU, for being sent to described first memory by transmission data; Described in described control module is used for controllingOFDM processing module is obtained described transmission data from described first memory, also deposits from described second for controlling described AFEIn reservoir, obtain the transmission data after described OFDM processing module modulation treatment; Described OFDM processing module, in instituteState under the control of control module, from described first memory, obtain described transmission data, also for described transmission data are enteredAfter row modulation treatment, be sent to described second memory; Described AFE, under the control of described control module, from describedIn two memories, obtain the transmission data after described OFDM processing module modulation treatment, also for to through described OFDM placeTransmission data after reason module modulation treatment are carried out being sent to after digital-to-analogue conversion and are connected with described power line carrier communication chipCoupling circuit;

Or,

Described AFE, under the control of described control module, reception is connected with described power line carrier communication chipThe reception data that described coupling circuit sends, carry out being sent to described second memory after analog-to-digital conversion to described reception data;Described control module, obtains through described AFE modulus and turns from described second memory for controlling described OFDM processing moduleReception data after changing, and enable described MCU and from described first memory, obtain through described OFDM processing module solution and mediateReception data after reason; Described OFDM processing module, under the control of described control module, from described second memoryObtain the reception data after described AFE analog-to-digital conversion, the reception data after described AFE analog-to-digital conversion are carried out to demodulationAfter processing, be sent to described first memory; Described MCU, under the control of described control module, from described the first storageIn device, obtain the reception data after the demodulation of described OFDM processing module.

Further, described OFDM processing module comprises: coding module, modulation module, inverse fast Fourier transform IFFTModule and add Cyclic Prefix windowing module;

Described coding module under the control of described control module, obtains described sending out from described first memorySend data, after described transmission data are encoded, be sent to described modulation module; Described modulation module, in described controlUnder the control of module, after being modulated, the transmission data after coding are sent to described IFFT module; Described IFFT module, forUnder the control of described control module, described in the transmission data after modulation are carried out being sent to after IFFT computing, add Cyclic Prefix and addWindow module; The described Cyclic Prefix windowing module that adds, under the control of described control module, to the transmission number after IFFT computingAfter adding Cyclic Prefix and windowing, be sent to described second memory.

Further, coding module, modulation module, the IFFT module that described OFDM processing module comprises and adding before circulationSew in windowing module, between the first module that at least one pair of is adjacent and the second module, be provided with the 3rd memory;

Described the first module, under the control of described control module, by the transmission through described the first resume moduleData are sent to described the 3rd memory;

Described the second module under the control of described control module, is obtained through institute from described the 3rd memoryState the transmission data of the first resume module.

Further, between described coding module and described modulation module, be provided with the 4th memory; Described modulation module andBetween described IFFT module, be provided with the 5th memory; Described IFFT module and described in add between Cyclic Prefix windowing module and be provided withSix memories;

Described coding module under the control of described control module, obtains described sending out from described first memorySend data, and the transmission data after coding are sent to described the 4th memory; Described modulation module, at described control mouldUnder the control of piece, from described the 4th memory, obtain the transmission data after coding, and the transmission data after modulation are sent toDescribed the 5th memory; Described IFFT module, under the control of described control module, obtains the tune of the 5th memory storesTransmission data after system, and the transmission data after IFFT computing are sent to described the 6th memory; The described Cyclic Prefix that adds addsWindow module under the control of described control module, is obtained the transmission data after IFFT computing from described the 6th memory,And the transmission data that add after Cyclic Prefix and windowing are sent to described second memory.

Transmission data-mapping after the modulation of storing in described the 5th memory further, is to described the 6th memoryIn; Described IFFT module under the control of described control module, is obtained the transmission after modulation from described the 6th memoryData.

Further, described OFDM processing module comprises: go Cyclic Prefix to move window module, Fast Fourier Transform (FFT) FFT mouldPiece, demodulation module and decoding module;

The described Cyclic Prefix that goes moves window module, under the control of described control module, from second memory, obtainsReceive data, after described reception data are removed Cyclic Prefix and moved window, be sent to described FFT module; Described FFT module, usesUnder the control in described control module, the reception data of removing Cyclic Prefix and move after window are carried out being sent to institute after FFT computingState demodulation module; Described demodulation module, under the control of described control module, to the reception data after described FFT computingCarry out being sent to described decoding module after demodulation; Described decoding module, under the control of described control module, to described solutionReception data after tune carry out being sent to described first memory after decoding.

Cyclic Prefix moves window module that what further, described OFDM processing module comprised go, FFT module, demodulation module withAnd in decoding module, between the 3rd module that at least one pair of is adjacent and four module, be provided with the 3rd memory;

Described the 3rd module, under the control of described control module, by the reception through described the 3rd resume moduleData are sent to described the 3rd memory;

Described four module under the control of described control module, obtains through institute from described the 3rd memoryState the reception data of the 3rd resume module.

Further, described in go Cyclic Prefix to move between window module and described FFT module to be provided with the 5th memory, andFive memories are also between described demodulation module and described FFT module; Between described demodulation module and described decoding module, establishThere is the 4th memory;

The described Cyclic Prefix that goes moves window module, under the control of described control module, from described second memoryObtain reception data, and the reception data of removing Cyclic Prefix and move after window are sent to described the 5th memory; Described FFT mouldPiece under the control of described control module, obtains Cyclic Prefix and moves the reception after window from described the 5th memoryData, and the reception data after FFT computing are sent in described the 5th memory; Described demodulation module, in described controlUnder the control of molding piece, obtain the reception data after the FFT computing of the 5th memory stores, and the reception data after demodulation are sent outDeliver in described the 4th memory; Described decoding module, under the control of described control module, from described the 4th memoryIn obtain the reception data after demodulation, and the reception data after decoding are sent in described first memory.

Further, described OFDM processing module also comprises: channel estimation module, described channel estimation module is for rightReception data after FFT computing are carried out channel estimating computing, and assessment operation values is sent to described demodulation module.

Further, between described channel estimation module and described demodulation module, be provided with the 6th memory, and the 5th depositsReservoir is also between FFT module and described channel estimation module;

Described channel estimation module under the control of described control module, is obtained FFT from described the 5th memoryReception data after computing, and channel estimating operation values is sent in described the 6th memory.

Power line carrier communication chip provided by the invention, transmitting terminal is stored to first by MCU by the first transmission dataIn memory, from first memory, obtain the first transmission data by OFDM processing module and carry out being sent to second after modulation treatmentAfter memory, MCU sends second and sends data in first memory, and AFE obtains the first transmission number from second memoryAccording to after processing and when sending the first transmission data, OFDM processing module is processed second and is sent data, and receiving terminal is logical equallyWhen crossing MCU and obtain the first reception data, OFDM processes second and receives data, by adopting the data processing of this streamlineMode, has improved efficiency of transmission, data processing speed and the hardware resource utilization of OFDM power line carrier communication chip data.

Brief description of the drawings

Fig. 1 is the structural representation of a kind of power line carrier communication chip embodiment mono-provided by the invention;

Fig. 2 is the structural representation of a kind of power line carrier communication chip embodiment bis-provided by the invention;

Fig. 3 A is the structural representation of a kind of power line carrier communication chip embodiment tri-provided by the invention;

Fig. 3 B is the structural representation of a kind of power line carrier communication chip embodiment tetra-provided by the invention;

Fig. 3 C is the structural representation of a kind of power line carrier communication chip embodiment five provided by the invention;

Fig. 3 D is the structural representation of a kind of power line carrier communication chip embodiment six provided by the invention;

Fig. 3 E is the structural representation of a kind of power line carrier communication chip embodiment seven provided by the invention;

Fig. 3 F is the structural representation of a kind of power line carrier communication chip embodiment eight provided by the invention;

Fig. 4 is the structural representation of a kind of power line carrier communication chip embodiment nine provided by the invention;

Fig. 5 is the structural representation of a kind of power line carrier communication chip embodiment ten provided by the invention;

Fig. 6 A is the structural representation of a kind of power line carrier communication chip embodiment 11 provided by the invention;

Fig. 6 B is the structural representation of a kind of power line carrier communication chip embodiment 12 provided by the invention;

Fig. 6 C is the structural representation of a kind of power line carrier communication chip embodiment 13 provided by the invention;

Fig. 6 D is the structural representation of a kind of power line carrier communication chip embodiment 14 provided by the invention;

Fig. 6 E is the structural representation of a kind of power line carrier communication chip embodiment 15 provided by the invention;

Fig. 6 F is the structural representation of a kind of power line carrier communication chip embodiment 16 provided by the invention;

Fig. 7 is the structural representation of a kind of power line carrier communication chip embodiment 17 provided by the invention.

Reference numeral:

10: microprocessor; 20:OFDM processing module; 30: control module;

40:AFE; 101: first memory; 102: second memory;

104: the four memories; 105: the five memories; 106: the six memories;

201: coding module; 202: modulation module; 203:IFFT module;

204: add Cyclic Prefix windowing module; 301: decoding module; 302: demodulation module;

303:FFT module; 304: go Cyclic Prefix to move window module; 305: channel estimation module;

50: the three memories; 501: memory A; 502: memory B.

Detailed description of the invention

Fig. 1 is the structural representation of a kind of power line carrier communication chip embodiment mono-provided by the invention; As Fig. 1 instituteShow, this power line carrier communication chip comprises: MCU10, control module 30, OFDM processing module 20 and AFE40; DescribedBetween MCU10 and described OFDM processing module 20, be provided with first memory 101, described OFDM processing module 20 and described AFE40Between be provided with second memory 102; Described MCU10, for being sent to transmission data described first memory 101; Described controlMolding piece 30 obtains described transmission data for controlling described OFDM processing module 20 from described first memory 101, also usesIn controlling described AFE40 from obtaining sending out after described OFDM processing module 20 modulation treatment described second memory 102Send data; Described OFDM processing module 20, for obtaining from described first memory 101 under the control in described control module 30Get described transmission data, also after modulation treatment, be sent to described second memory 102 for described transmission data are carried out; DescribedAFE40, for obtaining through described OFDM and process mould from described second memory 102 under the control in described control module 30Transmission data after piece 20 modulation treatment, also for entering the transmission data after described OFDM processing module 20 modulation treatmentAfter row digital-to-analogue conversion, be sent to the coupling circuit being connected with described power line carrier communication chip; Or, described AFE40, forUnder the control of described control module 30, receive the reception of the coupling circuit transmission being connected with described power line carrier communication chipData, carry out being sent to described second memory 102 after analog-to-digital conversion to described reception data; Described control module 30, forControl described OFDM processing module 20 from obtaining the reception number after described AFE40 analog-to-digital conversion described second memoryAccording to, and enable described MCU10 from obtaining described first memory 101 after described OFDM processing module 20 demodulation processReceive data; Described OFDM processing module 20, under the control in described control module 30 from described second memory 102Obtain the reception data after described AFE40 analog-to-digital conversion, the reception data after described AFE40 analog-to-digital conversion are carried outAfter demodulation process, be sent to described first memory 101; Described MCU10, under the control in described control module 30 from instituteState and in first memory 101, obtain the reception data after described OFDM processing module 20 demodulation.

In the embodiment of the present invention, power line carrier communication chip is except integrated AFE40, and MCU10 and OFDM process mouldOutside piece 20, control module 30, also integrated first memory 101 and second memory 102, can realize by chip internal controlFrom the memory of chip internal, obtain data, wherein, the present invention does not limit the performance height of MCU10, preferred, canSelect 32 low-power consumption high speed MCU 10, and the coupling circuit being connected with above-mentioned power line carrier communication chip can be oneComplete circuit can be also a power line carrier communication chip.

Concrete, in the embodiment shown in fig. 1, send in the process of data MCU10 at power line carrier communication chipThese transmission data are sent to first memory 101; Control module 30 enables to control OFDM processing module 20 from first memoryIn 101, obtain transmission data and carry out modulation treatment, the transmission data here can be regarded as the transmission number that MCU10 sends for the first timeAccording to, first sending data, the modulation treatment is here the concept of a summary, can comprise: in coding, modulation, quick FuThe processing procedures such as leaf inverse transformation (InverseFastFourierTransform, hereinafter to be referred as IFFT) computing; OFDM processesModule 20 is stored to above-mentioned second memory by the transmission data after modulation treatment after transmission Data Modulation is finished dealing withIn 102, now, control module 30 detects that 20 modulation of OFDM processing module finish, and illustrate the transmission in first memory 101Data are read sky by OFDM processing module 20, and control module 30 enables to control MCU10 transmission second and sends data to firstMemory 101, directly carries out modulation treatment by OFDM processing module 20, meanwhile, above-mentioned control module 30 enable AFE40 fromIn second memory 102, obtain first after modulation treatment and send data, and the transmission of first after modulation treatment data are carried outAfter digital-to-analogue conversion, send in the coupling circuit being connected with above-mentioned power line carrier communication chip, that is to say that AFE40 exchangesAfter system first sends digital-to-analogue conversion processing transmission and modulation place of OFDM processing module 20 to the second transmission data of dataReason is synchronously carried out.

Further, receive in the process of data at power line carrier communication chip, in the embodiment mono-shown in Fig. 1,Control module 30 enables to control AFE40 and receives the reception data that the coupling circuit that is connected with power line carrier communication chip sends,The reception data here can be regarded as the reception data that AFE40 receives for the first time, first receive data, and this reception numberAccording to being the carrier signal being coupled through overcoupled circuits, and AFE receives in all embodiment below from carrying with power lineThe reception data that the coupling circuit that wave communication chip connects sends are all the carrier signals that were coupled through overcoupled circuits; AFE40The first reception data are carried out being sent to second memory 102 after analog-to-digital conversion, and this second memory 102 adopts ping-pong structure,Be divided into left-half and right half part, the first reception data that left-half storage AFE40 sends, right half part storageThe second reception data that AFE40 sends, guarantee that AFE40 receives and sends to the data of second memory can not lose from power lineLose; When left-half is write completely by AFE40 after, control module 30 enables to control OFDM processing module 20 from second memory 102Obtain the reception of first after analog-to-digital conversion data and carry out demodulation process, it should be noted that the not merely only bag of demodulation hereContaining demodulating process, also comprise decoding, move window, Fast Fourier Transform (FFT) (FastFourierTransform, hereinafter to be referred as FFT)The processes such as computing, just transfer to summarize these processing procedures by solution here, and OFDM processing module 20 is by the after demodulation processOne receives data is sent in first memory 101, and the demodulation process that module 30 to be controlled detects OFDM processing module 20Through finishing, illustrate that first in second memory 102 receives data and read sky, control module 30 enables OFDM and processes mouldPiece 20 obtains the second reception data and carries out demodulation from second memory 102, simultaneously control module 30 also enable to control MCU10 fromIn first memory, 101 the first reception data of obtaining after demodulation process, that is to say that MCU10 is from first memory 101Obtain the process of the first reception data and OFDM processing module 20 obtains the second reception data and separates from second memory 102The process of adjusting is synchronously carried out.

Power line carrier communication chip provided by the invention, transmitting terminal is stored to first by MCU by the first transmission dataIn memory, from first memory, obtain the first transmission data by OFDM processing module and carry out being sent to second after modulation treatmentAfter memory, MCU sends second and sends data in first memory, and AFE obtains the first transmission number from second memoryAccording to after processing and when sending the first transmission data, OFDM processing module is processed second and is sent data, and receiving terminal is logical equallyWhen crossing MCU and obtain the first reception data, OFDM processing module is processed second and is received data, has improved OFDM power line carrierEfficiency of transmission, data processing speed and the hardware resource utilization of communication chip data.

Fig. 2 is the structural representation of a kind of power line carrier communication chip embodiment bis-provided by the invention, as Fig. 2 instituteShow, on the basis of above-described embodiment one, described OFDM processing module 20 comprises: coding module 201, modulation module 202, IFFTModule 203 and add Cyclic Prefix windowing module 204; Described coding module 201, under the control in described control module 30From described first memory 101, obtain described transmission data, after described transmission data are encoded, be sent to described modulationModule 202; Described modulation module 202, for adjusting the transmission data after coding under the control in described control module 30After system, be sent to described IFFT module 203; Described IFFT module 203, under the control in described control module 30 to modulationAfter transmission data add Cyclic Prefix windowing module 204 described in carrying out being sent to after IFFT computing; Describedly add Cyclic Prefix windowingModule 204, for adding Cyclic Prefix and add the transmission data after IFFT computing under the control in described control module 30After window, be sent to described second memory 102.

Concrete, send in the process of data at power line carrier communication chip, MCU10 is sent to the by these transmission dataOne memory 101; Control module 30 enables control coding module 201 and from first memory 101, obtains transmission data, hereSend data and can be regarded as the transmission data that MCU10 sends for the first time, first send data, coding module 201 is being controlledUnder the control of module 30, the first transmission data are encoded after processing, first after coding sent to data and be sent to modulation mouldPiece 202, module 30 to be controlled detects that the coding processing of coding module 201 finishes, and illustrates first in first memory 101Send the data module 201 that has been encoded to read sky, control module 30 enables to control MCU10 and sends second and send data to first and depositIn reservoir 101, wait to be encoded and follow-up processing, simultaneously control module 30 also enables modulation module 202 the after to codingOne data are carried out after modulation treatment, first after modulation sent to data and be sent to above-mentioned IFFT module 203; IFFT module 20330 times the first data after modulation are carried out to IFFT computing in control module, and first after IFFT computing sent to data transmissionTo the above-mentioned Cyclic Prefix windowing module 204 that adds; Add Cyclic Prefix windowing module 204 transports IFFT under the control of control module 30After calculation first sends data and adds Cyclic Prefix and windowing process, and by first that adds after Cyclic Prefix and windowing processSend data to be sent in above-mentioned second memory 102; Module 30 to be controlled detects that adding Cyclic Prefix windowing module 204 processes knotShu Hou, control module 30 enables control coding module 201 and from first memory 101, obtains the second transmission data and compileCode, modulation module 202 to second sending that data are modulated after encoding, IFFT module 203 is to second sending data and enter after modulatingRow IFFT computing and add Cyclic Prefix windowing module 204 IFFT processed after second send data and add Cyclic Prefix and addingWindow processing, and simultaneously, control module 30 also enables AFE40 and from second memory 102, obtains and add Cyclic Prefix and windowingAfter reason first sends data and carries out digital-to-analogue conversion, and the transmission of first after digital-to-analogue conversion data are sent to and power line carrierThe coupling circuit that communication chip connects, that is to say that AFE40 obtains from second memory 102 and adds Cyclic Prefix and windowing processAfter first send data and carry out digital-to-analogue conversion the process sending and coding module 201, modulation module 202, IFFT module 203And add the process that Cyclic Prefix windowing module 204 carries out respective handling to the second transmission data and synchronously carry out.

The power line carrier communication chip that the present embodiment provides, is stored to the first storage by MCU by the first transmission dataIn device, from first memory, obtain the first transmission data by OFDM processing module and carry out being sent to the second storage after modulation treatmentAfter device, MCU sends second and sends data in first memory, and AFE obtains the first transmission data from second memoryAfter reason and when sending the first transmission data, OFDM processing module is processed second and is sent data, has improved OFDM power line and has carriedEfficiency of transmission, data processing speed and the hardware resource utilization of wave communication chip data.

Further, on the basis of above-described embodiment, Fig. 3 A is a kind of power line carrier communication core provided by the inventionThe structural representation of sheet embodiment tri-, Fig. 3 B is the structure of a kind of power line carrier communication chip embodiment tetra-provided by the inventionSchematic diagram, Fig. 3 C is the structural representation of a kind of power line carrier communication chip embodiment five provided by the invention, Fig. 3 D is thisThe structural representation of a kind of power line carrier communication chip embodiment six that invention provides, Fig. 3 E is a kind of electricity provided by the inventionThe structural representation of powerline carrier communication chip embodiment seven, Fig. 3 F is a kind of power line carrier communication chip provided by the inventionThe structural representation of embodiment eight; Coding module 201 that wherein, described OFDM processing module 20 comprises, modulation module 202,IFFT module 203 and adding in Cyclic Prefix windowing module 204, establishes between the first module that at least one pair of is adjacent and the second moduleBe equipped with the 3rd memory 50; Described the first module, under controlling in described control module 30, by through the first resume moduleSend data and be sent to described the 3rd memory 50; Described the second module, under the control in described control module 30, from instituteState and in the 3rd memory 50, obtain the transmission data through described the first resume module.

Concrete, on the basis of above-described embodiment, between the first module that at least one pair of is adjacent and the second module, arrangeThere is the 3rd memory 50, can have following several implementation:

(1) between a pair of the first adjacent module and the second module, be provided with the 3rd memory 50, the 3rd memory 50 canWith between coding module 201 and modulation module 202, also can be between modulation module 202 and IFFT module 203, alsoCan and add between Cyclic Prefix windowing module 204 in IFFT module 203, that is to say at power line carrier communication data placeIn reason flow process, can there be three memories: first memory 101, second memory 102, the 3rd memory 50.

Wherein, as shown in Figure 3A, the 3rd memory 50 is between coding module 201 and modulation module 202 time, MCU10These transmission data are sent to first memory 101; Control module 30 enables control coding module 201 from first memory 101In obtain transmission data, the transmission data here can be regarded as the transmission data that MCU10 sends for the first time, first send numberAccording to, coding module 201 is encoded after processing to the first transmission data under the control of control module 30, by first after codingSend data and be sent to the 3rd memory 50; Module 30 to be controlled detects that the coding processing of coding module 201 finishes, and illustratesIn one memory 101 first sends the data module 201 that has been encoded and reads sky, and control module 30 enables to control MCU10 and sends outSend second to send data in first memory 101, wait to be encoded and follow-up processing, and enable modulation module 202 fromIn three memories 50, obtaining the transmission of first after coding data modulates.

Modulation module 202 sends data by first after modulation and is sent to IFFT computing module 203, by IFFT computing module203 carry out after IFFT computing, the first transmission data being sent to and adding Cyclic Prefix windowing module 204, add Cyclic Prefix windowing moduleAfter 204 pairs of IFFT computings first send data and add and the first transmission data are sent to after Cyclic Prefix and windowing process to theIn two memories 102; Meanwhile, module 30 to be controlled detects that the modulation treatment of modulation module 202 finishes, and illustratesAfter the coding that three memories 50 are stored first transmission data modulated module 202 are read sky, and control module 30 enables to compileCode module 201 is obtained the second transmission data and is encoded from first memory 101, and the second transmission data after coding are sent outDeliver to the 3rd memory 50; Control module 30 enables modulation module 202 the second transmission data after encoding is modulated, andNow control module 30 also enables MCU10 transmission the 3rd and sends data to first memory 101; In fact that is to say firstSend data modulation, IFFT computing, add Cyclic Prefix and windowing process process and MCU10 the second transmission data be sent to theOne memory synchronously carries out, and AFE40 obtains and adds after Cyclic Prefix and windowing process from second memory 102One sends data carries out digital-to-analogue conversion and sends to the processing procedure and second of opposite end coupling circuit to send the coding processing of dataProcess is also synchronously carried out.

As shown in Figure 3 B, the situation of the 3rd memory 50 between modulation module 202 and IFFT module 203, process andEmbodiment is above similar, and these transmission data are sent to first memory 101 by MCU10; Control module 30 enables control codingModule 201 is obtained the first transmission data from first memory 101, coding module 201 under the control of control module 30 toOne sends data encodes after processing, first after coding is sent to data and be sent to modulation module 202, modulation module 202Under the control of control module 30, the first data after coding are carried out after modulation treatment, first after modulation sent to data and send outDeliver to the 3rd memory 50; Module 30 to be controlled detects when the coding computing of coding module 201 finishes, first memory is describedData in 101 have been read sky, enable MCU10 and send and second send data to first memory 101, wait to be encoded and afterContinuous processing, also enables the first data that IFFT module 203 obtains after modulation from the 3rd memory 50 simultaneously and carries out IFFT fortuneCalculate, and first after IFFT computing sent to data be sent to and add Cyclic Prefix windowing module 204 and add Cyclic Prefix and addingWindow is sent to second memory 102 after processing; In the time that control module 30 detects that the IFFT computing of IFFT module 203 finishes, sayAfter the modulation of the storage in bright the 3rd memory 50 first sends data and read sky, and control module 30 enables coding module201 obtain the computing of encoding of the second transmission data from first memory 101, second after coding computing sent to data and send outDeliver to modulation module 202, under the control of control module 30, modulation module 202 sends data to second after encoding and adjustsAfter system, be sent to the 3rd memory 50, wait for IFFT computing and subsequent treatment; And when control module 30 detects coding againWhen the coding computing of module 201 finishes, also enable MCU10 and send and the 3rd send data to first memory 101, with canProcess according to above-mentioned processing procedure; In fact that is to say that the first transmission data carry out IFFT computing, add Cyclic PrefixSend the second process that sends data to first memory 101 with windowing process process and MCU10 and synchronize and carry out, andAFE40 from second memory 102, obtain add first after Cyclic Prefix and windowing process send data carry out digital-to-analogue conversion alsoSend to the processing procedure of opposite end coupling circuit and coding module 201 to encode after computing and send to tune the second transmission dataMolding piece carries out modulated process and also synchronously carries out.

As shown in Figure 3 C, the 3rd memory 50 is in IFFT module 203 and add between Cyclic Prefix windowing module 204,These transmission data are sent to first memory 101 by MCU10; Control module 30 enables control coding module 201 from the first storageIn device 101, obtain the first transmission data, coding module 201 is encoded to the first transmission data under the control of control module 30After processing, first after coding sent to data and be sent to modulation module 202; Modulation module 202 is in the control of control module 30Under to coding after the first data carry out after modulation treatment, by modulation after first send data be sent to IFFT module 203;IFFT module 203 is carried out first after IFFT computing being sent after IFFT computing data to the first transmission data and is stored to the 3rd and depositsReservoir 50; In the time that control module 30 detects that the coding computing of coding module 201 finishes, control module 30 enables MCU10 and sendsSecond sends data to first memory 101, also enables to add Cyclic Prefix windowing module 204 and obtains from the 3rd memory 50 simultaneouslyGet the transmission of first after IFFT computing data and add Cyclic Prefix and windowing process, and the first transmission data after treatment are sent outDeliver in second memory 102; In the time that control module 30 detects that the processing that adds Cyclic Prefix windowing module 204 finishes, explanationIn the 3rd memory 50 after the IFFT computing of memory first sends data and read sky, and control module 30 enables codingModule 201 from obtaining second memory 102, encode by the second transmission data, modulation module 202 to through coding computing afterThe second transmission data are modulated and IFFT module 203 is carried out IFFT computing to sending data through second of modulation treatment,Also enable simultaneously AFE40 from second memory 102, obtain add first after Cyclic Prefix and windowing process send data carry outDigital-to-analogue conversion also sends to the coupling circuit of opposite end; The coding computing that coding module 201 again detected when control module 30 is tiedShu Shi, also enables MCU10 transmission the 3rd and sends data to first memory 101 to carry out above-mentioned identical processing; In fact alsoIn other words, first send data and send data to first and deposit through adding Cyclic Prefix windowing process process and MCU10 transmission secondReservoir 101 processes are synchronous, and first sends process and the second data that the follow-up AFE40 digital-to-analogue conversion of data is processed and sentCoding, modulation, IFFT calculating process synchronously carry out.

Between (2) two pairs of the first adjacent modules and the second module, be respectively equipped with a memory, memory A501 andCan there be three kinds of modes, i.e. the first in the position of memory B502: between coding module 201 and modulation module 202, be provided with oneMemory, is assumed to be memory A501, is provided with a memory between modulation module 202 and IFFT module 203, is assumed to be and depositsReservoir B502; The second: between coding module 201 and modulation module 202, be provided with a memory, be assumed to be memory A501,IFFT module 203 and add between Cyclic Prefix windowing module 204 and be provided with a memory, is assumed to be memory B502; The third:Between modulation module 202 and IFFT module 203, be provided with a memory, be assumed to be memory A501, IFFT module 203 and addingBetween Cyclic Prefix windowing module 204, be provided with a memory, be assumed to be memory B502; That is to say power line carrier communicationIn flow chart of data processing, can there be four memories, be respectively: first memory 101, second memory 102, memory A501And memory B502, specific implementation is:

Be directed to the situation of the first, as shown in Figure 3 D, these transmission data are sent to first memory 101 by MCU10; ControlMolding piece 30 enables control coding module 201 and from first memory 101, obtains transmission data, and the transmission data here can be seenWork is the transmission data that MCU10 sends for the first time, first sends data, and coding module 201 is under the control of control module 30The first transmission data are encoded after processing, first after coding sent to data and be sent to memory A501; Molding to be controlledPiece 30 detects that the coding processing of coding module 201 finishes, and illustrates that first in first memory 101 sends data and compiledCode module 201 is read sky, and control module 30 enables to control MCU10 and sends and second send data in first memory 101, waits forCoding and follow-up processing, and enable modulation module 202 from memory A501, obtain first after coding send data enterRow modulation; Modulation module 202 obtains after the transmission of first after coding data are modulated and is sent to storage from memory A501In device B502; The modulation treatment that modulation module 202 detected when control module 30 finishes, and enables coding module 201 from firstIn memory 101, obtain the processing of encoding of the second transmission data, and second after coding sent to data be sent to memoryIn A501, prepare to carry out modulation treatment, also enable IFFT module 203 simultaneously and from memory B502, obtain first after modulationSend data to carry out IFFT computing, and first after computing sent to data be sent to and add Cyclic Prefix windowing module 204 and addCyclic Prefix and windowing process, and the first transmission data after treatment are sent to second memory 102; When control module 30 is examinedWhen the IFFT computing that measures IFFT module 203 finishes, illustrate that first in memory B502 sends data and read sky, controlMolding piece 30 enable modulation module 202 from memory A501, obtain second after coding send data carry out after modulation treatment,After modulation second sent to data and be sent in memory B502, and enable IFFT module 203 and obtain from memory B502After modulation second sends data and carries out IFFT computing; Meanwhile, control module 30 also enables AFE40 from second memory 102Obtain the coupling circuit that adds first after Cyclic Prefix and windowing process and send data and carry out sending to after digital-to-analogue conversion opposite end, realOn border, that is to say, first sends data in the time modulating, and second sends data waits for and compiling in first memory 101Code is processed, and in the time that the first transmission Data Modulation finishes, second sends data just can directly encode; When control module 30 detectsWhen the IFFT computing of the first transmission data end to IFFT module 203, second sends data just can directly carry out modulation treatment;In the time that the first transmission data are carried out analog-to-digital conversion, the second IFFT computing that sends data, add Cyclic Prefix and windowing process and itsSynchronously carry out, wherein, second memory 102 adopts ping-pong structure, is divided into left-half and right half part, left-halfStorage adds first after Cyclic Prefix and windowing process and sends data, and right half part storage adds after Cyclic Prefix and windowing processSecond sends data, can make AFE40 reading out data continuously from second memory 102.

Be directed to the second situation, as shown in Fig. 3 E, these transmission data are sent to first memory 101 by MCU10; ControlModule 30 enables control coding module 201 and from first memory 101, obtains the first transmission data, and coding module 201 is being controlledUnder the control of module 30, the first transmission data are encoded after processing, first after coding sent to data and be sent to memoryA501; Module 30 to be controlled detects that the coding processing of coding module 201 finishes, and illustrates first in first memory 101Send the data module 201 that has been encoded to read sky, control module 30 enables to control MCU10 and sends second and send data to first and depositIn reservoir 101, wait to be encoded and follow-up processing, and enable modulation module 202 and obtain after coding from memory A501First sends data modulates; Modulation module 202 obtains the transmission of first after coding data and adjusts from memory A501After system, be sent to IFFT module 203, IFFT module 203 sends data to first after modulation and enters under the control of control module 30After row IFFT computing, first after IFFT computing being sent to data is sent in memory B502; When control module 30 detects tuneWhen the modulation treatment of molding piece 202 finishes, enable coding module 201 and from first memory 101, obtain the second transmission data and enterRow coding sends data by second after coding after processing and is sent in memory A501, prepares to carry out modulation treatment, also simultaneouslyEnable to add Cyclic Prefix windowing module 204 from memory B502, obtain first after IFFT computing send data add circulationPrefix and windowing process, and be sent in second memory 102 adding the transmission of first after Cyclic Prefix and windowing process data;When control module 30 detects while adding the adding Cyclic Prefix and windowing process and finish of Cyclic Prefix windowing module 204, enable modulationModule 202 is obtained the transmission of second after coding data and is modulated from memory A501, and second after modulation sent to numberCarry out being sent in memory B502 after IFFT computing according to being sent to IFFT module 203, also enable AFE40 from the second storage simultaneouslyIn device 102, obtain add first after Cyclic Prefix and windowing process and send data and carry out digital-to-analogue conversion after and send to the coupling of opposite endClose circuit; In fact that is to say that the first transmission data are in the time modulating, second sends data at first memory 101Medium processing to be encoded, in the time that the first transmission Data Modulation and IFFT computing finish, second sends data just can directly compileCode; When control module 30 detects that adding Cyclic Prefix windowing process module adds Cyclic Prefix and windowing place to the first transmission dataWhen reason finishes, second sends data just can directly modulate and IFFT computing; In the time that the first transmission data are carried out analog-to-digital conversion,Second send data add Cyclic Prefix and windowing process is synchronizeed and is carried out with it, wherein, second memory 102 adopts rattlesStructure, is divided into left-half and right half part, and left-half storage adds first after Cyclic Prefix and windowing process and sends numberAccording to, right half part storage adds second after Cyclic Prefix and windowing process and sends data, can make AFE40 from second memoryReading out data continuously in 102.

Be directed to the third situation, as shown in Fig. 3 F, these transmission data are sent to first memory 101 by MCU10; ControlModule 30 enables control coding module 201 and from first memory 101, obtains the first transmission data, and coding module 201 is being controlledUnder the control of module 30, the first transmission data are encoded after processing, first after coding sent to data and be sent to modulation mouldPiece 202; Modulation module 202 sends data to first after coding and carries out modulation treatment under the control of control module 30, and willAfter modulation first sends data and is sent to memory A501; When control module 30 detects the coding computing of coding module 201When end, enable MCU10 transmission second and send data to first memory 101, also enable IFFT module 203 from memory simultaneouslyIn A501, obtain the transmission of first after modulation data and carry out IFFT computing, and the transmission of first after IFFT computing data are sent toIn memory B502; In the time that control module 30 detects that the IFFT computing of IFFT module 203 finishes, enable coding module 201 fromIn first memory 101, obtain the processing of encoding of the second transmission data, and second after coding sent to data be sent to tuneMolding piece 202 carries out modulation treatment, and the second transmission data after modulation are sent in memory A501, also enables to add simultaneouslyCyclic Prefix windowing process module is obtained first after IFFT computing and is sent data from memory B502, and will add Cyclic PrefixSending data with first after windowing process is sent in second memory 102; When detecting, control module 30 adds Cyclic PrefixWhile end with windowing process, enable IFFT module 203 from memory A501, obtain second after modulation send data carry outIFFT computing, and the transmission of second after IFFT computing data are sent in memory B502, also enable AFE40 from second simultaneouslyIn memory 102, obtain and add first after Cyclic Prefix and windowing process and send data and carry out being sent to after digital-to-analogue conversion opposite endCoupling circuit, also enables to add Cyclic Prefix windowing process module simultaneously and from memory B502, obtains second after IFFT computingSend data, and be sent in second memory 102 adding the transmission of second after Cyclic Prefix and windowing process data; In fact alsoIn other words, first sends data in the time carrying out IFFT computing, and the second transmission data are medium to be encoded at first memory 101Process; In the time that the first transmission data IFFT computing finishes, second sends data just can directly encode and modulate; When controlling mouldPiece 30 detects while adding Cyclic Prefix windowing process module to the adding Cyclic Prefix and windowing process and finish of the first transmission data,Two send data just can directly carry out IFFT computing; In the time that the first transmission data are carried out analog-to-digital conversion, second sends adding of dataCyclic Prefix and windowing process are synchronizeed and are carried out with it, and wherein, second memory 102 adopts ping-pong structure, are divided into left halfPart and right half part, left-half storage adds first after Cyclic Prefix and windowing process and sends data, right half part storageAdd second after Cyclic Prefix and windowing process and send data, can make AFE40 continuously read from second memory 102Fetch data.

Between (3) three pairs of the first adjacent modules and the second module, be respectively equipped with a memory, i.e. coding module 201 HesBetween modulation module 202, be provided with a memory, between modulation module 202 and IFFT module 203, be provided with a memory, IFFTModule 203 and add and be provided with a memory, namely power line carrier communication data processing between Cyclic Prefix windowing module 204In flow process, there are 5 memories. The following examples nine are specific descriptions that this situation is carried out.

On the basis of above-mentioned Fig. 1 to Fig. 3 F illustrated embodiment, Fig. 4 is a kind of power line carrier communication provided by the inventionThe structural representation of chip embodiment nine, preferred, between described coding module 201 and described modulation module 202, be provided with the 4thMemory 104; Between described modulation module 202 and described IFFT module 203, be provided with the 5th memory 105; Described IFFT module203 and described in add and between Cyclic Prefix windowing module 204, be provided with the 6th memory 106; Described coding module 201, in instituteState under the control of control module 30 and from described first memory 101, obtain described transmission data, and by the transmission number after codingAccording to being sent to described the 4th memory 104; Described modulation module 202, under the control in described control module 30 from describedIn the 4th memory 104, obtain the transmission data after coding, and the transmission data after modulation are sent to described the 5th memory105; Described IFFT module 203, for obtaining under the control in described control module 30 after the modulation that the 5th memory 105 storesTransmission data, and the transmission data after IFFT computing are sent to described the 6th memory 106; Describedly add Cyclic Prefix windowingModule 204, for obtaining the transmission IFFT computing from described the 6th memory 106 under the control in described control module 30Data, and the transmission data that add after Cyclic Prefix and windowing are sent to described second memory 102.

Concrete, 32 low-power consumption MCU10 is at a high speed sent to transmissions data in first memory 101, hereSend data can regard the first transmission data that MCU10 sends as, control module 30 enables coding module 201 and starts to encodeComputing; Coding module 201 obtains the first transmission data and encodes from first memory 101, and by first after codingSend data to be sent in the 4th memory 104; Control module 30 detects that the coding computing of coding module 201 finishes, and saysData in bright first memory 101 have been read sky, enable the data of MCU10 transmission next frame to first memory 101In (the transmission data of the next frame here can be the second transmission data), prepare to carry out the coding processing of the second transmission data,While control module 30 also enables modulation module 202 and starts to carry out modulation operation; After modulation module 202 is enabled, from the 4thIn memory 104, read first after coding and send data and modulate, and first after modulation sent to data be stored to theIn five memories 105; Control module 30 detects that the modulation treatment of modulation module 202 finishes, and the 4th memory 104 is describedIn data read sky, enable coding module 201 and from first memory 101, obtain the second transmission data and encodeProcess, and the second transmission data after coding are sent in the 4th memory 104, wait pending modulation treatment, control simultaneouslyModule 30 also enable IFFT module 203 from the 5th memory 105, obtain first after modulation send data carry out IFFT computing,And the transmission of first after IFFT computing data are sent in the 6th memory 106; Control module 30 detects IFFT module 203IFFT computing finish, illustrate that the data in the 5th memory 105 have been read sky, enable modulation module 202 fromIn four memories 104, obtain the transmission of second after coding data and modulate, and the second transmission data after modulation are sent toIn the 5th memory 105, prepare to carry out the IFFT computing of the second transmission data, also enable to add Cyclic Prefix windowing module simultaneously204 obtain the transmission of first after IFFT computing data from the 6th memory 106 adds Cyclic Prefix and windowing process, and willAdding the transmission of first after Cyclic Prefix and windowing process data is sent in second memory 102; Control module 30 detects and addsCyclic Prefix windowing module 204 add Cyclic Prefix and windowing process finishes, illustrate that data in the 6th memory 106 areThrough being read sky, control module 30 enables IFFT module 203 and from the 5th memory 105, obtains the transmission of second after modulation dataCarry out IFFT computing, and the transmission of second after computing data are sent in the 6th memory 106, control module 30 also makes simultaneouslyCan AFE40 from second memory 102, obtain and add first after Cyclic Prefix and windowing process and send data and carry out digital-to-analogue conversionRear and send to the coupling circuit of opposite end, the coupling that the coupling circuit of this opposite end is namely connected with power line carrier communication chipCircuit, meanwhile, control module 30 also enables to add Cyclic Prefix windowing module 204 and obtains IFFT computing from the 6th memory 106Second send data and be sent to second memory 102 after adding Cyclic Prefix and windowing process.

In fact that is to say, first sends after data encoding finishes, and MCU10 just can send second and send data to theIn one memory 101 and etc. processing to be encoded; In the time that the first transmission Data Modulation computing finishes, second sends data just can enterRow coding is processed; In the time that the first transmission data IFFT computing finishes, second sends data just can directly carry out modulation treatment; Work as controlMolding piece 30 detect add Cyclic Prefix windowing process module to the first transmission data add Cyclic Prefix and windowing process finishesTime, second sends data just can directly carry out IFFT computing; In the time that the first transmission data are carried out analog-to-digital conversion, second sends dataAdd Cyclic Prefix and windowing process is synchronizeed and is carried out with it, wherein, second memory 102 adopts ping-pong structure, is divided intoLeft-half and right half part, left-half storage adds first after Cyclic Prefix and windowing process and sends data, right half partStorage adds second after Cyclic Prefix and windowing process and sends data, can make AFE40 successive from second memory 102Reading out data.

Further, continue with reference to shown in Fig. 4, preferred, the transmission in described the 5th memory 105 after the modulation of storageData-mapping is to described the 6th memory 106; Described IFFT module 203, under the control in described control module 30 fromIn described the 6th memory 106, obtain the transmission data after modulation.

At modulation module 202, first after modulation sent to data and be sent in the 5th memory 105, the 5th memoryFirst after modulation sent data by 105 should be mapped in the 6th memory 106, and object is for convenient IFFT module below203 IFFT computing, afterwards, IFFT module 203 is obtained the transmission of first after mapping data and is carried out from the 6th memory 106IFFT computing, and the transmission of first after IFFT computing data are continued to be stored in the 6th memory 106; Remaining process referring toEmbodiment in embodiment tri-, does not repeat them here; It should be noted that IFFT module 203 and FFT module in the present invention303 can be same module, and the two can be multiplexing, and, in the time receiving data, the effect of this module is to carry out receiving dataFFT computing, in the time sending data, the effect of this module is to carry out IFFT computing to sending data.

The power line carrier communication that the present embodiment provides, by memory is set respectively between adjacent block, to storeData after each resume module, and by the setting of each memory, after making, frame data need not be waited until former frame data placeManaged the rear processing of just carrying out rear frame data, the computing between the modules that OFDM processing module comprises is independent completeBecome, effectively raise the processing speed of chip, also saved the hardware resource of modules.

Fig. 5 is the structural representation of power line carrier communication chip embodiment ten provided by the invention, at above-described embodimentBasis on, described OFDM processing module 20 comprises: go Cyclic Prefix to move window module 304, Fast Fourier Transform (FFT) FFT module303, demodulation module 302 and decoding module 301; The described Cyclic Prefix that goes moves window module 304, in described control module 30Control under from second memory 102, obtain reception data, described reception data are removed Cyclic Prefix and are moved after window and send outDeliver to described FFT module 303; Described FFT module 303, for carrying out FFT fortune to the reception data of removing Cyclic Prefix and move after windowAfter calculation, be sent to described demodulation module 302; Described demodulation module 302, for separating the reception data after described FFT computingAfter tune, be sent to described decoding module 301; Described decoding module 301, carries out decoding for the reception data to after described demodulationAfter be sent to described first memory 101.

Concrete, control module 30 enables to control AFE40 and receives the coupling circuit being connected with power line carrier communication chipThe reception data that send, the reception data here can be regarded as the reception data that AFE40 receives for the first time, first receive numberAccording to, AFE40 carries out being sent to second memory 102 after analog-to-digital conversion to the first reception data; This second memory 102 adopts table tennisPang structure, is divided into left-half and right half part, the first reception data that left-half storage AFE40 sends, right half partThe second reception data that storage AFE40 sends, guarantee that the data of AFE40 transmission can not be lost; When left-half is write full by AFE40After, control module 30 enables to control goes Cyclic Prefix to move window module 304 from second memory 102, to obtain the after analog-to-digital conversionOne receives data removes Cyclic Prefix and moves window processing, and will remove Cyclic Prefix and move window after treatment first to receive data numberAccording to being sent to FFT module 303; Control module 30 detects that Cyclic Prefix moves removing Cyclic Prefix and moving window place of window module 304Reason finishes, and the data that the left-half in second memory 102 is described have been read sky and (gone Cyclic Prefix to move window mouldWhen piece 304 reads the first reception data of second memory 102 left-half, AFE40 still can transmit the second reception dataGive the right half part of second memory 102), control module 30 enables to control FFT module 303 to removing Cyclic Prefix and moving window processingAfter first receive data carry out being sent to demodulation module 302 after FFT computing, demodulation module 302 is in the control of control module 30Under to first after FFT computing receive data carry out being sent to decoding module 301 after demodulation process; Decoding module 301 is being controlledUnder the control of module 30, first after FFT computing received to data and carry out decoding, and first after decoding is received to data transmissionTo first memory 101; Control module 30 detects when the decoding computing of decoding module 301 finishes, enables Cyclic PrefixMove window module 304 and from second memory 102, obtain the second reception data and remove Cyclic Prefix and move window processing, also make simultaneouslyCan from first memory 101, obtain the reception of first after decoding data by MCU10, that is to say the second reception data processAFE40 carries out analog-to-digital conversion and sends to the process of second memory and MCU10 to obtain after decoding from first memory 101The first process that receives data is synchronously carried out; And above-mentioned second memory 102 adopts ping-pong structure, is divided into left sidePoint and right half part, what left-half storage AFE40 sent first receives data, right half part storage adds the of AFE40 transmissionTwo receive data, guarantee that the data of AFE40 transmission can not be lost.

The power line carrier communication chip that the present embodiment provides, receives data by AFE by first after analog-to-digital conversion and sends outDeliver in second memory, from second memory, obtain after the first reception data are processed and be sent to by OFDM processing moduleAfter first memory, AFE sends second after analog-to-digital conversion and receives data to second memory, and MCU is from the first storageWhen obtaining the reception of first after decoding data in device, OFDM processing module is processed second and is sent data, has improved OFDM electricityThe efficiency of transmission of powerline carrier communication chip data and processing speed.

Further, Fig. 6 A is the structural representation of a kind of power line carrier communication chip embodiment 11 provided by the inventionFigure, Fig. 6 B is the structural representation of a kind of power line carrier communication chip embodiment 12 provided by the invention, Fig. 6 C is thisThe structural representation of the bright a kind of power line carrier communication chip embodiment 13 providing, Fig. 6 D is a kind of electricity provided by the inventionThe structural representation of powerline carrier communication chip embodiment 14, Fig. 6 E is a kind of power line carrier communication core provided by the inventionThe structural representation of sheet embodiment 15, Fig. 6 F is a kind of power line carrier communication chip embodiment's 16 provided by the inventionStructural representation; On the basis of above-described embodiment, what described OFDM processing module 20 comprised goes Cyclic Prefix to move window module304, in FFT module 303, demodulation module 302 and decoding module 301, the 3rd module and the four module that at least one pair of is adjacentBetween be provided with the 3rd memory 50; Described the 3rd module, deposits for treated reception data are sent to the described the 3rdReservoir 50; Described four module, under the control in described control module 30, from described the 3rd memory 50, obtain throughThe reception data of described the 3rd resume module.

(1) between a pair of the first adjacent module and the second module, be provided with the 3rd memory 50, the 3rd memory 50 canWith going Cyclic Prefix to move between window module 304 and FFT module 303, also can be positioned at FFT303 module and demodulation module 302Between, can also, between demodulation module 302 modules and decoding module 301, that is to say power line carrier communication data placeIn reason flow process, can there be three memories: first memory 101, second memory 102, the 3rd memory 50.

As shown in Figure 6A, the 3rd memory 50, in the time going Cyclic Prefix to move between window module 304 and FFT module 303, is controlledWhat molding piece 30 enabled that AFE40 receives from power line that opposite end coupling circuit sends first receives data, and to receive theOne receives data carries out analog-to-digital conversion process, and carries out the detection of synchronous head, so that the processing module of rear end can Obtaining AccurateTo the first reception data; After control module 30 detects synchronous head, data are stored in second memory 102, this is second years oldMemory 102 adopts ping-pong structure, is divided into left-half and right half part, and first of left-half storage AFE40 transmission connectsReceive data, the second reception data that right half part storage AFE40 sends, guarantee that the data of AFE40 transmission can not be lost; When a left side halfPart by AFE40 write full after, control module 30 enables to control goes Cyclic Prefix to move window module 304 to read in second memory 102First of left-half receives data and removes Cyclic Prefix and move window processing, and to removing Cyclic Prefix and moving window after treatment theOne receives data carries out data-mapping initialization, and the first reception data after mapping initialization are sent to the 3rd memory50, because second memory 102 is ping-pong structures, so read second memory 102 left sides going Cyclic Prefix to move window module 304When first of half part receives data, AFE40 still can send second after analog-to-digital conversion and receive data to second memoryRight half part in 102, guarantees that data can not lose.

Afterwards, control module 30 enables FFT module 303 and carries out FFT computing, after FFT module 303 is enabled, from the 3rdThe first reception data of obtaining in memory 50 after mapping initializes are carried out FFT computing, and first after FFT computing received to numberAccording to being sent to demodulation module 302; Demodulation module 302 receives data to first after FFT computing under the control of control module 30Carry out being sent to decoding module 301 after demodulation; Decoding module 301 first after absolute demodulation under the control of control module 30 connectsReceive data and carry out decoding, and the reception of first after decoding data are stored in first memory 101; Control module 30 detectsFFT computing in FFT module 303 finishes, and illustrates that the data in the 3rd memory 50 have been read sky, and control module 30 enablesGo Cyclic Prefix move window module 304 from second memory 102, obtain second after analog-to-digital conversion receive data go circulationPrefix and move window processing, and carry out data-mapping and data after treatment are sent in the 3rd memory 50 after initializing, withTime control module 30 also enable MCU10 from first memory 101, read first after decoding receive data, until MCU10 willAfter after decoding in first memory 101 first reception data have read, enable FFT module 303 from the 3rd memory 50In obtain mapping second after initializing and receive data and carry out second after to the FFT computing of FFT computing, demodulation module 302 and receiveData carry out demodulation process and decoding module 301 carries out decoding computing, decoding mould to the reception of second after demodulation process dataPiece 301 receives data by second after decoding and is stored in first memory 101.

As shown in Figure 6B, the 3rd memory 50 is between FFT module 303 and demodulation module 302 time, and control module 30 makesCan receive from power line the first reception data that opposite end coupling circuit sends by AFE40, and receive data to receive firstCarry out analog-to-digital conversion process, and carry out the detection of synchronous head so that the processing module of rear end can Obtaining Accurate to the first receptionData; After control module 30 detects synchronous head, data are stored in second memory 102, this second memory 102 is adoptedWith ping-pong structure, be divided into left-half and right half part, the first reception data that left-half storage AFE40 sends, right halfPart is stored the second reception data that AFE40 sends, and guarantees that the data of AFE40 transmission can not be lost; When left-half is by AFE40Write full after, control module 30 enables to control goes Cyclic Prefix to move window module 304 to read the of left-half in second memory 102One receives data removes Cyclic Prefix and moves window processing, and to removing Cyclic Prefix and moving window the first reception data after treatment and enterRow data-mapping initializes, and the first reception data after mapping initialization are sent to FFT module 303; Control module 30 makesCan FFT module 303 be carried out, after FFT computing, first after FFT computing received to number by the first reception data of shining upon after initializingAccording to being stored in the 3rd memory 50, in the time that control module detects that 303 computings of FFT module finish, enable demodulation module 302 fromIn the 3rd memory 50, obtain the reception of first after FFT computing data and carry out being sent to decoding module 301 after demodulation computing, thenBy decoding module 301, first after demodulation being received to data carries out being sent to first memory 101 after decoding; When control module 30When the demodulation computing that demodulation module 302 detected finishes, control module 30 enables Cyclic Prefix and moves window module 304 and deposit from secondIn reservoir 102, obtain the reception of second after analog-to-digital conversion data and remove Cyclic Prefix and move window processing, and will remove Cyclic PrefixWith move window after treatment second and receive data and be sent to FFT module 303 and carry out being sent to the 3rd memory 50 after FFT computing; WhenControl module 30 detects that, when decoding module 301 computings finish, control module 30 enables MCU10 and obtains from first memory 101Get first after decoding and receive data, read until first after the decoding in first memory 101 is received data by MCU10Afterwards, enable demodulation module 302 from the 3rd memory 50, obtain second after FFT computing receive data carry out demodulation computing.

As shown in Figure 6 C, the 3rd memory 50 is between demodulation module 302 and decoding module 301 time, control module 30Enable AFE40 and receive from power line the first reception data that opposite end coupling circuit sends, and receive number to receive firstAccording to carrying out analog-to-digital conversion process, and carry out the detection of synchronous head, so that the processing module of rear end can connect by Obtaining Accurate to the firstReceive data; After control module 30 detects synchronous head, data are stored in second memory 102 to this second memory 102Adopt ping-pong structure, be divided into left-half and right half part, the first reception data that left-half storage AFE40 sends, the right sideHalf part is stored the second reception data that AFE40 sends, and guarantees that the data of AFE40 transmission can not be lost; When left-half quiltAFE40 write full after, control module 30 enables to control goes Cyclic Prefix to move window module 304 to read left side in second memory 102The first reception data of dividing are removed Cyclic Prefix and are moved window processing, and receive removing Cyclic Prefix and moving window after treatment firstData are carried out data-mapping initialization, and the first reception data after mapping initialization are sent to FFT module 303; Control mouldPiece 30 enables FFT module 303 first after mapping is initialized and receives data and carry out after FFT computing first after FFT computingReceive data and be sent to demodulation module 302; Demodulation module 302 connects first after FFT computing under the control of control module 30Receive data and carry out demodulation, and the reception of first after demodulation data are stored in the 3rd memory 50; When control module detectsWhen demodulation module 302 demodulation computings finish, control module 30 enables decoding module 301 and obtains after demodulation from the 3rd memory 50First receive data and carry out first after decoding being received to data after decoding and be sent in first memory 101; When controlling mouldPiece 30 detects when the decoding processing of decoding module 301 finishes, and illustrates that the data in the 3rd memory 50 are read sky, makesCan go Cyclic Prefix to move window module 304 obtains the second reception data and removes Cyclic Prefix and move window from second memory 102Process, and to removing Cyclic Prefix and moving window the second reception data after treatment and carry out data-mapping initialization, and will shine upon initialAfter change first receives data and is sent to FFT module 303; Control module 30 enables FFT module 303 the after mapping is initializedTwo receive data carries out, after FFT computing, the reception of second after FFT computing data are sent to demodulation module 302; Demodulation module 302Under the control of control module 30, second after FFT computing received to data and carry out demodulation, and second after demodulation received to numberAccording to being stored in the 3rd memory 50; Simultaneously control module 30 enables MCU10 and from first memory 101, obtains the after decodingOne receives data, until MCU10 receives first after the decoding in first memory 101 after data have read, enables to translateCode module 301 is obtained the reception of second after demodulation data and is carried out decoding from the 3rd memory 50, and decoding module 301 is by after decodingSecond receive data be stored in first memory 101.

Between (2) two pairs of the first adjacent modules and the second module, be respectively equipped with a memory, memory A501 andThe position of memory B502 can be by three kinds of modes, i.e. the first: go Cyclic Prefix to move between window module 304 and FFT module 303Be provided with a memory, be assumed to be memory A501, between FFT module 303 and demodulation module 302, be provided with a memory,Be assumed to be memory B502; The second: remove Cyclic Prefix to move to be provided with between window module 304 and FFT module 303 memory,Be assumed to be memory A501, between demodulation module 302 and decoding module 301, be provided with a memory, be assumed to be memory B502;The third: between FFT module 303 and demodulation module 302, be provided with a memory, be assumed to be memory A501; Demodulation module302 and decoding module 301 between be provided with a memory, be assumed to be memory B502; That is to say power line carrier communication numberAccording to there being four memories in handling process, be respectively: first memory 101, second memory 102, memory A501 withAnd memory B502.

For the first situation, as shown in Figure 6 D, control module 30 enables AFE40 and receives opposite end coupling electricity from power lineWhat road sent first receives data, and receives data to receive first and carry out analog-to-digital conversion process, and carries out synchronous headDetect so that the processing module of rear end can Obtaining Accurate to the first reception data; After control module 30 detects synchronous head,Data are stored in second memory 102, and this second memory 102 adopts ping-pong structure, is divided into left-half and right halfPart, the first reception data that left-half storage AFE40 sends, the second reception data that right half part storage AFE40 sends,Guarantee AFE40 send data can not lose; When left-half is write completely by AFE40 after, control module 30 enables to control goes to circulatePrefix is moved window module 304 and is read first of left-half in second memory 102 and receive data and remove Cyclic Prefix and move windowProcess, and to removing Cyclic Prefix and moving window the first reception data after treatment and carry out data-mapping initialization, and will shine upon initialAfter change first receive data be sent to memory A501, because second memory 102 is ping-pong structures, thus go circulation beforeSew and move window module 304 and read first of second memory 102 left-half and receive when data, AFE40 still can send modulusAfter conversion second receives data to the right half part in second memory 102, guarantees that data can not lose.

After control module 30 detects that computing that Cyclic Prefix moves window module 304 finishes, control module 30 enablesFFT module 303 is carried out FFT computing, after FFT module 303 is enabled, obtains mapping the after initializing from memory A501One receives data carries out FFT computing, and the reception of first after FFT computing data are sent in memory B502; When controlling mouldPiece 30 detects when the FFT computing in FFT module 303 finishes, and illustrates that the data in memory A501 are read sky, enablesGo Cyclic Prefix move window module 304 from second memory 102, obtain second after analog-to-digital conversion receive data go circulationPrefix and move window processing, and carry out data-mapping and data after treatment are sent in memory A501 after initializing, prepareCarry out FFT computing, control module 30 also enables demodulation module 302 and from memory B502, obtains first after FFT computing simultaneouslyReceive data and carry out demodulation, demodulation module 302 receives data by first after demodulation and is sent to decoding module 301, by decoding mouldPiece 301 receives data to first after demodulation to carry out being sent in first memory 101 after decoding; When control module 30 detectsAfter the demodulation computing of demodulation module 302 finishes, illustrate that the data in memory B502 have been read sky, control module 30 enablesThe second reception data that FFT module 303 is obtained after mapping initializes from memory A501 are carried out FFT computing, and by after computingSecond receive data be sent in memory B502; The decoding computing that decoding module 301 detected when control module 30 finishesAfter, control module 30 enables MCU10 and from first memory 101, reads first after decoding and receive data, until MCU10 is by theAfter after decoding in one memory 101 first reception data have read, enable demodulation module 302 and obtain from memory B502Get the reception of second after FFT computing data and carry out demodulation.

For the second situation, as shown in Fig. 6 E, control module 30 enables AFE40 and receives opposite end coupling electricity from power lineWhat road sent first receives data, and receives data to receive first and carry out analog-to-digital conversion process, and carries out synchronous headDetect so that the processing module of rear end can Obtaining Accurate to the first reception data; After control module 30 detects synchronous head,Data are stored in second memory 102, and this second memory 102 adopts ping-pong structure, is divided into left-half and right halfPart, the first reception data that left-half storage AFE40 sends, the second reception data that right half part storage AFE40 sends,Guarantee AFE40 send data can not lose; When left-half is write completely by AFE40 after, control module 30 enables to control goes to circulatePrefix is moved window module 304 and is read first of left-half in second memory 102 and receive data and remove Cyclic Prefix and move windowProcess, and to removing Cyclic Prefix and moving window the first reception data after treatment and carry out data-mapping initialization, and will shine upon initialAfter change first receive data be sent to memory A501, because second memory 102 is ping-pong structures, thus go circulation beforeSew and move window module 304 and read first of second memory 102 left-half and receive when data, AFE40 still can send modulusAfter conversion second receives data to the right half part in second memory 102, guarantees that data can not lose.

After control module 30 detects that computing that Cyclic Prefix moves window module 304 finishes, control module 30 enablesFFT module 303 is carried out FFT computing, after FFT module 303 is enabled, obtains mapping the after initializing from memory A501One receives data carries out FFT computing, and the reception of first after FFT computing data are sent to demodulation module 302, demodulation module302 receive data to first after FFT computing under the control of control module 30 carries out demodulation and first after demodulation is receivedData are sent in memory B502; Control module 30 detects when the FFT computing of FFT module 303 finishes, and enables before circulationSew and move window module 304 and from second memory 102, obtain the second reception data and remove Cyclic Prefix and move window processing, and carry outData-mapping is sent to data after treatment in memory A501 after initializing, and control module 30 detects demodulation moduleWhen 302 demodulation computing finishes, enable decoding module 301 from memory B502, obtain first after demodulation receive data carry outAfter decoding, be sent to first memory 101; Control module 30 detects that when the decoding computing of decoding module 301 finishes, explanation is depositedData in reservoir B502 have been read sky, enable FFT module 303 and from memory A501, obtain mapping the after initializingTwo receive data carries out, after FFT computing, the reception of second after FFT computing data are sent to demodulation module 302, demodulation module 302After FFT computing second received to data and carry out being sent in memory B502 after demodulation, control module 30 also enables simultaneouslyMCU10 reads first after decoding and receives data from first memory 101, until MCU10 is by translating in first memory 101After code first receives after data have read, and enables decoding module 301 and from memory B502, obtains second after demodulation and connectReceive data and carry out decoding.

For the third situation, as shown in Fig. 6 F, control module 30 enables AFE40 and receives opposite end coupling electricity from power lineWhat road sent first receives data, and receives data to receive first and carry out analog-to-digital conversion process, and carries out synchronous headDetect so that the processing module of rear end can Obtaining Accurate to the first reception data; After control module 30 detects synchronous head,Data are stored in second memory 102, and this second memory 102 adopts ping-pong structure, is divided into left-half and right halfPart, the first reception data that left-half storage AFE40 sends, the second reception data that right half part storage AFE40 sends,Guarantee AFE40 send data can not lose; When left-half is write completely by AFE40 after, control module 30 enables to control goes to circulatePrefix is moved window module 304 and is read first of left-half in second memory 102 and receive data and remove Cyclic Prefix and move windowProcess, and to removing Cyclic Prefix and moving window the first reception data after treatment and carry out data-mapping initialization, and will shine upon initialAfter change first receives data and is sent to FFT module 303; Control module 30 enables FFT module 303 the after mapping is initializedOne receives data carries out after FFT computing, the reception of first after FFT computing data being stored in memory A501, works as control moduleWhen the 30 FFT computings that FFT module 303 detected finish, enable demodulation module 302 and obtain after FFT computing from memory A501First receive data carry out being sent in memory B502 after demodulation computing; Control module 30 detects demodulation module 302When demodulation computing finishes, illustrate that the data in memory A501 have been read sky, enable Cyclic Prefix move window module 304 fromIn second memory 102, obtain the reception of second after analog-to-digital conversion data and remove Cyclic Prefix and move window processing, and follow goingEncircle prefix and move window the second reception data after treatment and carry out after data-mapping initialization, being sent to FFT module 303, FFT module303 receive data to second after mapping initialization under the control of control module 30 carries out being sent to memory after FFT computingIn A501, control module 30 also enables decoding module 301 and from memory B502, obtains the reception of first after demodulation data simultaneouslyCarry out after decoding, the reception of first after decoding data being sent in first memory 101; Control module 30 detects decoding mouldWhen the decoding computing of piece 301 finishes, illustrate that the data in memory B502 have been read sky, enable demodulation module 302 from depositingIn reservoir A501, obtain the reception of second after FFT computing data and carry out being sent in memory B502 after demodulation, control mould simultaneouslyPiece 30 also enables MCU10 and from first memory 101, reads the reception of first after decoding data, until MCU10 is by the first storageAfter after decoding in device 101 first reception data have read, enable decoding module 301 and obtain demodulation from memory B502After second receive data carry out decoding.

Between (3) three pairs of the first adjacent modules and the second module, be respectively equipped with a memory, go Cyclic Prefix to moveBetween window module 304 modules and FFT module 303, be provided with a memory, and this memory is also arranged on FFT module 303And between demodulation module 302, between demodulation module 302 and decoding module 301, be provided with memory, namely a power line simultaneouslyIn carrier communication flow chart of data processing, there are 5 memories. The following examples 17 are specific descriptions that this situation is carried out.

On the basis of above-described embodiment, Fig. 7 is power line carrier communication chip embodiment's 17 provided by the inventionStructural representation, preferred, described in go Cyclic Prefix to move between window module 304 and described FFT module 303 to be provided with the 5th memory105, and the 5th memory 105 is also between described demodulation module 302 and described FFT module 303; Described demodulation module302 and described decoding module 301 between be provided with the 4th memory 104; The described Cyclic Prefix that goes moves window module 304, in instituteState under the control of control module 30 and obtain reception data from described second memory 102, and will remove Cyclic Prefix and move after windowReception data be sent to described the 5th memory 105; Described FFT module 303, under the control in described control module 30From described the 5th memory 105, obtain Cyclic Prefix and move the reception data after window, and by the reception data after FFT computingBe sent in described the 5th memory 105; Described demodulation module 302, for obtaining under the control in described control module 30Reception data after the FFT computing that five memories 105 are stored, and the reception data after demodulation are sent to described the 4th memoryIn 104; Described decoding module 301, for obtaining solution from described the 4th memory 104 under the control in described control module 30Reception data after tune, and the reception data after decoding are sent in described first memory 101.

Concrete, control module 30 enables AFE40 and receives from power line the first reception number that opposite end coupling circuit sendsAccording to, and the first reception data that receive are carried out to analog-to-digital conversion process, and carry out the detection of synchronous head, so that the processing of rear endModule can Obtaining Accurate to the first reception data; After control module 30 detects synchronous head, data are stored to second and depositIn reservoir 102, this second memory 102 adopts ping-pong structure, is divided into left-half and right half part, left-half storageThe first reception data that AFE40 sends, the second reception data that right half part storage AFE40 sends, guarantee the number that AFE40 sendsAccording to not losing; When left-half write by AFE40 full after, control module 30 enables to control goes Cyclic Prefix to move window module 304 to readGet the first reception data of left-half in second memory 102 and remove Cyclic Prefix and move window processing, and remove Cyclic PrefixWith move window after treatment first receive data carry out data-mapping initialization, and by mapping initialize after first receive data send outDeliver in the 5th memory 105; Because second memory 102 is ping-pong structures, so read going Cyclic Prefix to move window module 304While getting the first reception data of second memory 102 left-half, AFE40 still can send second after analog-to-digital conversion and receiveData are to the right half part in second memory 102, guarantee that data can not lose.

After control module 30 detects that computing that Cyclic Prefix moves window module 304 finishes, control module 30 enablesFFT module 303 is carried out FFT computing, after FFT module 303 is enabled, obtains after mapping initialization from the 5th memory 105First receive data carry out FFT computing, and by first after FFT computing receive data continue to be sent to the 5th memory 105In; Control module 30 enables demodulation module 302 and carries out demodulation process afterwards, and what this demodulation module 302 adopted is relative phase shift keyControl (DifferentialBinaryPhaseShiftKeying is hereinafter to be referred as DBPSK) or four phase relative phase shift keyings(DifferentialQuadraturePhaseShiftKeying, hereinafter to be referred as DQPSK), demodulation module 302 is by demodulationAfter first receive data be stored in the 4th memory 104; The demodulation computing that control module 30 detects demodulation module 302Through finishing, illustrate data in the 5th memory 105 demodulated module 302 read sky, control module 30 enables to circulatePrefix is moved window module 304 and from second memory 102, is obtained the second reception data and remove Cyclic Prefix and move window processing, and willRemove Cyclic Prefix and move after window the second reception data after treatment are shone upon initialization to be stored in the 5th memory 105, whenControl module 30 detects that Cyclic Prefix moves window module 304 when the second reception data processing is finished, and control module 30 makesThe second reception data that energy FFT module 303 is obtained after mapping initializes from the 5th memory 105 are carried out FFT calculation process, andAfter FFT calculation process second received to data and be stored in the 5th memory 105, prepare demodulation process; Control module 30 makesEnergy decoding module 301 obtains the reception of first after demodulation data and carries out decoding processing from the 4th memory 104, and by decoding placeAfter reason first receives data and is stored in first memory 101; The decoding that decoding module 301 detected when control module 30 is transportedCalculate while end, illustrate that the data in the 4th memory 104 have been read sky, control module 30 enables demodulation module 302 from the 5thThe second reception data of obtaining in memory 105 after FFT computing are carried out demodulation process, and second after demodulation process connectReceiving data is stored in the 4th memory 104; Control module 30 enables MCU10 and obtain decoding from first memory 101 simultaneouslyAfter first receive data, until MCU10 receives first after the decoding in first memory 101 after data have read,Enable decoding module 301 from the 4th memory 104, obtain second after demodulation receive data carry out decoding, decoding module 301After decoding second is received to data and be stored in first memory 101, it should be noted that the FFT module 303 in the present inventionWith IFFT module 203 can be same module, the two can be multiplexing, receiving when data, the effect of this module is dockingReceive data and carry out FFT computing, in the time sending data, the effect of this module is to carry out FFT computing to sending data.

Further, on basis embodiment illustrated in fig. 7, preferred, described OFDM processing module 20 also comprises: channelEvaluation module 305, described channel estimation module 305 is carried out channel estimating computing for the reception data to after FFT computing, and willAssessment operation values is sent to described demodulation module 302; Between described channel estimation module 305 and described demodulation module 302, be provided withThe 6th memory 106, and the 5th memory 105 is also between FFT module 303 and described channel estimation module 305; DescribedChannel estimation module 305, for obtaining FFT computing from described the 5th memory 105 under the control in described control module 30After reception data, and channel estimating operation values is sent in described the 6th memory 106.

Concrete, stored the first reception data after FFT computing in the 5th memory 105 after, control mouldPiece 30 enables respectively demodulation module 302 and channel estimation module 305 is obtained after FFT computing from the 5th memory 105First receives data, and channel estimation module 305 is carried out channel estimating to the first reception data after FFT computing, and willChannel estimating value is sent in the 6th memory 106, and demodulation module 302 obtains after FFT computing from the 5th memory 105One receives data, and, from the 6th memory 106, obtain the channel estimating value of the first reception data, and according to channel estimatingValue receives data to get first and carries out demodulation, guarantees the accuracy of data demodulates, and afterwards, demodulation module 302 is by demodulationAfter first receive data be sent in the 4th memory 104.

The power line carrier communication chip that the present embodiment provides, by memory is set respectively between adjacent block, withStore the data after each resume module, and by the setting of each memory, after making, frame data need not be waited until last frame numberAccording to the processing of frame data after just carrying out after finishing dealing with, the computing between the modules that OFDM processing module comprises is onlyStand, effectively raised the processing speed of chip, also saved the hardware resource of modules.

One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be led toCrossing the hardware that programmed instruction is relevant completes. Aforesaid program can be stored in a computer read/write memory medium. This journeyOrder, in the time carrying out, is carried out the step that comprises above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc orThe various media that can be program code stored such as person's CD.

Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; To the greatest extentPipe has been described in detail the present invention with reference to aforementioned each embodiment, and those of ordinary skill in the art is to be understood that: it is complied withThe technical scheme that so can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein enteredRow is equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from various embodiments of the present invention technologyThe scope of scheme.

Claims

1. a power line carrier communication chip, is characterized in that, comprising: Micro-processor MCV, control module, orthogonal frequency division multiplexingWith OFDM processing module and AFE(analog front end) AFE; Between described MCU and described OFDM processing module, be provided with first memory, instituteState between OFDM processing module and described AFE and be provided with second memory;

Described MCU, for being sent to described first memory by transmission data; Described control module is used for controlling described OFDM placeReason module is obtained described transmission data from described first memory, also for controlling described AFE from described second memoryObtain the transmission data after described OFDM processing module modulation treatment; Described OFDM processing module, in described controlUnder the control of module, from described first memory, obtain described transmission data, also for described transmission data are modulatedAfter processing, be sent to described second memory; Described AFE, under the control of described control module, from described the second storageIn device, obtain the transmission data after described OFDM processing module modulation treatment, also for to through described OFDM processing moduleTransmission data after modulation treatment carry out being sent to the coupling electricity being connected with described power line carrier communication chip after digital-to-analogue conversionRoad;

Or,

Described AFE, under the control of described control module, receive be connected with described power line carrier communication chip described inThe reception data that coupling circuit sends, carry out being sent to described second memory after analog-to-digital conversion to described reception data; DescribedControl module, obtains after described AFE analog-to-digital conversion from described second memory for controlling described OFDM processing moduleReception data, and enable described MCU from obtaining described first memory after described OFDM processing module demodulation processReception data; Described OFDM processing module under the control of described control module, is obtained from described second memoryReception data after described AFE analog-to-digital conversion, carry out demodulation process to the reception data after described AFE analog-to-digital conversionAfter be sent to described first memory; Described MCU, under the control of described control module, from described first memoryObtain the reception data after the demodulation of described OFDM processing module.

2. chip according to claim 1, is characterized in that, described OFDM processing module comprises: coding module, modulation mouldPiece, inverse fast Fourier transform IFFT module and add Cyclic Prefix windowing module;

Described coding module under the control of described control module, obtains described transmission number from described first memoryAccording to, after being encoded, described transmission data are sent to described modulation module; Described modulation module, in described control moduleControl under, the transmission data after coding are sent to described IFFT module after modulating; Described IFFT module, in instituteState under the control of control module, described in the transmission data after modulation are carried out being sent to after IFFT computing, add Cyclic Prefix windowing mouldPiece; The described Cyclic Prefix windowing module that adds, under the control of described control module, enters the transmission data after IFFT computingAfter adding Cyclic Prefix and windowing, row is sent to described second memory.

3. chip according to claim 2, is characterized in that, coding module, modulation that described OFDM processing module comprisesModule, IFFT module and add in Cyclic Prefix windowing module, establish between the first module that at least one pair of is adjacent and the second moduleBe equipped with the 3rd memory;

Described the first module, under the control of described control module, by the transmission data through described the first resume moduleBe sent to described the 3rd memory;

Described the second module under the control of described control module, is obtained through described from described the 3rd memoryThe transmission data of one resume module.

4. chip according to claim 2, is characterized in that, is provided with between described coding module and described modulation moduleFour memories; Between described modulation module and described IFFT module, be provided with the 5th memory; Described IFFT module with described in add and followBetween ring prefix windowing module, be provided with the 6th memory;

Described coding module under the control of described control module, obtains described transmission number from described first memoryAccording to, and the transmission data after coding are sent to described the 4th memory; Described modulation module, in described control moduleUnder control, from described the 4th memory, obtain the transmission data after coding, and described in the transmission data after modulation are sent toThe 5th memory; Described IFFT module, under the control of described control module, obtains after the modulation of the 5th memory storesTransmission data, and the transmission data after IFFT computing are sent to described the 6th memory; The described Cyclic Prefix windowing mould that addsPiece under the control of described control module, obtains the transmission data after IFFT computing from described the 6th memory, and willThe transmission data that add after Cyclic Prefix and windowing are sent to described second memory.

5. chip according to claim 4, is characterized in that, the transmission number after the modulation of storing in described the 5th memoryAccording to mapping in described the 6th memory; Described IFFT module, under the control of described control module, deposits from the described the 6thIn reservoir, obtain the transmission data after modulation.

6. chip according to claim 1, is characterized in that, described OFDM processing module comprises: go Cyclic Prefix to move windowModule, Fast Fourier Transform (FFT) FFT module, demodulation module and decoding module;

The described Cyclic Prefix that goes moves window module, under the control of described control module, obtains reception from second memoryData, are sent to described FFT module after described reception data are removed Cyclic Prefix and moved window; Described FFT module, forUnder the control of described control module, the reception data of removing Cyclic Prefix and move after window are carried out being sent to described solution after FFT computingMode transfer piece; Described demodulation module, under the control of described control module, carries out the reception data after described FFT computingAfter demodulation, be sent to described decoding module; Described decoding module, under the control of described control module, after described demodulationReception data carry out being sent to described first memory after decoding.

7. chip according to claim 6, is characterized in that, the Cyclic Prefix that goes that described OFDM processing module comprises moves windowIn module, FFT module, demodulation module and decoding module, between the 3rd module that at least one pair of is adjacent and four module, arrangeThere is the 3rd memory;

Described the 3rd module, under the control of described control module, by the reception data through described the 3rd resume moduleBe sent to described the 3rd memory;

Described four module under the control of described control module, obtains through described from described the 3rd memoryThe reception data of three resume module.

8. chip according to claim 6, is characterized in that, described in go Cyclic Prefix to move window module and described FFT moduleBetween be provided with the 5th memory, and the 5th memory is also between described demodulation module and described FFT module; Described demodulationBetween module and described decoding module, be provided with the 4th memory;

The described Cyclic Prefix that goes moves window module, under the control of described control module, from described second memory, obtainsReceive data, and the reception data of removing Cyclic Prefix and move after window are sent to described the 5th memory; Described FFT module, usesUnder the control in described control module, from described the 5th memory, obtain Cyclic Prefix and move the reception data after window,And the reception data after FFT computing are sent in described the 5th memory; Described demodulation module, in described control moduleControl under, obtain the reception data after the FFT computing of the 5th memory stores, and the reception data after demodulation be sent to instituteState in the 4th memory; Described decoding module under the control of described control module, obtains from described the 4th memoryReception data after demodulation, and the reception data after decoding are sent in described first memory.

9. according to the chip described in claim 6-8 any one, it is characterized in that, described OFDM processing module also comprises: channelEvaluation module, described channel estimation module is used for the reception data after FFT computing to carry out channel estimating computing, and will assess fortuneCalculation value is sent to described demodulation module.

10. chip according to claim 9, is characterized in that, between described channel estimation module and described demodulation moduleBe provided with the 6th memory, and the 5th memory is also between FFT module and described channel estimation module;

Described channel estimation module under the control of described control module, is obtained FFT computing from described the 5th memoryAfter reception data, and channel estimating operation values is sent in described the 6th memory.