CN104242990A

CN104242990A - Power line carrier communication chip

Info

Publication number: CN104242990A
Application number: CN201310254111.0A
Authority: CN
Inventors: 金江晓; 潘松; 沈力为; 陈光胜
Original assignee: Shanghai Hair Group Integated Circuit Co Ltd
Current assignee: Shanghai Hair Group Integated Circuit Co Ltd
Priority date: 2013-06-24
Filing date: 2013-06-24
Publication date: 2014-12-24
Anticipated expiration: 2033-06-24
Also published as: CN104242990B

Abstract

The invention provides a power line carrier communication chip. The power line carrier communication chip comprises an MCU, a control module, an OFDM processing module and an AFE. A first memorizer is arranged between the MCU and the OFDM processing module, and a second memorizer is arranged between the OFDM processing module and the AFE; the MCU is used for sending sent data to the first memorizer; the control module is used for controlling the OFDM processing module to acquire the sent data from the first memorizer and controlling the AFE to acquire the modulated sent data from the second memorizer; the OFDM processing module is used for acquiring the sent data from the first memorizer, modulating the sent data and then sending the modulated sent data to the second memorizer; the AFE is used for acquiring modulated sent data from the second memorizer, carrying out digital-to-analog conversion on the modulated sent data and then sending the modulated sent data to a coupled circuit connected with the power line carrier communication chip. The power line carrier communication chip solves the problem that a power line carrier communication chip in the prior art is low in data processing speed.

Description

Power line carrier communication chip

Technical Field

The invention relates to a communication technology, in particular to a power line carrier communication chip.

Background

In order to meet the higher requirements of the smart grid construction on the power line carrier communication in the aspects of reliability, real-time performance, transmission rate, channel adaptability and the like, an Orthogonal Frequency Division Multiplexing (OFDM) technology is taken as the most advanced physical layer frequency division Multiplexing technology at present, has unique performance advantages in a severe channel environment and becomes the mainstream technology of the new generation of power line carrier communication, a special application system is formed by a special OFDM modulation and demodulation module according to different applications, and the special application system is matched with a microprocessor (Micro Controller Unit, hereinafter referred to as MCU) and a data memory and an analog front end module to complete the communication with a power line.

In the prior art, a power line carrier communication chip integrates an MCU, an OFDM carrier communication module, and an Analog Front End (AFE), where the MCU stores transmitted data in a memory of a system, and the transmitted data is processed by the OFDM carrier communication module and then transmitted to a power line through the AFE; or receiving data from the power line through the AFE, processing the received data by the OFDM carrier communication module, and storing the processed data into a memory in the system, and acquiring the processed received data from the memory in the system by the MCU.

However, in the prior art, the efficiency of reading or storing data from or in the system memory by the plc chip is low, and the next frame of data can be processed only after one frame of data is processed, which results in low data processing speed, transmission efficiency and hardware resource utilization rate of the plc chip.

Disclosure of Invention

The invention provides a power line carrier communication chip, which is used for solving the problems of low data processing speed, low data transmission efficiency and low hardware resource utilization rate caused by reading or storing the power line carrier communication chip from a system memory in the prior art.

The invention provides a power line carrier communication chip, comprising: the system comprises a microprocessor MCU, a control module, an orthogonal frequency division multiplexing OFDM processing module and an analog front end AFE; a first memory is arranged between the MCU and the OFDM processing module, and a second memory is arranged between the OFDM processing module and the AFE;

the MCU is used for transmitting the transmission data to the first memory; the control module is configured to control the OFDM processing module to obtain the transmission data from the first memory, and is further configured to control the AFE to obtain the transmission data modulated and processed by the OFDM processing module from the second memory; the OFDM processing module is configured to acquire the transmission data from the first memory under the control of the control module, and is further configured to perform modulation processing on the transmission data and then transmit the transmission data to the second memory; the AFE is used for acquiring the transmission data modulated and processed by the OFDM processing module from the second memory under the control of the control module, and is also used for performing digital-to-analog conversion on the transmission data modulated and processed by the OFDM processing module and then transmitting the transmission data to a coupling circuit connected with the power line carrier communication chip;

or,

the AFE is used for receiving the receiving data sent by the coupling circuit connected with the power line carrier communication chip under the control of the control module, performing analog-to-digital conversion on the receiving data and sending the receiving data to the second memory; the control module is configured to control the OFDM processing module to acquire the received data after the AFE analog-to-digital conversion from the second memory, and enable the MCU to acquire the received data after the demodulation processing by the OFDM processing module from the first memory; the OFDM processing module is configured to acquire the received data after the AFE analog-to-digital conversion from the second memory under the control of the control module, demodulate the received data after the AFE analog-to-digital conversion, and send the demodulated received data to the first memory; and the MCU is used for acquiring the received data demodulated by the OFDM processing module from the first memory under the control of the control module.

Further, the OFDM processing module includes: the device comprises a coding module, a modulation module, an Inverse Fast Fourier Transform (IFFT) module and a cyclic prefix windowing module;

the coding module is used for acquiring the sending data from the first memory under the control of the control module, coding the sending data and sending the coded sending data to the modulation module; the modulation module is used for modulating the coded sending data and sending the modulated sending data to the IFFT module under the control of the control module; the IFFT module is used for carrying out IFFT operation on the modulated sending data and sending the modulated sending data to the cyclic prefix windowing module under the control of the control module; and the cyclic prefix windowing module is used for performing cyclic prefix and windowing on the sending data subjected to the IFFT operation under the control of the control module and then sending the sending data to the second memory.

Furthermore, in the coding module, the modulation module, the IFFT module and the cyclic prefix windowing module included in the OFDM processing module, a third memory is disposed between at least one pair of adjacent first and second modules;

the first module is used for sending the sending data processed by the first module to the third memory under the control of the control module;

and the second module is used for acquiring the transmission data processed by the first module from the third memory under the control of the control module.

Further, a fourth memory is arranged between the coding module and the modulation module; a fifth memory is arranged between the modulation module and the IFFT module; a sixth memory is arranged between the IFFT module and the cyclic prefix windowing module;

the encoding module is used for acquiring the sending data from the first memory under the control of the control module and sending the encoded sending data to the fourth memory; the modulation module is configured to acquire coded transmission data from the fourth memory under the control of the control module, and send the modulated transmission data to the fifth memory; the IFFT module is configured to acquire modulated transmission data stored in a fifth memory under the control of the control module, and send the transmission data after IFFT operation to the sixth memory; and the cyclic prefix windowing module is used for acquiring the transmission data subjected to the IFFT operation from the sixth memory under the control of the control module and transmitting the transmission data subjected to the cyclic prefix and windowing to the second memory.

Further, the modulated transmission data stored in the fifth memory is mapped into the sixth memory; the IFFT module is configured to obtain the modulated transmission data from the sixth memory under the control of the control module.

Further, the OFDM processing module includes: the device comprises a cyclic prefix removing and window shifting module, a Fast Fourier Transform (FFT) module, a demodulation module and a decoding module;

the cyclic prefix removing and window moving module is used for acquiring received data from a second memory under the control of the control module, removing the cyclic prefix and moving the window of the received data and then sending the received data to the FFT module; the FFT module is used for carrying out FFT operation on the received data after the cyclic prefix and the window shift are removed and then sending the received data to the demodulation module under the control of the control module; the demodulation module is used for demodulating the received data after the FFT operation and then sending the demodulated data to the decoding module under the control of the control module; and the decoding module is used for decoding the demodulated received data and then sending the decoded received data to the first memory under the control of the control module.

Furthermore, in a cyclic prefix window shifting removing module, an FFT module, a demodulation module and a decoding module included in the OFDM processing module, a third memory is disposed between at least one pair of adjacent third and fourth modules;

the third module is used for sending the received data processed by the third module to the third memory under the control of the control module;

and the fourth module is used for acquiring the received data processed by the third module from the third memory under the control of the control module.

Further, a fifth memory is arranged between the cyclic prefix window-shifting module and the FFT module, and the fifth memory is also arranged between the demodulation module and the FFT module; a fourth memory is arranged between the demodulation module and the decoding module;

the cyclic prefix removing and window moving module is configured to obtain received data from the second memory under the control of the control module, and send the received data after cyclic prefix removal and window moving to the fifth memory; the FFT module is configured to obtain received data without cyclic prefix and after window shifting from the fifth memory under the control of the control module, and send the received data after FFT operation to the fifth memory; the demodulation module is used for acquiring the received data after the FFT operation stored in the fifth memory under the control of the control module and sending the demodulated received data to the fourth memory; and the decoding module is used for acquiring the demodulated received data from the fourth memory under the control of the control module and sending the decoded received data to the first memory.

Further, the OFDM processing module further includes: and the channel evaluation module is used for carrying out channel evaluation operation on the received data after the FFT operation and sending an evaluation operation value to the demodulation module.

Further, a sixth memory is arranged between the channel estimation module and the demodulation module, and a fifth memory is also arranged between the FFT module and the channel estimation module;

and the channel estimation module is used for acquiring the received data after the FFT operation from the fifth memory under the control of the control module and sending the channel estimation operation value to the sixth memory.

According to the power line carrier communication chip provided by the invention, the sending end stores first sending data into the first memory through the MCU, the OFDM processing module acquires the first sending data from the first memory, the first sending data is modulated and sent to the second memory, the MCU sends second sending data into the first memory, the AFE acquires the first sending data from the second memory, the first sending data is processed and sent, meanwhile, the OFDM processing module processes the second sending data, the receiving end acquires the first receiving data through the MCU and simultaneously processes the second receiving data through the OFDM, and by adopting the pipeline data processing mode, the transmission efficiency, the data processing speed and the hardware resource utilization rate of the OFDM power line carrier communication chip data are improved.

Drawings

Fig. 1 is a schematic structural diagram of a first embodiment of a power line carrier communication chip according to the present invention;

fig. 2 is a schematic structural diagram of a second embodiment of a power line carrier communication chip according to the present invention;

fig. 3A is a schematic structural diagram of a third embodiment of a power line carrier communication chip provided in the present invention;

fig. 3B is a schematic structural diagram of a fourth embodiment of a power line carrier communication chip according to the present invention;

fig. 3C is a schematic structural diagram of a fifth embodiment of a power line carrier communication chip according to the present invention;

fig. 3D is a schematic structural diagram of a sixth embodiment of a power line carrier communication chip according to the present invention;

fig. 3E is a schematic structural diagram of a seventh embodiment of a power line carrier communication chip provided in the present invention;

fig. 3F is a schematic structural diagram of an eighth embodiment of a power line carrier communication chip provided in the present invention;

fig. 4 is a schematic structural diagram of a ninth embodiment of a power line carrier communication chip according to the present invention;

fig. 5 is a schematic structural diagram of a tenth embodiment of a power line carrier communication chip provided in the present invention;

fig. 6A is a schematic structural diagram of an eleventh embodiment of a power line carrier communication chip according to the present invention;

fig. 6B is a schematic structural diagram of a twelfth embodiment of a power line carrier communication chip according to the present invention;

fig. 6C is a schematic structural diagram of a thirteenth embodiment of a power line carrier communication chip according to the present invention;

fig. 6D is a schematic structural diagram of a fourteenth embodiment of a power line carrier communication chip according to the present invention;

fig. 6E is a schematic structural diagram of a fifteenth embodiment of a power line carrier communication chip provided in the present invention;

fig. 6F is a schematic structural diagram of a sixteenth embodiment of a power line carrier communication chip according to the present invention;

fig. 7 is a schematic structural diagram of a seventeenth embodiment of a power line carrier communication chip provided in the present invention.

Reference numerals:

10: a microprocessor; 20: an OFDM processing module; 30: a control module;

40: an AFE; 101: a first memory; 102: a second memory;

104: a fourth memory; 105: a fifth memory; 106: a sixth memory;

201: an encoding module; 202: a modulation module; 203: an IFFT module;

204: a cyclic prefix windowing module; 301: a decoding module; 302: a demodulation module;

303: an FFT module; 304: a cyclic prefix removal window shifting module; 305: a channel assessment module;

50: a third memory; 501: a memory A; 502: and a memory B.

Detailed Description

Fig. 1 is a schematic structural diagram of a first embodiment of a power line carrier communication chip according to the present invention; as shown in fig. 1, the power line carrier communication chip includes: MCU10, control module 30, OFDM processing module 20, and AFE 40; a first memory 101 is arranged between the MCU10 and the OFDM processing module 20, and a second memory 102 is arranged between the OFDM processing module 20 and the AFE 40; the MCU10, configured to send transmission data to the first memory 101; the control module 30 is configured to control the OFDM processing module 20 to obtain the transmission data from the first memory 101, and is further configured to control the AFE40 to obtain the transmission data modulated by the OFDM processing module 20 from the second memory 102; the OFDM processing module 20 is configured to acquire the transmission data from the first memory 101 under the control of the control module 30, and further configured to perform modulation processing on the transmission data and send the transmission data to the second memory 102; the AFE40 is configured to obtain the transmission data modulated by the OFDM processing module 20 from the second memory 102 under the control of the control module 30, and further configured to perform digital-to-analog conversion on the transmission data modulated by the OFDM processing module 20 and send the transmission data to a coupling circuit connected to the power line carrier communication chip; or, the AFE40 is configured to receive, under the control of the control module 30, reception data sent by a coupling circuit connected to the power line carrier communication chip, perform analog-to-digital conversion on the reception data, and send the reception data to the second memory 102; the control module 30 is configured to control the OFDM processing module 20 to obtain the received data after analog-to-digital conversion by the AFE40 from the second memory, and enable the MCU10 to obtain the received data after demodulation processing by the OFDM processing module 20 from the first memory 101; the OFDM processing module 20 is configured to obtain the received data after analog-to-digital conversion by the AFE40 from the second memory 102 under the control of the control module 30, demodulate the received data after analog-to-digital conversion by the AFE40, and send the demodulated received data to the first memory 101; the MCU10 is configured to, under the control of the control module 30, acquire the received data demodulated by the OFDM processing module 20 from the first memory 101.

In the embodiment of the present invention, the power line carrier communication chip integrates the AFE40, the MCU10, the OFDM processing module 20, and the control module 30, and also integrates the first memory 101 and the second memory 102, which can realize that data is obtained from the memory inside the chip by the internal control of the chip, wherein the performance of the MCU10 is not limited by the present invention, preferably, the 32-bit low-power consumption high-speed MCU10 can be selected, and the coupling circuit connected to the power line carrier communication chip can be a complete circuit or a power line carrier communication chip.

Specifically, in the embodiment shown in fig. 1, in the process of transmitting data by the power line carrier communication chip, the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables to control the OFDM processing module 20 to obtain the transmission data from the first memory 101 for modulation processing, where the transmission data may be regarded as the transmission data that is transmitted by the MCU10 for the first time, that is, the first transmission data, and the modulation processing here is a general concept and may include: processing procedures such as encoding, modulation, Inverse Fast Fourier Transform (IFFT) operation, and the like; after the OFDM processing module 20 completes the modulation processing of the transmission data, the OFDM processing module stores the transmission data after the modulation processing into the second memory 102, at this time, the control module 30 detects that the modulation processing of the OFDM processing module 20 is finished, it is indicated that the transmission data in the first memory 101 has been read empty by the OFDM processing module 20, the control module 30 enables the control MCU10 to transmit the second transmission data to the first memory 101, perform modulation processing directly by the OFDM processing module 20, at the same time, the control module 30 enables the AFE40 to obtain the modulated first transmission data from the second memory 102, and the first transmission data after modulation processing is sent to a coupling circuit connected with the power line carrier communication chip after being subjected to digital-to-analog conversion, that is, the digital-to-analog conversion processing of the modulated first transmission data and the transmission by the AFE40 are performed in synchronization with the modulation processing of the second transmission data by the OFDM processing module 20.

Further, in the process of receiving data by the power line carrier communication chip, in the first embodiment shown in fig. 1, the control module 30 enables to control the AFE40 to receive the received data sent by the coupling circuit connected to the power line carrier communication chip, where the received data may be regarded as the received data received by the AFE40 for the first time, that is, the first received data, and the received data is the carrier signal coupled by the coupling circuit, and the received data received by the AFE in all the following embodiments, sent from the coupling circuit connected to the power line carrier communication chip, is the carrier signal coupled by the coupling circuit; the AFE40 performs analog-to-digital conversion on the first received data and sends the first received data to the second memory 102, the second memory 102 adopts a ping-pong structure and is divided into a left half part and a right half part, the left half part stores the first received data sent by the AFE40, and the right half part stores the second received data sent by the AFE40, so that data received by the AFE40 from a power line and sent to the second memory can not be lost; when the left half is fully written by AFE40, control module 30 enables control OFDM processing module 20 to obtain the first received data after analog-to-digital conversion from second memory 102 for demodulation processing, and it should be noted that demodulation here does not only include demodulation process, but also includes decoding, window shifting, Fast Fourier Transform (FFT) operation, and so on, where these processing processes are summarized by demodulation, OFDM processing module 20 sends the first received data after demodulation processing to first memory 101, when control module 30 detects that demodulation processing of OFDM processing module 20 has ended, which indicates that the first received data in second memory 102 has been read empty, control module 30 enables OFDM processing module 20 to obtain the second received data from second memory 102 for demodulation, and control module 30 also enables control MCU10 to obtain the first received data after demodulation processing from first memory 101, that is, the process of MCU10 retrieving the first received data from first memory 101 and the process of OFDM processing module 20 retrieving the second received data from second memory 102 for demodulation are performed synchronously.

According to the power line carrier communication chip provided by the invention, the sending end stores the first sending data into the first memory through the MCU, the OFDM processing module acquires the first sending data from the first memory for modulation processing and then sends the first sending data to the second memory, the MCU sends the second sending data to the first memory, the AFE acquires the first sending data from the second memory for processing and sends the first sending data, the OFDM processing module processes the second sending data, the receiving end acquires the first receiving data through the MCU, and the OFDM processing module processes the second receiving data, so that the data transmission efficiency, the data processing speed and the hardware resource utilization rate of the OFDM power line carrier communication chip are improved.

Fig. 2 is a schematic structural diagram of a second embodiment of a power line carrier communication chip provided in the present invention, and as shown in fig. 2, on the basis of the first embodiment, the OFDM processing module 20 includes: an encoding module 201, a modulation module 202, an IFFT module 203, and a cyclic prefix windowing module 204; the encoding module 201 is configured to acquire the transmission data from the first memory 101 under the control of the control module 30, encode the transmission data, and send the encoded transmission data to the modulation module 202; the modulation module 202 is configured to modulate the coded transmission data under the control of the control module 30 and then transmit the modulated transmission data to the IFFT module 203; the IFFT module 203 is configured to perform IFFT operation on the modulated transmission data under the control of the control module 30, and then transmit the modulated transmission data to the cyclic prefix windowing module 204; the cyclic prefix windowing module 204 is configured to perform cyclic prefix and windowing on the transmission data after the IFFT operation under the control of the control module 30, and then transmit the transmission data to the second memory 102.

Specifically, in the process of transmitting data by the power line carrier communication chip, the MCU10 transmits the transmitted data to the first memory 101; the control module 30 enables the coding module 201 to acquire transmission data from the first memory 101, where the transmission data may be regarded as transmission data that is first transmitted by the MCU10, that is, first transmission data, after the coding module 201 performs coding processing on the first transmission data under the control of the control module 30, the coded first transmission data is transmitted to the modulation module 202, and when the control module 30 detects that the coding processing of the coding module 201 is finished, which indicates that the first transmission data in the first memory 101 has been read empty by the coding module 201, the control module 30 enables the control MCU10 to transmit second transmission data to the first memory 101, and waits for coding and subsequent processing, and simultaneously, after the control module 30 further enables the modulation module 202 to perform modulation processing on the coded first data, the modulated first transmission data is transmitted to the IFFT module 203; the IFFT module 203 performs IFFT operation on the modulated first data under the control module 30, and sends the IFFT-operated first transmission data to the cyclic prefix windowing module 204; the cyclic prefix windowing module 204 performs cyclic prefix adding and windowing on the first transmission data after the IFFT operation under the control of the control module 30, and sends the first transmission data after the cyclic prefix adding and windowing to the second memory 102; after the control module 30 detects that the processing of the cyclic prefix windowing module 204 is finished, the control module 30 enables the coding module 201 to acquire the second transmission data from the first memory 101 for coding, the modulation module 202 to modulate the coded second transmission data, the IFFT module 203 to perform IFFT operation on the modulated second transmission data, and the cyclic prefix windowing module 204 to perform cyclic prefix and windowing on the IFFT-processed second transmission data, and at the same time, the control module 30 also enables the AFE40 to acquire the cyclic prefix and windowed first transmission data from the second memory 102 for digital-to-analog conversion, and sends the digital-to-analog converted first transmission data to a coupling circuit connected to the power line carrier communication chip, that is, the AFE40 acquires the cyclic prefix and windowed first transmission data from the second memory 102 for digital-to analog conversion and sending, and the coding module 201, The modulation module 202, the IFFT module 203, and the cyclic prefix windowing module 204 perform corresponding processing on the second transmission data synchronously.

According to the power line carrier communication chip provided by the embodiment, the first sending data is stored in the first memory through the MCU, the OFDM processing module acquires the first sending data from the first memory, modulates the first sending data and sends the first sending data to the second memory, the MCU sends the second sending data to the first memory, the AFE acquires the first sending data from the second memory, processes the first sending data and sends the first sending data, and meanwhile, the OFDM processing module processes the second sending data, so that the data transmission efficiency, the data processing speed and the hardware resource utilization rate of the OFDM power line carrier communication chip are improved.

Further, on the basis of the above embodiments, fig. 3A is a schematic structural diagram of a third embodiment of the power line carrier communication chip provided by the present invention, fig. 3B is a schematic structural diagram of a fourth embodiment of the power line carrier communication chip provided by the present invention, fig. 3C is a schematic structural diagram of a fifth embodiment of the power line carrier communication chip provided by the present invention, fig. 3D is a schematic structural diagram of a sixth embodiment of the power line carrier communication chip provided by the present invention, fig. 3E is a schematic structural diagram of a seventh embodiment of the power line carrier communication chip provided by the present invention, and fig. 3F is a schematic structural diagram of an eighth embodiment of the power line carrier communication chip provided by the present invention; among the encoding module 201, the modulation module 202, the IFFT module 203, and the cyclic prefix windowing module 204 included in the OFDM processing module 20, a third memory 50 is disposed between at least one pair of adjacent first and second modules; the first module is configured to send the sending data processed by the first module to the third memory 50 under the control of the control module 30; the second module is configured to, under the control of the control module 30, obtain the transmission data processed by the first module from the third memory 50.

Specifically, on the basis of the above embodiment, the third memory 50 is disposed between at least one pair of adjacent first and second modules, and there may be several following implementation manners:

(1) a third memory 50 is disposed between a pair of adjacent first modules and second modules, that is, the third memory 50 may be located between the encoding module 201 and the modulation module 202, between the modulation module 202 and the IFFT module 203, or between the IFFT module 203 and the cyclic prefix windowing module 204, that is, there may be three memories in the data processing flow of power line carrier communication: a first memory 101, a second memory 102, and a third memory 50.

As shown in fig. 3A, when the third memory 50 is located between the encoding module 201 and the modulation module 202, the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables the coding module 201 to obtain the transmission data from the first memory 101, where the transmission data may be regarded as the transmission data that is first transmitted by the MCU10, that is, the first transmission data, and the coding module 201, after performing coding processing on the first transmission data under the control of the control module 30, transmits the coded first transmission data to the third memory 50; when the control module 30 detects that the encoding process of the encoding module 201 is finished, which indicates that the first transmission data in the first memory 101 has been read empty by the encoding module 201, the control module 30 enables the control MCU10 to transmit the second transmission data to the first memory 101, waits for encoding and subsequent processes, and enables the modulation module 202 to acquire the encoded first transmission data from the third memory 50 for modulation.

The modulation module 202 sends the modulated first sending data to the IFFT operation module 203, the IFFT operation module 203 performs IFFT operation and sends the first sending data to the cyclic prefix windowing module 204, and the cyclic prefix windowing module 204 performs cyclic prefix addition and windowing processing on the IFFT-operated first sending data and sends the first sending data to the second memory 102; meanwhile, when the control module 30 detects that the modulation processing of the modulation module 202 has ended, which indicates that the encoded first transmission data stored in the third memory 50 has been read empty by the modulation module 202, the control module 30 enables the encoding module 201 to acquire the second transmission data from the first memory 101 for encoding, and transmits the encoded second transmission data to the third memory 50; the control module 30 enables the modulation module 202 to modulate the encoded second transmission data, and at this time, the control module 30 also enables the MCU10 to transmit the third transmission data to the first memory 101; that is, the modulation, IFFT operation, cyclic prefix adding and windowing of the first transmission data are performed in synchronization with the transmission of the second transmission data to the first memory by the MCU10, and the processing of the AFE40 obtaining the cyclic prefix and windowed first transmission data from the second memory 102, performing digital-to-analog conversion, and transmitting the digital-to-analog converted first transmission data to the peer-to-peer coupling circuit is performed in synchronization with the encoding of the second transmission data.

As shown in fig. 3B, in the case where the third memory 50 is located between the modulation module 202 and the IFFT module 203, the MCU10 transmits the transmission data to the first memory 101, similarly to the above embodiment; the control module 30 enables the control coding module 201 to acquire first transmission data from the first memory 101, the coding module 201 performs coding processing on the first transmission data under the control of the control module 30 and then transmits the coded first transmission data to the modulation module 202, and the modulation module 202 performs modulation processing on the coded first data under the control of the control module 30 and then transmits the modulated first transmission data to the third memory 50; when the control module 30 detects that the coding operation of the coding module 201 is finished, it indicates that the data in the first memory 101 has been read empty, enabling the MCU10 to send second transmission data to the first memory 101, waiting for coding and subsequent processing, and enabling the IFFT module 203 to obtain modulated first data from the third memory 50 for IFFT operation, and sending the IFFT-operated first transmission data to the cyclic prefix windowing module 204 for cyclic prefix addition and windowing, and then sending the IFFT-operated first transmission data to the second memory 102; when the control module 30 detects that the IFFT operation of the IFFT module 203 is finished, indicating that the modulated first transmission data stored in the third memory 50 has been read empty, the control module 30 enables the encoding module 201 to obtain the second transmission data from the first memory 101 for encoding operation, and sends the encoded second transmission data to the modulation module 202, and under the control of the control module 30, the modulation module 202 modulates the encoded second transmission data and sends the modulated second transmission data to the third memory 50, and waits for the IFFT operation and subsequent processing; and when the control module 30 detects the end of the encoding operation of the encoding module 201 again, the MCU10 is also enabled to transmit third transmission data to the first memory 101 so that it can process according to the above-mentioned processing procedure; in fact, that is, the IFFT operation is performed on the first transmission data, the cyclic prefix and windowing process is performed in synchronization with the process of transmitting the second transmission data to the first memory 101 by the MCU10, and the process of acquiring the cyclic prefix and windowed first transmission data from the second memory 102 by the AFE40, performing digital-to-analog conversion on the first transmission data and transmitting the first transmission data to the peer-to-peer coupling circuit is also performed in synchronization with the process of encoding the second transmission data by the encoding module 201 and transmitting the second transmission data to the modulation module for modulation.

As shown in fig. 3C, the third memory 50 is located between the IFFT module 203 and the cyclic prefix windowing module 204, and the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables the control encoding module 201 to acquire first transmission data from the first memory 101, and the encoding module 201 transmits the encoded first transmission data to the modulation module 202 after encoding the first transmission data under the control of the control module 30; the modulation module 202 modulates the encoded first data under the control of the control module 30, and then sends the modulated first transmission data to the IFFT module 203; the IFFT module 203 performs IFFT operation on the first transmission data and stores the IFFT-operated first transmission data in the third memory 50; when the control module 30 detects that the coding operation of the coding module 201 is finished, the control module 30 enables the MCU10 to send the second transmission data to the first memory 101, and also enables the cyclic prefix windowing module 204 to obtain the first transmission data after the IFFT operation from the third memory 50 for cyclic prefix and windowing, and send the processed first transmission data to the second memory 102; when the control module 30 detects that the processing of the cyclic prefix windowing module 204 is finished, which indicates that the first transmission data after IFFT operation in the memory of the third memory 50 is already empty, the control module 30 enables the encoding module 201 to obtain the second transmission data from the second memory 102 for encoding, the modulation module 202 to modulate the second transmission data after encoding operation, and the IFFT module 203 to perform IFFT operation on the second transmission data after modulation processing, and also enables the AFE40 to obtain the cyclic prefix and the first transmission data after windowing from the second memory 102 for digital-to-analog conversion and send to the coupling circuit of the opposite end; when the control module 30 detects the end of the encoding operation of the encoding module 201 again, the MCU10 is also enabled to transmit third transmission data to the first memory 101 for the same processing as described above; in fact, the process of windowing the first transmission data is synchronized with the process of transmitting the second transmission data to the first memory 101 by the MCU10, and the subsequent process of digital-to-analog conversion and transmission of the AFE40 is synchronized with the process of encoding, modulating, and IFFT operation of the second data.

(2) If a memory is disposed between two adjacent pairs of the first module and the second module, the memory a501 and the memory B502 can be located in three ways, namely, the first way: a memory is arranged between the coding module 201 and the modulation module 202, which is assumed as a memory A501, and a memory is arranged between the modulation module 202 and the IFFT module 203, which is assumed as a memory B502; and the second method comprises the following steps: a memory is arranged between the coding module 201 and the modulation module 202, and is assumed to be a memory A501, and a memory is arranged between the IFFT module 203 and the cyclic prefix windowing module 204, and is assumed to be a memory B502; and the third is that: a memory is arranged between the modulation module 202 and the IFFT module 203, which is assumed as a memory a501, and a memory is arranged between the IFFT module 203 and the cyclic prefix windowing module 204, which is assumed as a memory B502; that is, there may be four memories in the data processing flow of the power line carrier communication, which are respectively: the first memory 101, the second memory 102, the memory a501 and the memory B502 are specifically implemented as follows:

for the first case, as shown in fig. 3D, the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables the coding module 201 to obtain the transmission data from the first memory 101, where the transmission data may be regarded as the transmission data that is first transmitted by the MCU10, that is, the first transmission data, and the coding module 201, after performing coding processing on the first transmission data under the control of the control module 30, transmits the coded first transmission data to the memory a 501; when the control module 30 detects that the encoding processing of the encoding module 201 is finished, which indicates that the first transmission data in the first memory 101 has been read empty by the encoding module 201, the control module 30 enables the control MCU10 to transmit the second transmission data to the first memory 101, waits for encoding and subsequent processing, and enables the modulation module 202 to acquire the encoded first transmission data from the memory a501 for modulation; the modulation module 202 acquires the coded first transmission data from the memory a501, modulates the first transmission data, and transmits the modulated first transmission data to the memory B502; when the control module 30 detects that the modulation processing of the modulation module 202 is finished, the enable coding module 201 obtains the second transmission data from the first memory 101 for coding processing, and sends the coded second transmission data to the memory a501, to be ready for modulation processing, and simultaneously, the enable IFFT module 203 obtains the modulated first transmission data from the memory B502 for IFFT operation, and sends the calculated first transmission data to the cyclic prefix windowing module 204 for cyclic prefix and windowing processing, and sends the processed first transmission data to the second memory 102; when the control module 30 detects that the IFFT operation of the IFFT module 203 is finished, which indicates that the first transmission data in the memory B502 is already read empty, the control module 30 enables the modulation module 202 to obtain the encoded second transmission data from the memory a501 for modulation processing, and then sends the modulated second transmission data to the memory B502, and enables the IFFT module 203 to obtain the modulated second transmission data from the memory B502 for IFFT operation; meanwhile, the control module 30 enables the AFE40 to obtain the first transmission data after cyclic prefix and windowing from the second memory 102, perform digital-to-analog conversion, and transmit the first transmission data to the coupling circuit of the opposite end, that is, actually, when the first transmission data is modulated, the second transmission data is already waiting for encoding processing in the first memory 101, and when the modulation of the first transmission data is finished, the second transmission data can be directly encoded; when the control module 30 detects that the IFFT operation of the IFFT module 203 on the first transmission data is finished, the second transmission data can be directly modulated; when the first sending data is analog-to-digital converted, the IFFT operation, cyclic prefix adding and windowing processing of the second sending data are performed synchronously, wherein the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first sending data after cyclic prefix adding and windowing processing, and the right half stores the second sending data after cyclic prefix adding and windowing processing, so that the AFE40 can continuously read data from the second memory 102.

For the second case, as shown in fig. 3E, the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables the control encoding module 201 to acquire first transmission data from the first memory 101, and the encoding module 201 transmits the encoded first transmission data to the memory a501 after encoding the first transmission data under the control of the control module 30; when the control module 30 detects that the encoding processing of the encoding module 201 is finished, which indicates that the first transmission data in the first memory 101 has been read empty by the encoding module 201, the control module 30 enables the control MCU10 to transmit the second transmission data to the first memory 101, waits for encoding and subsequent processing, and enables the modulation module 202 to acquire the encoded first transmission data from the memory a501 for modulation; the modulation module 202 acquires the encoded first transmission data from the memory a501, modulates the first transmission data, and transmits the modulated first transmission data to the IFFT module 203, and the IFFT module 203 performs IFFT operation on the modulated first transmission data under the control of the control module 30 and transmits the IFFT-operated first transmission data to the memory B502; when the control module 30 detects that the modulation processing of the modulation module 202 is finished, the enable encoding module 201 obtains the second transmission data from the first memory 101, performs encoding processing on the second transmission data, and then transmits the encoded second transmission data to the memory a501, to prepare for modulation processing, and simultaneously, the enable cyclic prefix windowing module 204 obtains the first transmission data after IFFT operation from the memory B502, performs cyclic prefix adding and windowing processing on the first transmission data, and transmits the first transmission data after cyclic prefix adding and windowing processing to the second memory 102; when the control module 30 detects that the cyclic prefix adding and windowing processing of the cyclic prefix windowing module 204 is finished, the modulation module 202 is enabled to acquire the coded second transmission data from the memory a501 for modulation, and transmit the modulated second transmission data to the IFFT module 203 for IFFT operation and then to the memory B502, and the AFE40 is also enabled to acquire the cyclic prefix adding and windowing processed first transmission data from the second memory 102 for digital-to-analog conversion and then to transmit to the coupling circuit of the opposite end; in fact, that is to say, when the first transmission data is modulated, the second transmission data is already waiting for coding in the first memory 101, and when the modulation of the first transmission data and the IFFT operation are finished, the second transmission data can be directly coded; when the control module 30 detects that the cyclic prefix windowing processing module finishes the cyclic prefix adding and windowing processing of the first sending data, the second sending data can be directly modulated and subjected to IFFT operation; when the first transmission data is analog-to-digital converted, the cyclic prefix and the windowing of the second transmission data are performed synchronously, wherein the second memory 102 adopts a ping-pong structure and is divided into a left half and a right half, the left half stores the first transmission data after the cyclic prefix and the windowing, and the right half stores the second transmission data after the cyclic prefix and the windowing, so that the AFE40 can continuously read data from the second memory 102.

For the third case, as shown in fig. 3F, the MCU10 transmits the transmission data to the first memory 101; the control module 30 enables the control encoding module 201 to acquire first transmission data from the first memory 101, and the encoding module 201 transmits the encoded first transmission data to the modulation module 202 after encoding the first transmission data under the control of the control module 30; the modulation module 202 modulates the encoded first transmission data under the control of the control module 30, and transmits the modulated first transmission data to the memory a 501; when the control module 30 detects that the coding operation of the coding module 201 is finished, the MCU10 is enabled to send the second transmission data to the first memory 101, and the IFFT module 203 is enabled to obtain the modulated first transmission data from the memory a501 for IFFT operation, and send the IFFT-operated first transmission data to the memory B502; when the control module 30 detects that the IFFT operation of the IFFT module 203 is finished, the enable encoding module 201 obtains second transmission data from the first memory 101 to perform encoding processing, sends the encoded second transmission data to the modulation module 202 to perform modulation processing, and sends the modulated second transmission data to the memory a501, and also enables the cyclic prefix windowing processing module to obtain first transmission data after the IFFT operation from the memory B502, and sends the first transmission data after the cyclic prefix and windowing processing to the second memory 102; when the control module 30 detects that the cyclic prefix adding and windowing processing is finished, the IFFT module 203 is enabled to obtain the modulated second transmission data from the memory a501 for IFFT operation, and send the IFFT-operated second transmission data to the memory B502, and the AFE40 is also enabled to obtain the cyclic prefix added and windowed first transmission data from the second memory 102 for digital-to-analog conversion and send the converted first transmission data to the coupling circuit of the opposite end, and the cyclic prefix windowing processing module is also enabled to obtain the IFFT-operated second transmission data from the memory B502, and send the cyclic prefix added and windowed second transmission data to the second memory 102; that is, when the first transmission data is subjected to the IFFT operation, the second transmission data already waits for the encoding processing in the first memory 101; when the IFFT operation of the first sending data is finished, the second sending data can be directly coded and modulated; when the control module 30 detects that the cyclic prefix windowing module finishes the cyclic prefix adding and windowing of the first sending data, the second sending data can directly perform the IFFT operation; when the first transmission data is analog-to-digital converted, the cyclic prefix and the windowing of the second transmission data are performed synchronously, wherein the second memory 102 adopts a ping-pong structure and is divided into a left half and a right half, the left half stores the first transmission data after the cyclic prefix and the windowing, and the right half stores the second transmission data after the cyclic prefix and the windowing, so that the AFE40 can continuously read data from the second memory 102.

(3) A memory is respectively arranged between the three adjacent pairs of the first module and the second module, namely, a memory is arranged between the coding module 201 and the modulation module 202, a memory is arranged between the modulation module 202 and the IFFT module 203, and a memory is arranged between the IFFT module 203 and the cyclic prefix windowing module 204, namely, 5 memories are arranged in the power line carrier communication data processing flow. The following example nine is a specific description of this case.

On the basis of the embodiments shown in fig. 1 to fig. 3F, fig. 4 is a schematic structural diagram of a ninth embodiment of the power line carrier communication chip provided by the present invention, and preferably, a fourth memory 104 is disposed between the encoding module 201 and the modulation module 202; a fifth memory 105 is arranged between the modulation module 202 and the IFFT module 203; a sixth memory 106 is arranged between the IFFT module 203 and the cyclic prefix windowing module 204; the encoding module 201 is configured to obtain the sending data from the first memory 101 under the control of the control module 30, and send the encoded sending data to the fourth memory 104; the modulation module 202 is configured to obtain the coded transmission data from the fourth memory 104 under the control of the control module 30, and send the modulated transmission data to the fifth memory 105; the IFFT module 203, configured to obtain the modulated transmission data stored in the fifth memory 105 under the control of the control module 30, and send the IFFT-operated transmission data to the sixth memory 106; the cyclic prefix windowing module 204 is configured to obtain the transmission data after IFFT operation from the sixth memory 106 under the control of the control module 30, and send the transmission data after cyclic prefix and window addition to the second memory 102.

Specifically, the 32-bit MCU10 with low power consumption and high speed transmits the transmission data to the first memory 101, where the transmission data can be regarded as the first transmission data transmitted by the MCU10, and the control module 30 enables the encoding module 201 to start encoding operation; the encoding module 201 acquires first transmission data from the first memory 101 for encoding, and transmits the encoded first transmission data to the fourth memory 104; when the control module 30 detects that the encoding operation of the encoding module 201 has ended, which indicates that the data in the first memory 101 has been read empty, the MCU10 is enabled to transmit the data of the next frame to the first memory 101 (where the transmission data of the next frame may be the second transmission data), so as to prepare for encoding the second transmission data, and the control module 30 also enables the modulation module 202 to start the modulation operation; after the modulation module 202 is enabled, the encoded first transmission data is read from the fourth memory 104 for modulation, and the modulated first transmission data is stored in the fifth memory 105; when detecting that the modulation processing of the modulation module 202 has ended, that is, the data in the fourth memory 104 has been read empty, the control module 30 enables the encoding module 201 to obtain the second transmission data from the first memory 101 for encoding, and send the encoded second transmission data to the fourth memory 104, waiting for the modulation processing to be performed, and simultaneously, the control module 30 also enables the IFFT module 203 to obtain the modulated first transmission data from the fifth memory 105 for IFFT operation, and send the IFFT-operated first transmission data to the sixth memory 106; when the control module 30 detects that the IFFT operation of the IFFT module 203 has ended, which indicates that the data in the fifth memory 105 has been read empty, the modulation module 202 is enabled to obtain the encoded second transmission data from the fourth memory 104 for modulation, and send the modulated second transmission data to the fifth memory 105, prepare to perform IFFT operation on the second transmission data, and at the same time, the cyclic prefix windowing module 204 is enabled to obtain the first transmission data after IFFT operation from the sixth memory 106 for cyclic prefix and windowing processing, and send the first transmission data after cyclic prefix and windowing processing to the second memory 102; the control module 30 detects that the cyclic prefix windowing and windowing process of the cyclic prefix windowing module 204 has ended, indicating that the data in the sixth memory 106 has been read empty, the control module 30 enables the IFFT module 203 to acquire the modulated second transmission data from the fifth memory 105 for IFFT operation, and transmits the operated second transmission data to the sixth memory 106, meanwhile, the control module 30 enables the AFE40 to obtain the cyclic prefix and windowed first transmission data from the second memory 102, perform digital-to-analog conversion on the obtained data and transmit the converted data to the coupling circuit of the opposite terminal, the coupling circuit of the opposite end is the coupling circuit connected with the power line carrier communication chip, and at the same time, the control module 30 further enables the cyclic prefix windowing module 204 to obtain the second transmission data after the IFFT operation from the sixth memory 106, perform cyclic prefix and windowing processing, and then transmit the second transmission data to the second memory 102.

In fact, after the first transmission data is encoded, the MCU10 may send the second transmission data to the first memory 101 and wait for encoding; when the modulation operation of the first sending data is finished, the second sending data can be coded; when the IFFT operation of the first sending data is finished, the second sending data can be directly modulated; when the control module 30 detects that the cyclic prefix windowing module finishes the cyclic prefix adding and windowing of the first sending data, the second sending data can directly perform the IFFT operation; when the first transmission data is analog-to-digital converted, the cyclic prefix and the windowing of the second transmission data are performed synchronously, wherein the second memory 102 adopts a ping-pong structure and is divided into a left half and a right half, the left half stores the first transmission data after the cyclic prefix and the windowing, and the right half stores the second transmission data after the cyclic prefix and the windowing, so that the AFE40 can continuously read data from the second memory 102.

Further, as shown with continued reference to fig. 4, preferably, the modulated transmission data stored in the fifth memory 105 is mapped into the sixth memory 106; the IFFT module 203 is configured to obtain the modulated transmission data from the sixth memory 106 under the control of the control module 30.

After the modulation module 202 sends the modulated first transmission data to the fifth memory 105, the fifth memory 105 maps the modulated first transmission data to the sixth memory 106 in order to facilitate the IFFT operation of the IFFT module 203, and then the IFFT module 203 obtains the mapped first transmission data from the sixth memory 106 to perform the IFFT operation, and continuously stores the IFFT-operated first transmission data in the sixth memory 106; for the rest of the processing, refer to the implementation in the third embodiment, which is not described herein again; it should be noted that the IFFT module 203 and the FFT module 303 in the present invention may be the same module, and they may be multiplexed, that is, when receiving data, the module is used to perform FFT operation on the received data, and when transmitting data, the module is used to perform IFFT operation on the transmitted data.

In the power line carrier communication provided by the embodiment, the memories are respectively arranged between the adjacent modules to store the data processed by each module, and the memories are arranged to enable the next frame of data not to wait until the previous frame of data is processed, that is, the operation among the modules included in the OFDM processing module is independently completed, so that the processing speed of the chip is effectively improved, and the hardware resources of each module are also saved.

Fig. 5 is a schematic structural diagram of a tenth embodiment of a power line carrier communication chip provided in the present invention, and on the basis of the foregoing embodiment, the OFDM processing module 20 includes: a cyclic prefix de-windowing module 304, a fast fourier transform FFT module 303, a demodulation module 302 and a decoding module 301; the cyclic prefix removing and window shifting module 304 is configured to obtain received data from the second memory 102 under the control of the control module 30, perform cyclic prefix removing and window shifting on the received data, and send the received data to the FFT module 303; the FFT module 303 is configured to perform FFT operation on the received data without cyclic prefix and after moving the window, and send the received data to the demodulation module 302; the demodulation module 302 is configured to demodulate the received data after the FFT operation and send the demodulated received data to the decoding module 301; the decoding module 301 is configured to decode the demodulated received data and send the decoded received data to the first memory 101.

Specifically, the control module 30 enables to control the AFE40 to receive the received data sent by the coupling circuit connected to the power line carrier communication chip, where the received data may be regarded as the received data received by the AFE40 for the first time, that is, the first received data, and the AFE40 performs analog-to-digital conversion on the first received data and sends the first received data to the second memory 102; the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data transmitted by the AFE40, and the right half stores the second received data transmitted by the AFE40, so as to ensure that the data transmitted by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to obtain the first received data after analog-to-digital conversion from the second memory 102 for performing the cyclic prefix removal and window shifting processing, and send the first received data after cyclic prefix removal and window shifting processing to the FFT module 303; when the control module 30 detects that the processing of removing the cyclic prefix and the window by the window-shifting module 304 is finished, it indicates that the left half of the data in the second memory 102 has been read empty (when the window-shifting module 304 reads the first received data in the left half of the second memory 102, the AFE40 can still transmit the second received data to the right half of the second memory 102), the control module 30 enables to control the FFT module 303 to perform FFT operation on the first received data after removing the cyclic prefix and the window-shifting processing and then send the first received data to the demodulation module 302, and the demodulation module 302 performs demodulation processing on the first received data after FFT operation under the control of the control module 30 and then sends the first received data to the decoding module 301; the decoding module 301 decodes the first received data after the FFT operation under the control of the control module 30, and sends the decoded first received data to the first memory 101; when the control module 30 detects that the decoding operation of the decoding module 301 is finished, the cp windowing module 304 is enabled to acquire the second received data from the second memory 102 for cp removal and windowing, and the MCU10 is also enabled to acquire the decoded first received data from the first memory 101, that is, the process of analog-to-digital converting the second received data via the AFE40 and sending the second received data to the second memory is synchronized with the process of the MCU10 acquiring the decoded first received data from the first memory 101; the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data transmitted by the AFE40, and the right half stores the second received data transmitted by the AFE40, so as to ensure that the data transmitted by the AFE40 is not lost.

According to the power line carrier communication chip provided by the embodiment, the AFE sends the first received data after analog-to-digital conversion to the second memory, the OFDM processing module obtains the first received data from the second memory for processing and then sends the first received data to the first memory, the AFE sends the second received data after analog-to-digital conversion to the second memory, and the MCU obtains the decoded first received data from the first memory and simultaneously the OFDM processing module processes the second sent data, so that the transmission efficiency and the processing speed of the data of the OFDM power line carrier communication chip are improved.

Further, fig. 6A is a schematic structural diagram of an eleventh embodiment of a power line carrier communication chip provided by the present invention, fig. 6B is a schematic structural diagram of a twelfth embodiment of the power line carrier communication chip provided by the present invention, fig. 6C is a schematic structural diagram of a thirteenth embodiment of the power line carrier communication chip provided by the present invention, fig. 6D is a schematic structural diagram of a fourteenth embodiment of the power line carrier communication chip provided by the present invention, fig. 6E is a schematic structural diagram of a fifteenth embodiment of the power line carrier communication chip provided by the present invention, and fig. 6F is a schematic structural diagram of a sixteenth embodiment of the power line carrier communication chip provided by the present invention; on the basis of the above embodiment, in the cyclic prefix de-windowing module 304, the FFT module 303, the demodulation module 302 and the decoding module 301 included in the OFDM processing module 20, a third memory 50 is disposed between at least one pair of adjacent third and fourth modules; the third module is configured to send the processed received data to the third memory 50; the fourth module is configured to, under the control of the control module 30, obtain the received data processed by the third module from the third memory 50.

(1) a third memory 50 is disposed between a pair of adjacent first and second modules, that is, the third memory 50 may be located between the window-shifting module 304 for removing cyclic prefix and the FFT module 303, between the FFT303 module and the demodulation module 302, or between the demodulation module 302 module and the decoding module 301, that is, there may be three memories in the data processing flow of power line carrier communication: a first memory 101, a second memory 102, and a third memory 50.

As shown in fig. 6A, when the third memory 50 is located between the window-shifting module 304 for cyclic prefix and the FFT module 303, the control module 30 enables the AFE40 to receive the first received data sent by the opposite-end coupling circuit from the power line, perform analog-to-digital conversion on the received first received data, and perform detection on the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data in the left half of the second memory 102 for the cyclic prefix and window shifting processing, perform the data mapping initialization on the first received data after the cyclic prefix and window shifting processing, and send the first received data after the mapping initialization to the third memory 50, because the second memory 102 is a ping-pong structure, when the cyclic prefix window shifting module 304 reads the first received data in the left half of the second memory 102, the AFE40 can still send the second received data after the analog-to-digital conversion to the right half of the second memory 102, thereby ensuring that the data is not lost.

Then, the control module 30 enables the FFT module 303 to perform FFT operation, and after the FFT module 303 is enabled, acquires the first received data after mapping initialization from the third memory 50 to perform FFT operation, and sends the first received data after FFT operation to the demodulation module 302; the demodulation module 302 demodulates the first received data after the FFT operation under the control of the control module 30 and then sends the demodulated first received data to the decoding module 301; the decoding module 301 decodes the first received data after absolute demodulation under the control of the control module 30, and stores the decoded first received data into the first memory 101; when the control module 30 detects that the FFT operation in the FFT module 303 is finished, which indicates that the data in the third memory 50 has been read empty, the control module 30 enables the window module 304 to obtain the second received data after analog-to-digital conversion from the second memory 102 for performing the processing of removing the cyclic prefix and moving the window, and sends the processed data to the third memory 50 after initializing the data mapping, and simultaneously, the control module 30 also enables the MCU10 to read the decoded first received data from the first memory 101 until the MCU10 finishes reading the decoded first received data in the first memory 101, the FFT module 303 obtains the second received data after initializing the mapping from the third memory 50 for performing the FFT operation, the demodulation module 302 performs the demodulation processing on the second received data after FFT operation, and the decoding module 301 performs the decoding operation on the second received data after demodulation processing, the decoding module 301 stores the decoded second received data in the first memory 101.

As shown in fig. 6B, when the third memory 50 is located between the FFT module 303 and the demodulation module 302, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, and performs analog-to-digital conversion processing on the received first received data, and performs detection of a synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data of the left half in the second memory 102 for the cyclic prefix removal and window shifting processing, perform data mapping initialization on the first received data after the cyclic prefix removal and window shifting processing, and send the first received data after the mapping initialization to the FFT module 303; the control module 30 enables the FFT module 303 to perform FFT operation on the first received data after map initialization, and then stores the first received data after FFT operation in the third memory 50, and when the control module detects that the operation of the FFT module 303 is finished, enables the demodulation module 302 to acquire the first received data after FFT operation from the third memory 50, and then sends the first received data after FFT operation to the decoding module 301 after demodulation operation, and then sends the first received data after demodulation to the first memory 101 after the decoding module 301 decodes the first received data after demodulation; when the control module 30 detects that the demodulation operation of the demodulation module 302 is finished, the control module 30 enables the cyclic prefix removal window shifting module 304 to obtain the second received data after the analog-to-digital conversion from the second memory 102 for cyclic prefix removal and window shifting, and sends the second received data after the cyclic prefix removal and the window shifting to the FFT module 303 for FFT operation and then to the third memory 50; when the control module 30 detects that the operation of the decoding module 301 is finished, the control module 30 enables the MCU10 to obtain the decoded first received data from the first memory 101, and enables the demodulation module 302 to obtain the second received data after the FFT operation from the third memory 50 for demodulation operation until the MCU10 finishes reading the decoded first received data from the first memory 101.

As shown in fig. 6C, when the third memory 50 is located between the demodulation module 302 and the decoding module 301, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, and performs analog-to-digital conversion processing on the received first received data, and performs detection of the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data of the left half in the second memory 102 for the cyclic prefix removal and window shifting processing, perform data mapping initialization on the first received data after the cyclic prefix removal and window shifting processing, and send the first received data after the mapping initialization to the FFT module 303; the control module 30 enables the FFT module 303 to perform FFT operation on the first received data after map initialization, and then sends the first received data after FFT operation to the demodulation module 302; the demodulation module 302 demodulates the first received data after the FFT operation under the control of the control module 30, and stores the demodulated first received data into the third memory 50; when the control module detects that the demodulation operation of the demodulation module 302 is finished, the control module 30 enables the decoding module 301 to acquire the demodulated first received data from the third memory 50, decode the demodulated first received data, and send the decoded first received data to the first memory 101; when the control module 30 detects that the decoding processing of the decoding module 301 is finished, which indicates that the data in the third memory 50 has been read empty, the window shifting module 304 for enabling the cyclic prefix removal obtains the second received data from the second memory 102 to perform cyclic prefix removal and window shifting processing, performs data mapping initialization on the second received data after cyclic prefix removal and window shifting processing, and sends the first received data after mapping initialization to the FFT module 303; the control module 30 enables the FFT module 303 to perform FFT operation on the second received data after map initialization, and then sends the second received data after FFT operation to the demodulation module 302; the demodulation module 302 demodulates the second received data after the FFT operation under the control of the control module 30, and stores the demodulated second received data in the third memory 50; meanwhile, the control module 30 enables the MCU10 to obtain the decoded first received data from the first memory 101, and enables the decoding module 301 to obtain the demodulated second received data from the third memory 50 for decoding after the MCU10 reads the decoded first received data from the first memory 101, and the decoding module 301 stores the decoded second received data in the first memory 101.

(2) If a memory is disposed between two adjacent pairs of the first module and the second module, the locations of the memory a501 and the memory B502 can be determined by three ways, namely, the first way: a memory is arranged between the cyclic prefix removing and window moving module 304 and the FFT module 303, and is assumed to be a memory A501, and a memory is arranged between the FFT module 303 and the demodulation module 302, and is assumed to be a memory B502; and the second method comprises the following steps: a memory is arranged between the cyclic prefix removing and window moving module 304 and the FFT module 303, and is assumed to be a memory A501, and a memory is arranged between the demodulation module 302 and the decoding module 301, and is assumed to be a memory B502; and the third is that: a memory is arranged between the FFT module 303 and the demodulation module 302, and is assumed as a memory a 501; a memory is arranged between the demodulation module 302 and the decoding module 301, and is assumed as a memory B502; that is, there may be four memories in the data processing flow of the power line carrier communication, which are respectively: a first memory 101, a second memory 102, a memory a501 and a memory B502.

For the first case, as shown in fig. 6D, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, perform analog-to-digital conversion on the received first received data, and perform detection on the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data in the left half of the second memory 102 for the cyclic prefix and window shifting processing, perform the data mapping initialization on the first received data after the cyclic prefix and window shifting processing, and send the first received data after the mapping initialization to the memory a501, because the second memory 102 is a ping-pong structure, when the cyclic prefix window shifting module 304 reads the first received data in the left half of the second memory 102, the AFE40 can still send the second received data after the analog-to-digital conversion to the right half of the second memory 102, thereby ensuring that the data is not lost.

When the control module 30 detects that the operation of the window shifting module 304 for removing cyclic prefix is finished, the control module 30 enables the FFT module 303 to perform FFT operation, and after the FFT module 303 is enabled, the first receiving data after mapping initialization is obtained from the memory a501 to perform FFT operation, and the first receiving data after FFT operation is sent to the memory B502; when the control module 30 detects that the FFT operation in the FFT module 303 is finished, it indicates that the data in the memory a501 has been read empty, the window module 304 capable of removing cyclic prefix performs cyclic prefix removal and window removal processing on the second received data after analog-to-digital conversion acquired from the second memory 102, and sends the processed data to the memory a501 after data mapping initialization, to prepare for FFT operation, meanwhile, the control module 30 also enables the demodulation module 302 to acquire the first received data after FFT operation from the memory B502 for demodulation, the demodulation module 302 sends the demodulated first received data to the decoding module 301, and the decoding module 301 decodes the demodulated first received data and sends the decoded first received data to the first memory 101; when the control module 30 detects that the demodulation operation of the demodulation module 302 is finished, which indicates that the data in the memory B502 is empty, the control module 30 enables the FFT module 303 to obtain the second receiving data after the mapping initialization from the memory a501 for FFT operation, and sends the second receiving data after the operation to the memory B502; when the control module 30 detects that the decoding operation of the decoding module 301 is finished, the control module 30 enables the MCU10 to read the decoded first received data from the first memory 101, until the MCU10 finishes reading the decoded first received data from the first memory 101, and enables the demodulation module 302 to acquire the second received data after the FFT operation from the memory B502 for demodulation.

For the second case, as shown in fig. 6E, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, perform analog-to-digital conversion on the received first received data, and perform detection on the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data in the left half of the second memory 102 for the cyclic prefix and window shifting processing, perform the data mapping initialization on the first received data after the cyclic prefix and window shifting processing, and send the first received data after the mapping initialization to the memory a501, because the second memory 102 is a ping-pong structure, when the cyclic prefix window shifting module 304 reads the first received data in the left half of the second memory 102, the AFE40 can still send the second received data after the analog-to-digital conversion to the right half of the second memory 102, thereby ensuring that the data is not lost.

When the control module 30 detects that the operation of the window-shifting module 304 for removing cyclic prefix is finished, the control module 30 enables the FFT module 303 to perform FFT operation, after the FFT module 303 is enabled, acquires the first received data after mapping initialization from the memory a501 to perform FFT operation, and sends the first received data after FFT operation to the demodulation module 302, and the demodulation module 302 demodulates the first received data after FFT operation and sends the demodulated first received data to the memory B502 under the control of the control module 30; when the control module 30 detects that the FFT operation of the FFT module 303 is finished, the enable de-cyclic prefix window-shifting module 304 acquires the second received data from the second memory 102 to perform de-cyclic prefix and window-shifting processing, and sends the processed data to the memory a501 after initializing data mapping, and when the control module 30 detects that the demodulation operation of the demodulation module 302 is finished, the enable decoding module 301 acquires the demodulated first received data from the memory B502 to decode the first received data and sends the first received data to the first memory 101; when the control module 30 detects that the decoding operation of the decoding module 301 is finished, it indicates that the data in the memory B502 has been read empty, the FFT module 303 is enabled to acquire the second received data after the mapping initialization from the memory a501, perform FFT operation, and then transmit the second received data after the FFT operation to the demodulation module 302, the demodulation module 302 demodulates the second received data after the FFT operation and transmits the second received data to the memory B502, and at the same time, the control module 30 also enables the MCU10 to read the decoded first received data from the first memory 101, until the MCU10 finishes reading the decoded first received data in the first memory 101, the decoding module 301 is enabled to acquire the demodulated second received data from the memory B502 for decoding.

For the third situation, as shown in fig. 6F, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, perform analog-to-digital conversion on the received first received data, and perform detection on the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is filled with the AFE40, the control module 30 enables the control module 304 to read the first received data of the left half in the second memory 102 for the cyclic prefix removal and window shifting processing, perform data mapping initialization on the first received data after the cyclic prefix removal and window shifting processing, and send the first received data after the mapping initialization to the FFT module 303; the control module 30 enables the FFT module 303 to perform FFT operation on the first received data after map initialization, and then stores the first received data after FFT operation in the memory a501, and when the control module 30 detects that the FFT operation of the FFT module 303 is finished, enables the demodulation module 302 to acquire the first received data after FFT operation from the memory a501, perform demodulation operation on the first received data, and then send the first received data to the memory B502; when the control module 30 detects that the demodulation operation of the demodulation module 302 is finished, it indicates that the data in the memory a501 has been read empty, the window module 304 capable of removing cyclic prefix performs the processing of removing cyclic prefix and moving window on the second received data obtained after analog-to-digital conversion from the second memory 102, and sends the second received data after the processing of removing cyclic prefix and moving window to the FFT module 303 after performing data mapping initialization, the FFT module 303 performs FFT operation on the second received data after mapping initialization under the control of the control module 30 and sends the second received data to the memory a501, and at the same time, the control module 30 further enables the decoding module 301 to obtain the demodulated first received data from the memory B502 and send the decoded first received data to the first memory 101 after decoding; when the control module 30 detects that the decoding operation of the decoding module 301 is finished, it indicates that the data in the memory B502 has been read empty, the demodulation module 302 is enabled to acquire the second received data after the FFT operation from the memory a501, demodulate the second received data and send the second received data to the memory B502, and simultaneously the control module 30 also enables the MCU10 to read the decoded first received data from the first memory 101, until the MCU10 finishes reading the decoded first received data in the first memory 101, the decoding module 301 is enabled to acquire the demodulated second received data from the memory B502 and decode the second received data.

(3) A memory is respectively arranged between the three adjacent pairs of the first module and the second module, namely a memory is arranged between the module 304 for removing the cyclic prefix and the FFT module 303, and the memory is also arranged between the FFT module 303 and the demodulation module 302, and a memory is arranged between the demodulation module 302 and the decoding module 301, namely 5 memories are arranged in the data processing flow of the power line carrier communication. The following example seventeenth specifically describes this case.

On the basis of the foregoing embodiments, fig. 7 is a schematic structural diagram of a seventeenth embodiment of the power line carrier communication chip provided in the present invention, and preferably, a fifth memory 105 is disposed between the cyclic prefix removing and windowing module 304 and the FFT module 303, and the fifth memory 105 is also located between the demodulation module 302 and the FFT module 303; a fourth memory 104 is arranged between the demodulation module 302 and the decoding module 301; the cyclic prefix removing and window moving module 304 is configured to obtain received data from the second memory 102 under the control of the control module 30, and send the received data after cyclic prefix removal and window moving to the fifth memory 105; the FFT module 303, configured to obtain received data after cyclic prefix removal and window shifting from the fifth memory 105 under the control of the control module 30, and send the received data after FFT operation to the fifth memory 105; the demodulation module 302 is configured to obtain the FFT-operated received data stored in the fifth memory 105 under the control of the control module 30, and send the demodulated received data to the fourth memory 104; the decoding module 301 is configured to obtain demodulated received data from the fourth memory 104 under the control of the control module 30, and send the decoded received data to the first memory 101.

Specifically, the control module 30 enables the AFE40 to receive the first received data sent by the peer-to-peer coupling circuit from the power line, perform analog-to-digital conversion processing on the received first received data, and perform detection of the synchronization header, so that the processing module at the back end can accurately acquire the first received data; after the control module 30 detects the sync header, the data is stored in the second memory 102, where the second memory 102 is divided into a left half and a right half by using a ping-pong structure, the left half stores the first received data sent by the AFE40, and the right half stores the second received data sent by the AFE40, so as to ensure that the data sent by the AFE40 is not lost; when the left half is full written by the AFE40, the control module 30 enables the control module 304 to read the first received data of the left half in the second memory 102 for the cyclic prefix removal and window shifting processing, perform the data mapping initialization on the first received data after the cyclic prefix removal and window shifting processing, and send the first received data after the mapping initialization to the fifth memory 105; since the second memory 102 is of a ping-pong structure, when the window-moving module 304 reads the first received data in the left half of the second memory 102, the AFE40 can still send the analog-to-digital converted second received data to the right half of the second memory 102, so as to ensure that the data is not lost.

When the control module 30 detects that the operation of the window-shifting module 304 for removing cyclic prefix is finished, the control module 30 enables the FFT module 303 to perform FFT operation, and after the FFT module 303 is enabled, obtains the first received data after mapping initialization from the fifth memory 105 to perform FFT operation, and continuously sends the first received data after FFT operation to the fifth memory 105; then, the control module 30 enables the demodulation module 302 to perform demodulation processing, where the demodulation module 302 uses relative Phase Shift Keying (DBPSK) or Quadrature relative Phase Shift Keying (DQPSK), and the demodulation module 302 stores the demodulated first received data in the fourth memory 104; when the control module 30 detects that the demodulation operation of the demodulation module 302 has ended, which indicates that the data in the fifth memory 105 has been read empty by the demodulation module 302, the control module 30 enables the window removal module 304 to obtain the second received data from the second memory 102 for performing the processing of removing the cyclic prefix and moving the window, and stores the second received data after the processing of removing the cyclic prefix and moving the window into the fifth memory 105 after performing mapping initialization, and when the control module 30 detects that the window removal module 304 has ended processing of the second received data, the control module 30 enables the FFT module 303 to obtain the second received data after the mapping initialization from the fifth memory 105 for performing the FFT operation processing, and stores the second received data after the FFT operation processing into the fifth memory 105 to prepare for the demodulation processing; the control module 30 enables the decoding module 301 to acquire the demodulated first received data from the fourth memory 104 for decoding, and stores the decoded first received data into the first memory 101; when the control module 30 detects that the decoding operation of the decoding module 301 is finished, which indicates that the data in the fourth memory 104 has been read empty, the control module 30 enables the demodulation module 302 to acquire the second received data after the FFT operation from the fifth memory 105 for demodulation processing, and stores the second received data after the demodulation processing into the fourth memory 104; meanwhile, the control module 30 enables the MCU10 to obtain the decoded first received data from the first memory 101, until the MCU10 finishes reading the decoded first received data in the first memory 101, the decoding module 301 obtains the demodulated second received data from the fourth memory 104 for decoding, and the decoding module 301 stores the decoded second received data in the first memory 101.

Further, on the basis of the embodiment shown in fig. 7, preferably, the OFDM processing module 20 further includes: a channel estimation module 305, where the channel estimation module 305 is configured to perform channel estimation operation on the received data after FFT operation, and send an estimation operation value to the demodulation module 302; a sixth memory 106 is arranged between the channel estimation module 305 and the demodulation module 302, and a fifth memory 105 is also arranged between the FFT module 303 and the channel estimation module 305; the channel estimation module 305 is configured to obtain the received data after the FFT operation from the fifth memory 105 under the control of the control module 30, and send the channel estimation operation value to the sixth memory 106.

Specifically, after the FFT-operated first received data is stored in the fifth memory 105, the control module 30 enables the demodulation module 302 and the channel estimation module 305 to acquire the FFT-operated first received data from the fifth memory 105, the channel estimation module 305 performs channel estimation on the FFT-operated first received data and sends the channel estimation value to the sixth memory 106, the demodulation module 302 acquires the FFT-operated first received data from the fifth memory 105 and acquires the channel estimation value of the first received data from the sixth memory 106, demodulates the acquired first received data according to the channel estimation value, and ensures the accuracy of data demodulation, and then the demodulation module 302 sends the demodulated first received data to the fourth memory 104.

The power line carrier communication chip provided by this embodiment stores data processed by each module by respectively setting the memories between the adjacent modules, and by setting each memory, the next frame of data does not need to wait until the previous frame of data is processed, that is, the operations between the modules included in the OFDM processing module are independently completed, which effectively improves the processing speed of the chip and also saves the hardware resources of each module.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power line carrier communication chip, comprising: the system comprises a microprocessor MCU, a control module, an orthogonal frequency division multiplexing OFDM processing module and an analog front end AFE; a first memory is arranged between the MCU and the OFDM processing module, and a second memory is arranged between the OFDM processing module and the AFE;

or,

2. The chip of claim 1, wherein the OFDM processing module comprises: the device comprises a coding module, a modulation module, an Inverse Fast Fourier Transform (IFFT) module and a cyclic prefix windowing module;

3. The chip of claim 2, wherein the OFDM processing module includes a coding module, a modulation module, an IFFT module, and a cyclic prefix windowing module, and a third memory is disposed between at least one pair of adjacent first and second modules;

4. The chip of claim 2, wherein a fourth memory is disposed between the encoding module and the modulation module; a fifth memory is arranged between the modulation module and the IFFT module; a sixth memory is arranged between the IFFT module and the cyclic prefix windowing module;

5. The chip of claim 4, wherein the modulated transmission data stored in the fifth memory is mapped into the sixth memory; the IFFT module is configured to obtain the modulated transmission data from the sixth memory under the control of the control module.

6. The chip of claim 1, wherein the OFDM processing module comprises: the device comprises a cyclic prefix removing and window shifting module, a Fast Fourier Transform (FFT) module, a demodulation module and a decoding module;

7. The chip of claim 6, wherein the OFDM processing module comprises a cyclic prefix de-windowing module, an FFT module, a demodulation module, and a decoding module, and a third memory is disposed between at least one pair of adjacent third and fourth modules;

8. The chip of claim 6, wherein a fifth memory is disposed between the de-cyclic prefix window-shifting module and the FFT module, and the fifth memory is also disposed between the demodulation module and the FFT module; a fourth memory is arranged between the demodulation module and the decoding module;

9. The chip according to any one of claims 6-8, wherein the OFDM processing module further comprises: and the channel evaluation module is used for carrying out channel evaluation operation on the received data after the FFT operation and sending an evaluation operation value to the demodulation module.

10. The chip of claim 9, wherein a sixth memory is disposed between the channel estimation module and the demodulation module, and a fifth memory is also disposed between the FFT module and the channel estimation module;