CN104242956B

CN104242956B - Based on the random high-performance low complex degree ldpc decoder for calculating

Info

Publication number: CN104242956B
Application number: CN201410437444.1A
Authority: CN
Inventors: 陈赟; 张启晨; 吴迪; 曾晓洋
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2014-09-01
Filing date: 2014-09-01
Publication date: 2017-07-07
Anticipated expiration: 2034-09-01
Also published as: CN104242956A

Abstract

It is specially a kind of based on the random high-performance low complex degree ldpc decoder for calculating the invention belongs to radio digital communication and broadcast technology field.The decoder supports IEEE 802.16（WiMAX）Standard, its structure includes：It is adapted to IEEE 802.16（WiMAX）In standard（576,480）The look-up table of the NDS coefficients of check matrix（LUT）Array, the VN arrays with EM function of initializing, and the saturated counters with calculating posterior information and SM.The decoder while contemporary communication standards throughput is met, can effectively reduce the line complexity of decoder using the random Information Communication decoding algorithm for calculating, and improve chip area utilization rate；The decoder is directed to specific check matrix simultaneously, chooses suitable NDS parameters and improves random computing hardware structure, reduces initialization time, accelerates convergence rate, so as to improve its random decoding performance for calculating, reduces decoding time, improves throughput.

Description

Based on the random high-performance low complex degree ldpc decoder for calculating

Technical field

The invention belongs to radio digital communication and broadcast technology field, and in particular to a kind of based on the random high-performance for calculating Low complex degree ldpc decoder.

Background technology

Since the nineties in 20th century, human society enters a digitlization, information-based fast-developing stage.Due to society Can environment it is different, information science technology is developed rapidly so that in social each field continue to bring out various digital communications Technology, and people pursue also growing to the reliable communication system of high speed.Encoding and decoding are carried out by channel information, can be right Information with interchannel noise carries out error correction, it is ensured that information it is safe and reliable.Wherein, LDPC code（Low density parity check code）It is A kind of high performance code encoding/decoding mode, performance can approach shannon limit.LDPC code by doctor Gallager 1962 propose, but It is that, due to IC manufacturing level backward at that time, LDPC code never has the attention for obtaining academia.Until 1997, Mackay and Neal just excavate LDPC code again, and hereafter LDPC code is increasingly becoming main force's code encoding/decoding mode of channel error correction.

LDPC code has coding gain high relative to other error correcting codes, and performance is good, the decoding various advantages such as throughput is high, existing Stage many communication standards all carry out channel error correction, such as WiMAX, WLAN and DTV of wireless access using LDPC code The communication standards such as DVB-S2, DTMB use LDPC encoding and decoding.The decoder circuit of LDPC code has decoding circuit simple, and In the optical communication systems such as the advantages of row degree is high, it is adaptable to high-throughput, especially 100Gbps.

As the code length that LDPC code is used is more and more long, the scale of check matrix is also increasing.Accordingly, LDPC The circuit scale of decoder is also increasing.With IEEE 802.3an（10GBASE-T）As a example by, its check matrix scale is （2048,1723）, that is to say, that in ldpc decoder, VN（Variable Node, variable node）Number be 2048, And the dimension of each VN is 6, it is assumed that each information is quantified as 4bit, such VN and CN（Check Node, check-node） Between line altogetherBar.Like this, the line complexity in decoder is just excessively complicated, And substantial amounts of chip area is taken, bring extra power consumption and reduce the working frequency of chip.Popular in smart mobile phone Today, excessive chip area and too high power consumption is clearly intolerable.

Random calculating is a kind of new method for realizing ldpc decoder.Random calculating solves in probability domain to LDPC code Code, by a series of random Bernoulli sequences, is converted into a string " 01 " sequences, in the sequence by the probable value of channel information The desired value of " 1 " number just represents the probability of channel information.So, with traditional Min-Sum decoded in log-domain Scheduling algorithm is contrasted, it is random calculate can by addition, compare wait complexity mathematical operation be converted to or, XOR etc. simply patrols Computing is collected, the complexity of VN and CN declines to a great extent.Also, due to only needing to process a bit every time, so wiring quantity will Decline corresponding quantization multiple, the line complexity than 10GBASE-T decoders described above can be descended toBar, reduces 4 times.Thus, random calculating is a kind of decoding algorithm of very promising LDPC code.

The content of the invention

It is an object of the invention to provide a kind of based on the random high-performance low complex degree ldpc decoder for calculating.

The ldpc decoder that the present invention is provided, based on random computational algorithm, is carried out in probability domain using belief propagation algorithm Decoding.The decoder supports IEEE 802.16（WiMAX）In standard（576,480）Check matrix.Its structure includes：Properly IEEE 802.16（WiMAX）In standard（576,480）The NDS of check matrix（Noise dependent scaling, according to Rely the coefficient of diminution in noise）The look-up table of coefficient（LUT）Array, with EM（Edge Memory, edge memory）Initialization The Variable Node of function（VN）Array, and with calculating posterior information S and SM（S Memory, S memories）It is full And counter；Wherein, the LUT arrays will quantify to turn into corresponding probable value with noisy channel information, and NDS coefficients will be general Rate value tapers to rational scope；The VN array computations posterior information and pass to saturated counters and corresponding Check Nodes（CN）Array, the time required to initialization EM is to reduce decoding；The saturated counters are used for recording the posteriority letter of VN transmission The probability trend of breath, and correspondence carries out differentiation output firmly as decoding output.SM can be used to the posteriority letter of output before collecting Breath value, can accelerate convergence rate.

In the present invention, the LUT arrays have 576 LUT, correspondence code length 576.Each LUT is according to formula The corresponding probable value of channel information is calculated, whereinRepresent with noisy channel information.After calculating corresponding probable value, need Certain diminution is carried out to probable value according to NDS parameters, so accelerate convergence rate.NDS parameters are different to various criterion All it is different for check matrix, it is necessary to be determined by Computer Simulation.By emulation, the NDS parameters of the decoder are 7.5。

In the present invention, the VN arrays, according to the difference of dimension, letter are tested before being returned comprising the input of several detection channels and CN Breath whether identical structure, each construction module be used for collecting storage with EM before identical information, and differing When output EM intermediate storages value as output, accelerate convergence rate and improve decoding performance.VN's in the decoder EM carries function of initializing, in a cycle that new channel information is input into, first bit quantified using channel information The whole EM of value filling is used as initialization value.So, decoding performance will not both be reduced, moreover it is possible to further speed up convergence rate.

In the present invention, the saturated counters are the counters for having bound.The counter used in the decoder it is upper Lower limit is（I.e. the upper limit is 7, and lower limit is -7）.The input of saturated counters is external information R, in input source plus certain Gate circuit network calculate posterior information S, as input.Compared with external information R is directly inputted, the sign to probability of S is more Plus it is accurate, decoding performance can be improved.There is a small-sized gate circuit network to calculate S outside counter input.With the addition of and The similar SM of EM function and structures, stores effective S values, and is exported when S is invalid, accelerates convergence rate.

The ldpc decoder that the present invention is provided, supports IEEE 802.16（WiMAX）Standard.The decoder is using random meter The Information Communication decoding algorithm of calculation, while contemporary communication standards throughput is met, can effectively reduce the line of decoder Complexity, improves chip area utilization rate.The decoder is directed to specific check matrix simultaneously, chooses suitable NDS parameters simultaneously Random computing hardware structure is improved, initialization time is reduced, convergence rate is accelerated, its random decoding for calculating is improve Performance, reduces decoding time, improves throughput.

Brief description of the drawings

Fig. 1 is the random high-performance low complex degree ldpc decoder structured flowchart for calculating of the invention.

Fig. 2 is the VN basic block diagrams of the random high-performance low complex degree ldpc decoder for calculating of the invention.

Fig. 3 is the EM initializing circuits of the random high-performance low complex degree ldpc decoder for calculating of the invention.

Fig. 4 is the saturated counters importation electricity of the random high-performance low complex degree ldpc decoder for calculating of the invention Road.

Fig. 5 is the VN structure charts of the random high-performance low complex degree ldpc decoder for calculating of the invention.

Fig. 6 is the SM and saturated counters connection figure of the random high-performance low complex degree ldpc decoder for calculating of the invention.

Fig. 7 is the random high-performance low complex degree ldpc decoder performance simulation figure for calculating of the invention.

Fig. 8 is the random high-performance low complex degree ldpc decoder difference NDS performance parameters analogous diagrams for calculating of the invention.

Specific embodiment

The schematic block for being the designed ldpc decoder based on the random high-performance low complex degree for calculating shown in Fig. 1 Figure.It is an important module in each dotted line frame.Including LFSR, altogether including 24 randomizers, use To produce random number, randomization is carried out to probable value；LUT modules, altogether including 576 look-up tables, for channel information is converted It is corresponding probable value, and according to NDS parameters, probable value is reduced accordingly；VN modules, comprising 576 VN, receive and From the prior information of CN, external information and posterior information are calculated, external information passes to corresponding CN modules, and posterior information passes to right The saturated counters answered（It is included in VN）.Basic structure is as shown in Figure 2；CN modules, comprising 96 CN, receive outer from VN Information, calculates prior information, and pass to corresponding VN modules；Verification（Check）Module, comprising 96 check, basic structure It is consistent with CN, the hard decision output from saturated counters is received, then judge whether successfully decoded.

The structure of the EM that initialization VN modules are added based on the random decoder for calculating proposed by the present invention, such as Fig. 3 institutes Show.In initialization,1 is set to, thenInput can just be directly passed to SET and CLR ports, EM is carried out just Beginningization；Initialization continues a cycle；After initialization terminates,0 is set to, then SET and CLR are set to 0 and 1, EM respectively Normal work.The method of initialization EM of traditional one is so contrasted, the initial method can be saved substantial amounts of initial Change time, the result that emulation is obtained can save 19.98% decoding time.

It is proposed by the present invention for IEEE 802.16（WiMAX）In standard（576,480）The choosing of check matrix NDS parameters Take.The selection of NDS parameters mainly passes through the function curve of computer simulation decoder, so as to find out the parameter being best suitable for Value.It is the function curve of the decoder under different NDS parameters shown in Fig. 6, it can be seen that 7.5 is most suitable selection.

The input end structure of the saturated counters with posterior information calculation and SM structures proposed by the present invention, such as Fig. 4 institutes Show.By taking the counter of 3 inputs as an example.Whether three inputs of electric circuit inspection of three gate compositions are identicals, if identical, 0 is then exported, if there is a difference, that just exports 1.Update controls whether to update the content in SM, and 0 just updates, and 1 then not more Newly.If identical, posterior information is directly inputted to saturated counters, if it is different, then randomly choosing one from SM, is input to full In the middle of counter.Like this, it is ensured that in saturated counters is all posterior information, convergence rate can be accelerated and is carried Decoding performance high.

VN structures proposed by the invention, as shown in Figure 5.Due to（576,480）Arranged in matrix has three kinds of different feelings again Condition, respectively 2,3,4, their structure is substantially the same, and the number being only input into is different, so here only by taking the VN of 2 inputs as an example. It is the sub- VN in a VN in Fig. 5, with the presence of the sub- VN of its row weight number in a VN.The main structure body of sub- VN is included by one With door, the judging an of NAND gate and OR gate composition be input into whether identical structure and an EM structure of 64bit.Non- When initialization, the value of ini_i is 0, is CN feedacks and the letter from after comparator quantization with door and NAND gate input Road information, when two inputs are identical, two output of door necessarily one " 1 " and one " 0 ", the output of such OR gate Necessarily " 1 "；And two inputs it is different when, it is all " 0 " that the outputs of two doors are inevitable, and the output of such OR gate is necessarily " 0 ".Or Whether one data selector of output control of door, represents the value for exporting channel.When selective value is " 1 ", data Selector directly exports the value of channel.The effect of the EM structures of 64bit virtual value produced before being storage.Due to random meter Calculation needs virtual value, and invalid value is harmful, can cause decoding it is locked, so storage before virtual value and obtaining invalid Exported during value, exactly solve a locked effectively method.EM is general, and shift register again is constituted, and data selection of arranging in pairs or groups Device array randomly select the function of value.When ini_i is " 0 ", and during the logic door section two identical values of input of top, The input of update ports is just " 1 ", and the value is input to the in ports of EM simultaneously, and EM will be shifted and be stored the value；Work as gate When part is input into two different values, the input of update ports is just " 0 ", and new value would not be stored in EM.Meanwhile, Random ports are input into the random value of 0-63 always, and export corresponding bit from out ports, and when being input into different, the value is just Can export.Lower section initialization module is exactly array as shown in Figure 3, and its major function is exactly a cycle in decoding It is interior, EM is integrally refreshed as first channel value of input.It is known that channel information error is after all minority, mostly Number information is correct.So the first comparator output major part after quantifying is also correct, EM is initialized with this value The time of the initialization of the previous position that can be reduced, the refreshing that the EM for initializing mistake also can be quickly into right value, so this Individual method can be to accelerate convergence rate.Initialization array has 64 such as structures of Fig. 3, one in each correspondence EM Bit, when ini_i is " 1 ", rst_n is also " 1 ", and this is that in ports can just be input into the information of oneself, by control The value of EM is refreshed in SET and CLR ports.

Counter structure of the invention is as shown in Figure 6.Mainly it is made up of the saturated counters that SM modules and size are 7, often Individual VN nodes have such structure.The structure of SM modules by the VN of 3 inputs as shown in figure 4, illustrated here.The structure of SM It is consistent with EM, all it is made up of shift register and data selector array.Whether XOR gate array judges three identical, phases of input Just output " 1 ", to the update ports of SM, obtains posterior information S, and be stored in SM structures if.When 3 outputs are different, Output " 0 " to the update ports of SM, SM randomly chooses the counting of the bit output in SM according to the random information of input In device.The input of saturated counters is Jia 1 for " 1 ", then subtracts one when being input into as " 0 ".Maximin is positive and negative 7.Sign bit is made Differentiate that result is exported to verification for hard（check）Module is verified, and illustrates that decoding is correct if whole results are " 0 ".

Claims

1. a kind of high-performance low complex degree ldpc decoder, it is characterised in that based on random computational algorithm, application is put in probability domain Letter propagation algorithm enters row decoding；The decoder supports IEEE 802.16（WiMAX）In standard（576,480）Check matrix；Its Structure includes：It is adapted to IEEE 802.16（WiMAX）In standard（576,480）The look-up table LUT of the NDS coefficients of check matrix Array, the VN arrays with EM function of initializing, and the saturated counters with calculating posterior information and SM；Wherein：

The LUT arrays will quantify to turn into corresponding probable value with noisy channel information, and NDS coefficients taper to probable value Rational scope；The VN array computations posterior information and posterior information is passed into saturated counters, external information is passed to Corresponding CN arrays, the time required to initialization EM is to reduce decoding；The saturated counters are remembered by corresponding plus-minus counting The probability trend of the posterior information of record VN transmission, and correspondence carries out differentiation output firmly as decoding output；SM can be with before collecting For the posterior information value for exporting, to accelerate convergence rate；

Here, NDS refers to IEEE 802.16（WiMAX）In standard（576,480）The reduction for depending on noise of check matrix Coefficient, VN refers to variable node, and CN refers to check-node, and EM refers to edge memory, and SM refers to posterior information S storages Device.

2. high-performance low complex degree ldpc decoder according to claim 1, it is characterised in that：The LUT arrays, have 576 LUT, correspondence code length 576；Each LUT is according to formulaThe corresponding probable value of channel information is calculated, wherein Represent with noisy channel information；After calculating corresponding probable value, certain contracting is carried out to probable value according to NDS parameters It is small so that the probable value of all input values accelerates convergence rate in a certain size scope；NDS parameters to various criterion not With being all different for check matrix, determined by Computer Simulation.

3. high-performance low complex degree ldpc decoder according to claim 2, it is characterised in that：The VN arrays, according to The difference of dimension, comprising it is several detection channels input and CN passback before test information whether identical structure, if identical, with regard to conduct External information is exported；Each construction module carries identical external information information before an EM is used for collecting storage, and is differing When output EM intermediate storages value as output, it is before the information for so ensureing each VN outputs is all or now identical Information, with accelerate convergence rate and improve decoding performance；The EM of the VN in the decoder carries function of initializing, in new letter The a cycle of road information input, first bit value quantified using channel information fills whole EM as initialization value.

4. high-performance low complex degree ldpc decoder according to claim 3, it is characterised in that：The saturated counters have Bound；The input of saturated counters is external information R, adds a gate circuit network in input source to calculate posterior information S, as input；There is a gate circuit network outside counter input to calculate S, add the SM similar with EM function and structures, Effective S values are stored, and is exported when S is invalid.