CN104241387B - A kind of bigrid groove MOS unit and preparation method thereof - Google Patents
A kind of bigrid groove MOS unit and preparation method thereof Download PDFInfo
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- CN104241387B CN104241387B CN201410532499.0A CN201410532499A CN104241387B CN 104241387 B CN104241387 B CN 104241387B CN 201410532499 A CN201410532499 A CN 201410532499A CN 104241387 B CN104241387 B CN 104241387B
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 49
- 150000002500 ions Chemical class 0.000 claims description 10
- 210000002105 tongue Anatomy 0.000 claims description 4
- 210000004027 cell Anatomy 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005574 cross-species transmission Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention provides a kind of bigrid groove MOS units and preparation method thereof, wherein bigrid groove MOS unit includes first grid and its first grid insulating layer, wherein the first grid insulating layer is silicon nitride layer.Using the above scheme, oxygen is isolated using silicon nitride layer in the present invention, is conducive to prevent from aoxidizing, and simplification of flowsheet, reduces defect, promotes yield, has very high market application value.
Description
Technical field
The present invention relates to bigrid groove MOS technologies, more particularly to, a kind of bigrid groove MOS unit and its system
Preparation Method.
Background technology
General bigrid（dual gate）Groove MOS（Metal-Oxide-Semiconductor, metal oxide half
Conductor tube）After formation of the groove, the structure in bigrid trench MOS structure face under the metal layers, that is, the oxide layer after being formed,
As gate insulating layer, as shown in Figure 1, including exhausted between silicon substrate 101, first grid oxide layer 102, first grid 103, grid
Edge oxide layer 104, second grid oxide layer 105 and second grid 106.
For example, Chinese patent 201010104006.5 disclose it is a kind of foreign ion is doped into two grid method,
Including:The grid that the first conductive type foreign ion is doped into the semiconductor substrate with first area and second area is led
Electric layer, wherein implementing the doping using concentration gradient so that the doping concentration on grid conducting layer top is dense higher than the doping of lower part
Degree, using the mask for exposing a part for grid conducting layer in second area, the second conductive type foreign ion is doped into
The part of the grid conducting layer of second area, and by implement heat treatment come spread the first conductive type foreign ion and this second
Conductive-type impurity ion.
For another example, Chinese patent 201110142449.8 proposes a kind of dual gate oxide groove of tape channel cut-off groove
MOSFET and three or four masking process.The semiconductor devices contains multiple gate electrodes, and it is active to be formed at semiconductor substrate
In groove in area.First grid slideway is formed in the substrate, and is electrically connected on gate electrode, wherein first grid slideway
Surround active area.Second grid slideway is connected on first grid slideway, and between active area and cut-off region.Cut-off knot
Structure surrounds the first and second gate runners and active area.Cut-off structure, which contains, is covered with leading in the groove of insulant in substrate
Electric material, wherein cut-off structure is shorted to the source electrode or body layer of substrate, to constitute the tunnel end points of device.
For another example, Chinese patent 201410065951.7 discloses one kind and being used to prepare igbt（IGBT）Device
The method of part includes：1）Semiconductor substrate is prepared, the semiconductor of the second conduction type is located at the first conductive type epitaxial layer
On substrate；2）Using a gate trench masks, first groove and second groove are opened, a gate insulating layer is then prepared,
Gasket channel is used in combination polysilicon layer to fill groove, forms first groove grid and second groove grid；3）Inject the first conductive-type
The dopant of type forms top heavily doped layer in the epitaxial layer；And 4）Planar gate is prepared above first groove grid, profit
With injection mask, bulk doped object and source dopant are injected, body zone and source electrode are formed in the adjacent top surface of semiconductor substrate
Area.
But existing bigrid groove MOS, in process fabrication steps complexity, the prior art uses silica as insulation
Layer in oxidation process below, in order to avoid oxidation, can carry out very big complexity since oxygen cannot be isolated in silica to process bands,
Generate defect.
Therefore, the prior art is defective, needs to improve.
Invention content
Technical problem to be solved by the invention is to provide a kind of new bigrid groove MOS units and preparation method thereof.
Technical scheme is as follows：A kind of bigrid groove MOS unit comprising first grid and its first grid
Insulating layer, wherein the first grid insulating layer is silicon nitride layer.
Preferably, the silicon nitride layer is deposited in first grid oxide layer.
Preferably, the first grid is arranged in the silicon nitride layer package.
Preferably, between the first grid and second grid be arranged grid between insulating oxide.
Preferably, the first grid is less than the second grid.
The another technical solution of the present invention is as follows：A kind of preparation method of bigrid groove MOS unit comprising following step
Suddenly：First grid insulating layer is formed using silicon nitride layer.
Preferably, deposit silicon nitride layer after the first grid oxide layer of groove is formed.
Preferably, after formation of the groove, one layer very thin of first grid oxide layer is only grown, then deposit silicon nitride layer,
To form first grid insulating layer.
Preferably, between the first grid and second grid be arranged grid between insulating oxide.
Preferably, the first grid is less than the second grid.
Using the above scheme, oxygen is isolated using silicon nitride layer in the present invention, is conducive to prevent from aoxidizing, and simplifies technique stream
Journey reduces defect, promotes yield, has very high market application value.
Description of the drawings
Fig. 1 is the schematic diagram of the prior art；
Fig. 2 is the schematic diagram of one embodiment of the present of invention；
Fig. 3 to Figure 11 is respectively the process flow diagram of one embodiment of the present of invention.
Specific implementation mode
To facilitate the understanding of the present invention, in the following with reference to the drawings and specific embodiments, the present invention will be described in more detail.
The preferred embodiment of the present invention is given in this specification and its attached drawing, still, the present invention can be in many different forms
To realize, however it is not limited to this specification described embodiment.Make to the present invention on the contrary, purpose of providing these embodiments is
Disclosure understanding it is more thorough and comprehensive.
It should be noted that when a certain element is fixed on another element, including that the element is directly fixed on this is another
A element, or the element is fixed on another element by least one other elements placed in the middle.When an element connects
It connects another element, including the element is directly connected to another element, or the element passed through at least one placed in the middle
Other elements be connected to another element.
One embodiment of the present of invention is a kind of bigrid groove MOS unit comprising first grid and its first grid
Insulating layer, wherein the first grid insulating layer is silicon nitride layer.Preferably, the silicon nitride layer is deposited on first grid oxygen
Change on layer.For another example, the first grid is arranged using chemical vapour deposition technique.
Preferably, the thickness of the silicon nitride layer between the first grid and the first grid oxide layer, is described
The 50% to 250% of the thickness of first grid oxide layer；In this way, advantageously reducing switching loss.For example, the first grid with
The thickness of silicon nitride layer between the first grid oxide layer, be the first grid oxide layer thickness 50%, 60%,
70%, 80%, 90%, 100%, 110%, 120%, 130%, 150%, 180%, 200%, 220% or 250%；Preferably, in the first grid
The thickness of silicon nitride layer between pole and the first grid oxide layer, be the first grid oxide layer thickness 150% to
200%.In this way, will not additional effect conducting resistance.Preferably, the first grid is the polysilicon of polishing treatment；For another example, institute
It is the polysilicon with laminated construction to state first grid；For another example, the first grid is cylinder；Alternatively, the first grid
For cuboid, particularly, the first grid is cube.Corresponding, shape and the size of the second grid are equal to institute
First grid is stated, for another example, the shape of the second grid is equal to the first grid, also, the volume of the second grid
More than the first grid.
Preferably, the first grid is arranged in the silicon nitride layer package.Preferably, the silicon nitride layer at least partly wraps
Wrap up in the setting first grid.Preferably, the first grid is arranged in the silicon nitride layer portions package.Alternatively, the nitridation
The fully wrapped around setting first grid of silicon layer.For another example, one layer of silicon nitride layer is set outside the first grid, thickness is uniform
Setting.For example, the thickness of the thickness of silicon nitride layer insulating oxide between the grid；For another example, the silicon nitride layer
The sum of the thickness of thickness thickness of insulating oxide and the first grid oxide layer between the grid.
Preferably, between the first grid and second grid be arranged grid between insulating oxide.The first grid is minimum
In the second grid.Preferably, insulating oxide between the first grid and the grid is arranged in the silicon nitride layer package
Layer.Preferably, the silicon nitride layer wraps up respectively is arranged insulating oxide between the first grid and the grid.For another example,
Integrally insulating oxide between the first grid and the grid is arranged in package to the silicon nitride layer, i.e., the described silicon nitride layer is whole
Insulating oxide between the first grid and the grid is arranged in body package.Preferably, the second grid is polishing treatment
Silicon or polysilicon；For another example, the second grid is the silicon structure with laminated construction；For another example, the second grid is circle
Cylinder；Alternatively, the second grid is cuboid, particularly, the second grid is cube.Preferably, the second gate
The height of pole is less than the height of the first grid.For another example, the volume of the second grid is equal to the volume of the first grid.
Preferably, what the first grid oxide layer abutted the silicon nitride layer also sets up several grooves, Ruo Gansuo on one side
That states that silicon nitride layer abuts the first grid oxide layer also sets up several tongues on one side, and each tongue corresponds to a groove, this
Sample can enhance the stability of the silicon nitride layer to a certain extent.For another example, first grid oxide layer is aoxidized with second grid
Layer connection setting.Preferably, the first grid insulating layer is cylindrical shape；Alternatively, the first grid insulating layer is truncated cone-shaped,
For example, the area of its lower surface is less than the area of upper surface.For another example, in first grid oxide layer be arranged silicon nitride layer and
Silicon nitride layer is set between grid on insulating oxide；Preferably, silicon nitride layer deposit is once to be deposited directly on the twice
It is another time to be deposited between grid on insulating oxide, that is, the deposit silicon nitride in first grid oxide layer on one grid oxic horizon
Layer and the deposit silicon nitride layer on insulating oxide between grid.Preferably, the height of the truncated cone-shaped is the first grid
The 120% to 180% of height.
For example, a kind of bigrid groove MOS unit comprising silicon substrate, first grid oxide layer, silicon nitride layer, first
Insulating oxide, second grid oxide layer and second grid between grid, grid.As shown in Fig. 2, a kind of bigrid groove MOS list
Member comprising insulating oxide 104, second grid between silicon substrate 101, first grid oxide layer 102, first grid 103, grid
Oxide layer 105 and second grid 106, further include silicon nitride layer 201.For example, flat shape is arranged in the groove, it is preferred that institute
It states flat shape and is parallel to ground level；For example, the groove is cylindrical or cuboid, i.e. its first grid oxide layer connects
Contacting surface is plane, and its is parallel rather than be obliquely installed, and is easy to grow the first grid oxide layer in this way.For another example, the groove
The groove body, such as S-shaped, circle or C-shaped etc. of several preset shapes is arranged in bottom etching, and for another example, spiral shell is arranged in the groove wall portion
Line；In this way, being suitble to special application environment, be conducive to the physical strength of oxidation reinforced layer to a certain extent.Preferably, several
Groove connection setting, for another example, the first grid oxide layer connection setting of each groove.
Preferably, first grid is arranged with second grid Doped ions；Preferably, the doping concentration of second grid is higher than the
The doping concentration of one grid；Preferably, it is formed on surface and mixes low-resistance grid again.For example, by first grid and second gate
Pole is divided into several regions from inside to outside, and the same ion of different energy dose is injected in each region, wherein the energy of interior zone
Dosage is more than the energy dose of perimeter；Alternatively, the energy dose of perimeter is more than the energy dose of interior zone.Or
Person, the phase different ion of each region injection identical energy dosage.For another example, first grid and second grid are divided into several regions,
Innermost layer region is round or oval, outer to be arranged several circles, i.e. annular region, including circular annular region or ellipse annulus
Domain, from innermost layer region to each annular region, the identical or phase different ion of identical or different energy dose is injected in each region.Again
Such as, the energy dose of interior zone is more than the energy dose of perimeter, also, its energy is arranged according to the area discrepancy in region
The difference of dosage.Preferably, the product of the area Yu its energy dose in each region is a special value, the certain number in each region
It is worth equal setting.
Another embodiment of the present invention is as follows：A kind of preparation method of bigrid groove MOS unit comprising following step
Suddenly：First grid insulating layer is formed using silicon nitride layer.Preferably, deposit silicon nitride after the first grid oxide layer of groove is formed
Layer.Preferably, after formation of the groove, one layer very thin of first grid oxide layer is only grown, then deposit silicon nitride layer, to be formed
First grid insulating layer.For example, the very thin first grid oxide layer, height is nanometer scale；For example, the first grid
The height of pole oxide layer is 0.1 to 1 nanometer；For another example, the height of the first grid oxide layer is 1 to 2 nanometer；For another example, described
The height of first grid oxide layer is 2 to 10 nanometers；For another example, the height of the first grid oxide layer is 10 to 50 nanometers；Again
Such as, the height of the first grid oxide layer is 50 to 200 nanometers；For another example, the height of the first grid oxide layer be 0.5 to
1.5 microns etc.；And so on.
Preferably, between the first grid and second grid be arranged grid between insulating oxide.The first grid is minimum
In the second grid.Preferably, the silicon nitride layer wraps up insulating oxide between the first grid and the grid.Example
Such as, a kind of preparation method of bigrid groove MOS unit, is used to prepare bigrid groove MOS list described in any of the above-described embodiment
Member.For another example, a kind of preparation method of bigrid groove MOS unit, is used to prepare bigrid groove described in any of the above-described embodiment
MOS cell comprising following steps：First grid insulating layer is formed using silicon nitride layer.
For another example, a kind of preparation method of bigrid groove MOS unit, includes the following steps：Etching groove, groove oxidation,
Silicon nitride deposition, first grid deposit, first grid, which returns, to be carved, and oxide layer aoxidizes between first grid, silicon nitride etch and side oxygen
Change layer removal, the oxidation of second grid oxide layer, second grid deposits back quarter.The flow of its each step is sequentially and obtained double
Gate trench MOS cell as shown in Fig. 3 to Figure 11, is described as follows respectively：Etching groove waits for as shown in figure 3, obtaining having
The silicon substrate of the groove of processing；Groove aoxidizes as shown in figure 4, an oxide layer, i.e. first grid oxide layer is arranged in trench wall；Nitrogen
SiClx deposits as shown in figure 5, trench oxide layer inner wall deposit silicon nitride layer；First grid deposits as shown in fig. 6, deposit spill-over ditch
Slot；First grid, which returns, to be carved as shown in fig. 7, returning for use first grid of residue after quarter；Oxide layer oxidation is such as Fig. 8 institutes between first grid
Show, obtains insulating oxide between grid；Silicon nitride etch and the removal of side oxide layer for second grid as shown in figure 9, reserve conjunction
Suitable space；The oxidation of second grid oxide layer is as shown in Figure 10, and second grid oxygen is obtained on the inner wall of the remainder of groove
Change layer；Second grid deposits back quarter as shown in figure 11, to realize second grid.
Further, the embodiment of the present invention further includes that each technical characteristic of the various embodiments described above is combined with each other formation
Bigrid groove MOS unit and preparation method thereof.
It should be noted that above-mentioned each technical characteristic continues to be combined with each other, the various embodiments not being enumerated above are formed,
It is accordingly to be regarded as the range of description of the invention record；Also, for those of ordinary skills, it can add according to the above description
To improve or convert, and all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (5)
1. a kind of bigrid groove MOS unit comprising first grid and its first grid insulating layer, second grid and its second
Grid oxic horizon, which is characterized in that the first grid insulating layer is silicon nitride layer；
The thickness of silicon nitride layer between the first grid and first grid oxide layer is the first grid oxide layer
The 150% to 200% of thickness；
What the first grid oxide layer abutted the silicon nitride layer also sets up several grooves on one side, and several silicon nitride layers are adjacent
Connect the first grid oxide layer also sets up several tongues on one side, and each tongue corresponds to a groove；
The first grid oxide layer is connected to setting with second grid oxide layer；
First grid is arranged with second grid Doped ions；The doping concentration of second grid is higher than the doping concentration of first grid,
Second grid is located on first grid, mixes low-resistance grid again to be formed in the bigrid groove MOS cell surface.
2. bigrid groove MOS unit according to claim 1, which is characterized in that the silicon nitride layer is deposited on the first grid
In the oxide layer of pole.
3. bigrid groove MOS unit according to claim 2, which is characterized in that described in the silicon nitride layer package setting
First grid.
4. bigrid groove MOS unit according to claim 3, which is characterized in that the first grid and second grid it
Between setting grid between insulating oxide.
5. bigrid groove MOS unit according to claim 4, which is characterized in that the first grid is less than described second
Grid.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320753A (en) * | 2007-05-29 | 2008-12-10 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN204088328U (en) * | 2014-10-11 | 2015-01-07 | 王金 | A kind of novel bigrid groove MOS unit |
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| US9048282B2 (en) * | 2013-03-14 | 2015-06-02 | Alpha And Omega Semiconductor Incorporated | Dual-gate trench IGBT with buried floating P-type shield |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320753A (en) * | 2007-05-29 | 2008-12-10 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN204088328U (en) * | 2014-10-11 | 2015-01-07 | 王金 | A kind of novel bigrid groove MOS unit |
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