CN104241283B - Double-trench rectifier and manufacturing method thereof - Google Patents
Double-trench rectifier and manufacturing method thereof Download PDFInfo
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- CN104241283B CN104241283B CN201310739980.2A CN201310739980A CN104241283B CN 104241283 B CN104241283 B CN 104241283B CN 201310739980 A CN201310739980 A CN 201310739980A CN 104241283 B CN104241283 B CN 104241283B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 230000000994 depressogenic effect Effects 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 27
- 230000002262 irrigation Effects 0.000 claims description 19
- 238000003973 irrigation Methods 0.000 claims description 19
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- 238000005516 engineering process Methods 0.000 claims description 13
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- 239000010703 silicon Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000011144 upstream manufacturing Methods 0.000 claims 6
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 230000008859 change Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 239000012895 dilution Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910010380 TiNi Inorganic materials 0.000 description 1
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Abstract
The invention provides a double-channel rectifier and a manufacturing method thereof, wherein the structure of a double-channel MOS rectifier component comprises a plurality of main channels which are formed in parallel in an n-epitaxial layer on a heavily doped n + semiconductor substrate, the main channels are separated from each other by a platform unit and internally provided with main channel oxide layers which are formed at the bottom and the side wall of the main channel and are filled with a conductive first polycrystalline silicon layer to form a channel metal oxide semiconductor structure; in addition, a plurality of concave regions are arranged in the platform, the concave regions comprise MOS structures and are composed of conductive second polysilicon layers/sub-channel gate oxide layers/n-epitaxial layers, and a plurality of p-type bodies (ion implantation regions) are implanted at two sides of the concave region MOS structures; a top metal layer is covered on the front surface of the semiconductor substrate including the polysilicon layers and the p-type ion implantation area in a blanket mode to serve as an anode, and a bottom metal layer is formed on the heavily doped n + semiconductor substrate as a cathode.
Description
Technical field
The present invention is related to semiconductor subassembly, particularly relates to a kind of new double groove-shaped commutation diode structures and its manufacture
Method.
Background technology
Schottky diode is a kind of important (PCC) power, be widely applied to the switch of power supply unit, motor control,
Telecommunication switches, factory automation, automatic electronic etc. and many high-speed power switch applications.Why Schottky diode has
Attractive part is with good performance, such as under reverse blas, with can be said to be reasonable leakage current (Schottky diode
Leakage current is higher than general PN type diodes), low forward bias voltage drop and reverse turnaround time tRRThen at least may be used during short, reverse bias
To stop the high pressure up to 250 volts.But, Schottky diode leakage current is higher than general PN type diodes, and leakage current
Unstable value but increase with the increase of reverse bias because image charge potential barrier reduce (image charge
potential barrier lowering).An other major defect is, Metals-semiconductor contacts under temperature rise, it
Reliability can also be reduced, and cause Schottky diode it bears forward and the ability of reverse surging declines.
Known ditching type rectifier stack has a variety of different manufacture methods, and one of them refers to the another of inventor
Patent application case, application serial number is No. 101140637.
Known ditching type rectifier stack structure, refers to Fig. 1, includes active region 15A and terminator 15T.Wherein actively
There is the active region 15A for the n- epitaxial layers 105 that irrigation canals and ditches are formed on the n+ semiconductor substrates 100 of heavy doping in area 15A.Have in irrigation canals and ditches
Ditch oxidation layer 10G is formed at bottom and the side wall of irrigation canals and ditches.Filled up again with a polysilicon 40.Platform between irrigation canals and ditches then separately has p+ weights
Doped region 20 as two little Er , hang over the both sides that platform is adjacent to irrigation canals and ditches.Separately there is metal silicide on polysilicon 40 and platform
60 form, and a metal layer at top 80 connects active region 15A and extended with the termination plot structure of covering part, terminate as anode
The area 15T plot structure that terminates includes a bigger irrigation canals and ditches, and trench sidewall has oxide layer 10D/ sidewall polycrystalline silicon 40S/ irrigation canals and ditches grid
Pole oxide layer 10G is formed thereon.Another metal level is then formed at the back side of the n+ semiconductor substrates 100 of heavy doping, using as
Negative electrode.MOS (metal-oxide semiconductor (MOS)) density of texture of this structure is not high.
The present invention will disclose another new double type rectifier stack structure, make full use of the area of plane that can be utilized, because
For the platform between irrigation canals and ditches area, then depressed area is formed, and in addition to tap drain canal has MOS structure, also there is MOS structure depressed area,
And because the oxide layer in the MOS structure of depressed area is enough thin, therefore, forward initial bias VF is lower, the smaller purpose of reverse leakage.
And because sufficiently using the area of plane thus can to carry electric current bigger.
The content of the invention
Present invention aims at the manufacture method and structure for disclosing a kind of pair of ditching type MOS rectifier stack.The component is included：
In the parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of multiple tap drain canals, there is master in the multiple tap drain canal
Ditch oxidation layer is formed at the main trench bottom and side wall；Multiple depressed area intervals are formed at the master between the multiple tap drain canal
In the n- epitaxial layers of platform, in the multiple depressed area there is counter drain canal grid oxic horizon to be formed at the depressed area bottom and side
Wall；First polysilicon layer of one conductive-type impurity doping is formed in the tap drain canal；More than the second of one conductive-type impurity doping
Crystal silicon layer is formed in the depressed area to form MOS structure, and the MOS structure includes second polysilicon layer/pair
Irrigation canals and ditches grid oxic horizon/the epitaxial layer；Multiple p-type body zones are formed at the n- epitaxial layers under the platform of the depressed area both sides
It is interior；It is positive to be used as anode, one that one metal layer at top is covered in the semiconductor substrate including the polysilicon layer, p-type body zone
Bottom metal layers are formed on the n+ semiconductor substrates of the heavy doping as negative electrode.
The component also includes in another embodiment that the present invention is provided, the parallel n+ for being formed at heavy doping of multiple tap drain canals half
Have in n- epitaxial layers on conductor substrate, in the multiple tap drain canal tap drain canal oxide layer be formed at the main trench bottom and
Side wall；Multiple depressed area intervals are formed in the n- epitaxial layers of the main platform between the multiple tap drain canal, the multiple depressed area
It is interior that there is counter drain canal grid oxic horizon to be formed on the depressed area bottom and side wall and the platform of depressed area both sides；One conductivity type
First polysilicon layer of impurity doping is formed in the tap drain canal, and counter drain canal grid is also formed with first polysilicon layer
Oxide layer；Second polysilicon layer of one conductive-type impurity doping is formed at the depressed area and is spilled on platform, and exceeds
In on the counter drain canal grid oxic horizon on the first polysilicon layer of tap drain canal, second polysilicon layer be patterned into multiple row with
The tap drain canal moves towards perpendicular multiple MOS structures row, described MOS structure row, comprising second polysilicon layer/described
Counter drain canal grid oxic horizon/epitaxial layer and second polysilicon layer/counter drain canal grid oxic horizon/described more than first
Crystal silicon layer；Multiple p-type body zones are formed in the n- epitaxial layers that the MOS structure is arranged under adjacent platform；One metal layer at top
The semiconductor substrate front including MOS structure row and adjacent body zone is covered in be used as anode, a bottom metal layers
It is formed at as negative electrode on the n+ semiconductor substrates of the heavy doping.
The manufacture method of a kind of pair of ditching type rectifier stack is also provided in the embodiment of the present invention, the manufacture method is comprising following
Step：Form multiple tap drain canals each with the spaced and parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of a platform
It is interior；Tap drain canal oxide layer is formed on the main trench bottom and side wall and the platform；Form conductive-type impurity doping
First polysilicon layer in the tap drain canal until overflow；Impose etch-back technics and overflowed with removing more than first on the platform
Tap drain canal oxide layer on crystal silicon layer and the platform；Form multiple depressed areas each with an interval, be formed at the n- of the platform
In epitaxial layer；Thermal oxidation technology is imposed to form counter drain canal grid oxic horizon in the depressed area bottom, side wall platform and described
On first polysilicon layer；The second polysilicon layer is formed in the depressed area, until overflowing and higher than first polysilicon layer
On counter drain canal grid oxic horizon；Pattern second polysilicon layer and arranged with forming multiple MOS structures, the MOS structure row
Comprising etch-back technics is imposed, to remove the second polysilicon layer on platform, to be formed at the depressed area, the MOS structure
Include second polysilicon layer/counter drain canal grid oxic horizon/n- epitaxial layers；Impose first time ion implanting skill
Art, injects with n-type impurity, to form p bodies in the n- epitaxial layers under the adjacent platform of the MOS structure；Impose annealing
Technique, to activate the impurity of implantation；Remove all exposed oxide layers on platform；One or two of n+ ion implanted region is formed in described
P-type body zone and the both sides for being adjacent to the MOS structure row；Partly led including the polysilicon layer, p-type body zone with being covered in
Structure base board front is to be used as anode；A bottom metal layers are formed as negative electrode on the n+ semiconductor substrates of the heavy doping.
The manufacture method is further comprising the steps of in another embodiment that the present invention is provided：Form multiple tap drain canals each with one
In the spaced and parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of platform；Tap drain canal oxide layer is formed in the master
On trench bottom and side wall and the platform；The first polysilicon layer of conductive-type impurity doping is formed in straight in the tap drain canal
To spilling；Impose etch-back technics and overflowed with removing in the tap drain canal oxygen on the first polysilicon layer and the platform on the platform
Change layer；Form multiple depressed areas each with an interval, be formed in the n- epitaxial layers of the platform；Thermal oxidation technology is imposed to be formed
Counter drain canal grid oxic horizon is on the depressed area bottom, side wall platform and first polysilicon layer；Form the second polysilicon
Layer is in the depressed area, until overflowing；Pattern second polysilicon layer and tied with forming the MOS moved towards perpendicular to tap drain canal
Structure is arranged, and the MOS structure row include second polysilicon layer/counter drain canal grid oxic horizon/n- epitaxial layers and institute
State the second polysilicon layer/counter drain canal grid oxic horizon/first polysilicon layer；First time ion implantation technique is imposed,
Injection is with n-type impurity, to be formed in the n- epitaxial layers that p bodies are arranged in the MOS structure under adjacent platform；Impose lehr attendant
Skill, to activate the impurity of implantation；Remove all exposed counter drain canal grid oxic horizons on platform；A metal layer at top is formed to cover
It is placed on the semiconductor substrate including the polysilicon layer, p-type body zone positive to be used as anode；Form a bottom metal layers conduct
Negative electrode is on the n+ semiconductor substrates of the heavy doping.
The present invention has advantages below：
Compared to known ditching type rectifier structure, double irrigation canals and ditches rectifier structures of the invention have MOS structure in tap drain canal,
Also there is MOS structure depressed area, eliminates Schottky contact so that reverse leakage is substantially reduced.In MOS structure in depressed area
Oxide layer is thinner, and this can significantly reduce forward start voltage VF.In addition, n+ heavily doped regions 145 are formed at p-type body 135
Both sides close to MOS row can further reduce forward start voltage.
On the other hand, then it is the leakage current of significant reduction reverse blas.
One, which is indebted on double trench architectures, same level area, again can carry higher forward current.
Brief description of the drawings
The following drawings is only intended to do schematic illustration and explanation to the present invention, not delimit the scope of the invention, wherein：
Fig. 1 shows known ditching type rectifier cross-sectional view.
Fig. 2 a displays are bowed according to double ditching type MOS structures (being free of top metal pad) of first embodiment of the invention manufacture
Depending on schematic diagram.
Fig. 2 b are according to double ditching type MOS structures (being free of top metal pad) of first embodiment of the invention change type manufacture
Schematic top plan view.
Fig. 3 a displays are bowed according to double ditching type MOS structures (being free of top metal pad) of second embodiment of the invention manufacture
Depending on schematic diagram.
Fig. 3 b are according to double ditching type MOS structures (being free of top metal pad) of second embodiment of the invention change type manufacture
Schematic top plan view.
Fig. 4 shows that tap drain canal is formed in n- epitaxial layers, and in the tap drain canal and cross section that has the formation of tap drain canal oxide layer 120 shows
It is intended to.
Fig. 5 shows that the first polysilicon layer is backfilled in after Fig. 4 tap drain canal, then imposes eatch-back to remove be higher by main platform the
The cross-sectional view of one polysilicon layer and tap drain canal oxide layer.
Fig. 6 A and Fig. 6 B show the AA ' lines of cut and BB ' cross-sectional view along Fig. 2 a respectively, and icon defines depressed area
The photoresistance pattern of position.
Fig. 7 A, Fig. 7 B, Fig. 7 C show the cross-sectional view along Fig. 2 a AA ' lines of cut, BB ' and CC ' lines of cut respectively,
Diagram depressed area has been formed, and also forms counter drain canal grid oxic horizon.
Fig. 8 A, Fig. 8 B, Fig. 8 C show the cross-sectional view along Fig. 2 a AA ' lines of cut, BB ' and CC ' lines of cut respectively,
The second polysilicon layer is illustrated to have been formed.
Fig. 9 A, Fig. 9 B, Fig. 9 C show the cross-sectional view along Fig. 2 a AA ' lines of cut, BB ' and CC ' lines of cut respectively,
Diagram, the second polysilicon layer is etched back.
Figure 10 A, Figure 10 B, Figure 10 C show the cross section signal along Fig. 2 a AA ' lines of cut, BB ' and CC ' lines of cut respectively
Figure, it is illustrated that, p-type body (p body) is formed in the n- epitaxial layers under time platform.
Figure 11 A, Figure 11 B, Figure 11 C show the cross section signal along Fig. 2 a AA ' lines of cut, BB ' and CC ' lines of cut respectively
Figure, it is illustrated that, double positive final structures of irrigation canals and ditches rectifier stack.
Figure 12 A, Figure 12 B, Figure 12 C show the cross section signal along Fig. 2 b AA ' lines of cut, BB ' and CC ' lines of cut respectively
Figure, icon, change type of the photoresistance pattern to define first embodiment.
Figure 13 A, Figure 13 B, Figure 13 C show the cross section signal along Fig. 2 b AA ' lines of cut, BB ' and CC ' lines of cut respectively
Figure, it is illustrated that, the positive final structure of the change type of second embodiment.
Figure 14 A, Figure 14 B, Figure 14 C show along the AA ' lines of cut, BB ' and CC ' lines of cut of Fig. 3 a top plan views respectively
Cross-sectional view, it is illustrated that, the second polysilicon layer of second embodiment is defined after pattern.
Figure 15 A, Figure 15 B, Figure 15 C show along the AA ' lines of cut, BB ' and CC ' lines of cut of Fig. 3 a top plan views respectively
Cross-sectional view, it is illustrated that, the p-type body (p body) of second embodiment is formed in the n- epitaxial layers under time platform.
Figure 16 A, Figure 16 B, Figure 16 C show along the AA ' lines of cut, BB ' and CC ' lines of cut of Fig. 3 a top plan views respectively
Cross-sectional view, it is illustrated that, double positive final structures of irrigation canals and ditches rectifier stack second embodiment.
Figure 17 A, Figure 17 B, Figure 17 C show along the AA ' lines of cut, BB ' and CC ' lines of cut of Fig. 3 b top plan views respectively
Cross-sectional view, it is illustrated that, double irrigation canals and ditches rectifier stack second embodiment change type photoresistance patterns have been formed.
Figure 18 A, Figure 18 B, Figure 18 C show along the AA ' lines of cut, BB ' and CC ' lines of cut of Fig. 3 b top plan views respectively
Cross-sectional view, it is illustrated that, the positive final structure of double irrigation canals and ditches rectifier stack second embodiment change types.
Reference
The n- epitaxial layers of n+ semiconductor substrates 105 of 100 heavy doping
The main platform of 115 tap drain canal 118
The tap drain canal oxide layer of 125 depressed area 120
130 first polysilicon layer 135p types bodies (p body)
The photoresistance pattern of 140 second polysilicon layer 122,142,152
127 counter drain canal grid oxic horizon 145n+ doped regions
180th, the polysilicon layer of 80 metal layer at top 40
10G irrigation canals and ditches grid oxic horizon 15A active regions
10D oxide layer 15T terminators
90th, 190 bottom metal layers 20p types injection region
Embodiment
In order to which technical characteristic, purpose and effect to the present invention are more clearly understood from, now control illustrates this hair
Bright embodiment.
The present invention discloses a pair of ditching type MOS rectifier stack structures, and the top plan view and Figure 11 A that refer to Fig. 2 a are extremely schemed
11C cross-sectional view, herein and the # in figure #A as described below, figure #B, figure #C refers to that # schemes, the capitalization English after #
Represented by literary A, B, C is the AA ' lines, BB ', CC ' lines painted along top plan view.For the benefit of understand thin portion structure, plane is bowed
The thin portion content of view and not comprising metal layer at top 180, the relation of metal layer at top 180 and modular construction, and modular construction,
It refer to cross-sectional view.
The foundation first embodiment of the present invention, double ditching type MOS rectifier stack structures, comprising:Multiple tap drain canals 115 are parallel
It is formed in the n- epitaxial layers 105 on the n+ semiconductor substrates 100 of heavy doping, there is tap drain canal oxygen in the plurality of tap drain canal 115
Change layer 120 and be formed at the bottom of tap drain canal 115 and side wall；Multiple depressed areas 125 are spaced with a distance, are formed under platform 118
In n- epitaxial layers 105, in multiple depressed areas 125 there is counter drain canal grid oxic horizon 127 to be formed at the bottom of depressed area 125 and side
Wall；First polysilicon layer 130 of one conductive-type impurity doping is formed at tap drain canal 115, the second polycrystalline of conductive-type impurity doping
Silicon layer 140 is formed in depressed area 125 and fills up it, and to form MOS structure, the MOS structure includes the second polysilicon layer
140/ counter drain canal grid oxic horizon 127/n- epitaxial layers 105；Multiple p-type bodies (ion implanted region) 135 flow into the MOS knots
In n- epitaxial layers 105 under the platform 118 of structure both sides；The code-pattern of one metal layer at top 180 is covered in including those polysilicon layers
130th, p bodies 135 on so that as anode, a bottom metal layers are formed at the n+ semiconductor substrates of the heavy doping as negative electrode
On.
The change type of first embodiment, is to further include two n+ doped regions 145 in p-type body (p body) 135, these
Individual n+ doped regions 145 can reduce forward start voltage VF.Top plan view 2b and cross-sectional view are referred to, Figure 13 A are extremely
Figure 13 C.
In a second embodiment, Fig. 3 a top plan view and Figure 16 A to Figure 16 C cross-sectional view be refer to.Lead
Second polysilicon layer 140 of electric type impurity doping is after depressed area 125 is completed, and the height of spilling is than in tap drain canal 115 more than first
Counter drain canal grid oxic horizon 127 on crystal silicon layer 130 is highly taller.Afterwards in a patterned manner, a conductive-type impurity is mixed
The second miscellaneous polysilicon layer 140 is formed at those depressed areas 125 and is spilled on platform 118, and exceeds in tap drain canal 115
On counter drain canal grid oxic horizon 127 on first polysilicon layer 130, the second polysilicon layer 140 is patterned into multiple row and tap drain
Canal 115 moves towards perpendicular multiple MOS structures row, and described MOS structure row include the counter drain canal grid of the second polysilicon layer 140/
Oxide layer 127/n- epitaxial layers 105 and the polysilicon layer 130 of 140/ counter drain canal grid oxic horizon of the second polysilicon layer 127/ first.It is many
Individual p-type body zone 135 is formed in the n- epitaxial layers 105 that MOS structure is arranged under adjacent platform 115.The blanket of one metal layer at top 180
Formula is covered to be covered in including those MOS structures row, the upper surface of p bodies 135 so that as anode, a bottom metal layers 190 are used as negative electrode
It is formed on the back side of n+ semiconductor substrates 100 of the heavy doping.
The change type of second embodiment, is also to further include two n+ doped regions 145 in p-type body (p body) 135, please
Referring to top plan view 3b and cross-sectional view, Figure 18 A to Figure 18 C.
Manufacture method is will be described below.In the following description, follow the representative of the "-" number after n or p and be lightly doped, and "+" table
Show heavy doping.
The cross-sectional view shown in Fig. 4 is refer to, Fig. 4 shows that the n+ semiconductor substrates 100 of a p-type impurity heavy doping have
The n- epitaxial layers 105 of one p-type impurity doping.Multiple tap drain canals 115, can known photoresistance pattern (non-icon) be photomask or
With rigid photomask (not shown), then impose dry etching method and formed.
Then, then thermal oxidation technology formation tap drain canal oxide layer 120 is imposed in the side wall of tap drain canal 115 and bottom and adjacent
On the platform 118 of irrigation canals and ditches.This step can also repair etching injury simultaneously.
Fig. 5 is refer to, then, is deposited the first polysilicon layer of conduction type ion 130 with the technology for depositing and synchronously adulterating
In the tap drain canal 115 and it is filled up to spilling.Then, then with etch-back techniques or cmp it will be above on platform 118
One polysilicon layer 130 is removed, until the oxide layer on platform 118 is also removed, and untill exposing the epitaxial layer 105 of platform.
Then, Fig. 6 A and Fig. 6 B be refer to, respectively illustrate two moved towards perpendicular to tap drain canal 115 but diverse location it is transversal
Face schematic diagram.A photoresistance pattern 122 is formed in the surface after etch-back, to define the position where depressed area.Depressed area is intended to edge
A-A ' directions are formed at the platform 118 between tap drain canal 115, and are protected along B-B ' directions with photoresistance pattern 122.
And then, it is photomask with photoresistance pattern 122, imposes a plasma etch technology, forms depressed area 125 in platform
In 118.Fig. 7 A, Fig. 7 B show shows two cross-sectional views moved towards perpendicular to tap drain canal 115 respectively, and Fig. 7 C show along platform
To cross-sectional view.Then, then impose thermal oxidation technology to form counter drain canal grid oxic horizon 127 in depressed area 125
The upper surface of the adjacent platform in bottom, side wall, depressed area 125 and the first polysilicon layer 130.It is worth noting that counter drain canal grid
Oxide layer 127 is thinner than tap drain canal oxide layer 120.
Then, then with the synchronous technology adulterated by conduction type ion deposit the second polysilicon layer 140 will be filled with it is all recessed
Area 125 is fallen into, until overflowing.It refer to Fig. 8 A~cross-sectional views of Fig. 8 C along three directions.
Then, Fig. 9 A to Fig. 9 C are refer to, be will be above with etch-back techniques or cmp more than second on platform 118
Crystal silicon layer 140 is removed, until the counter drain canal grid oxic horizon 127 on platform 118 is also removed, and exposes the epitaxial layer of platform
Untill 105, to form MOS structure in depressed area 125.
It please then refer to Figure 10 A~Figure 10 C.With ion implantation technique, p-type conductivity ion is implanted into comprehensively, and in MOS
P-type body (p body) 135 is formed under the adjacent platform 118 of structure.The dosage of ion implanting is so that p body135 concentration is high
In high 1~3 order of magnitude of the n-type concentration of n- epitaxial layers 105, such as 1E12-1E14/cm2.The energy of injection is about
10keV-1000keV.Then all oxide layers in plane, then with buffer solution or the HF of dilution are removed.
It please then refer to Figure 11 A~Figure 11 C cross-sectional view.Re-form metal layer at top 180.Form top metal
Before layer 180, it can select first to impose self-aligning metal silicide technology.For example, first with sputtering technology deposited in sequential Ti/TiN.So
Impose RTA again afterwards and wet etching removes unreacted metal level.Metal layer at top 180 is usually one to three layer of storehouse metal
Layer.Such as TiNi/Ag or TiW/Al or Al etc..
The change type of first embodiment is that two n+ (n-type heavy doping) area is re-formed in p-type body (p body) 135.
Figure 12 A~Figure 12 C then show the photoresistance pattern photomask of ion implanting.Figure 13 A~Figure 13 C then show that p-type body (p body) 135 is wrapped
The cross-sectional view of end-results containing two n+ (n-type heavy doping) area 145.
According to one more embodiment of the present invention, the technique of second embodiment in deposit the second polysilicon layer 140 be etched back it is previous
As first embodiment, i.e. Fig. 4 are identical to Fig. 8.Following step is carried out again.
A photoresistance pattern 142 for defining the second polysilicon layer 140 is formed, then to define the photoresistance pattern 142 of MOS structure row
For photomask, with the second polysilicon layer of plasma etch 140.MOS structure row described here are secondary comprising the second polysilicon layer 140/
Irrigation canals and ditches grid oxic horizon 127/n- epitaxial layers 105 and the polysilicon of 140/ counter drain canal grid oxic horizon of the second polysilicon layer 127/ first
Layer 130.As illustrated, being removed along second polysilicon layer 140 in BB ' directions, along second polysilicon layer 140 in AA ' directions
Protected by photoresistance pattern 142.And therefore, along CC ' directions photoresistance pattern just as shown in Figure 14 C.Result after etching, please
With reference to Figure 14 A~Figure 14 C.
Then, refer to Figure 15 A~Figure 15 C, remove photoresistance pattern 142, then carry out ion implanting, by p-type conductivity from
Sub implantation comprehensively, and arranged in MOS structure and p-type body (pbody) 135 is formed under adjacent platform.The dosage of ion implanting, just like
Described in first embodiment.
Then, Figure 16 A~Figure 16 C are refer to, then with all oxide layers on buffer solution or the HF of dilution removal planes.Again
Form metal layer at top 180.With Specifications metal layer at top 180 generation type one as in the first embodiment.Finally, then n+ is ground
The back side of semiconductor substrate 100, a redeposited bottom metal layers 190 are to be used as electrode.
Similarly, the change that second embodiment can also be as in the first embodiment, n+ conductive impurities are planted in every p
The both sides of type body (p body) 135.Figure 17 A~Figure 17 C show photoresistance pattern during ion implantation technique.Figure 18 A~Figure 18 C show
Cross-sectional view after the formation of metal layer at top 180.Finally, then the back side of n+ semiconductor substrates 100, redeposition one are ground
Bottom metal layers 190 are to be used as electrode.
The schematical embodiment of the present invention is the foregoing is only, the scope of the present invention is not limited to.Appoint
The person skilled of what this area, the equivalent variations made on the premise of the design of the present invention and principle is not departed from are with repairing
Change, protection scope of the present invention all should be belonged to.
Claims (10)
1. a kind of pair of ditching type rectifier stack, it is characterised in that the component is included：
In the parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of multiple tap drain canals, have in the multiple tap drain canal
There is tap drain canal oxide layer to be formed at the main trench bottom and side wall；
Multiple depressed area intervals are formed in the n- epitaxial layers of the main platform between the multiple tap drain canal, in the multiple depressed area
The depressed area bottom and side wall are formed at counter drain canal grid oxic horizon；
First polysilicon layer of one conductive-type impurity doping is formed in the tap drain canal；
Second polysilicon layer of one conductive-type impurity doping is formed in the depressed area to form MOS structure, the MOS structure
Comprising second polysilicon layer, the counter drain canal grid oxic horizon, the epitaxial layer is bottom upstream sequence by the epitaxial layer
Formed；
Multiple p-type body zones are formed in the n- epitaxial layers under the platform of the depressed area both sides；
One metal layer at top be covered in including first and second described polysilicon layer, p-type body zone semiconductor substrate front with
As anode, a bottom metal layers are formed at the back side of the n+ semiconductor substrates of the heavy doping as negative electrode.
2. according to claim 1 pair of ditching type rectifier stack, it is characterised in that each of the p-type body zone is also
Comprising forming two n+ ion implanted regions in the p-type body zone and be adjacent to the both sides of the MOS structure.
3. according to claim 1 pair of ditching type rectifier stack, it is characterised in that the component also includes a metal silication
Nitride layer is formed on second polysilicon layer, the n- epitaxial layers, to connect the metal layer at top.
4. a kind of pair of ditching type rectifier stack, it is characterised in that the component includes：
In the parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of multiple tap drain canals, have in the multiple tap drain canal
There is tap drain canal oxide layer to be formed at the main trench bottom and side wall；
Multiple depressed area intervals are formed in the n- epitaxial layers of the main platform between the multiple tap drain canal, in the multiple depressed area
It is formed at counter drain canal grid oxic horizon on the depressed area bottom and side wall and the platform of depressed area both sides；
First polysilicon layer of one conductive-type impurity doping is formed in the tap drain canal, is also formed on first polysilicon layer
There is counter drain canal grid oxic horizon；
Second polysilicon layer of one conductive-type impurity doping is formed at the depressed area and is spilled on platform, and exceeds in master
On counter drain canal grid oxic horizon on first polysilicon layer of irrigation canals and ditches, second polysilicon layer be patterned into multiple row with it is described
Tap drain canal moves towards perpendicular multiple MOS structures row, and described MOS structure row include second polysilicon layer, the counter drain
Canal grid oxic horizon, the epitaxial layer is that bottom upstream sequence is formed and second polysilicon layer by the epitaxial layer, the pair
Irrigation canals and ditches grid oxic horizon, first polysilicon layer is that bottom upstream sequence is formed by first polysilicon layer；
Multiple p-type body zones are formed in the n- epitaxial layers that the MOS structure is arranged under adjacent platform；
One metal layer at top is covered in the semiconductor substrate front including MOS structure row and adjacent body zone to be used as sun
Pole a, bottom metal layers are formed at the back side of the n+ semiconductor substrates of the heavy doping as negative electrode.
5. according to claim 4 pair of ditching type rectifier stack, it is characterised in that each of the p-type body zone is also
Comprising two n+ ion implanted regions of formation are in the p-type body zone and are adjacent to the both sides that the MOS structure is arranged.
6. the manufacture method of a kind of pair of ditching type rectifier stack, it is characterised in that the manufacture method is comprised the steps of：
Form multiple tap drain canals each with the spaced and parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of a platform；
Tap drain canal oxide layer is formed on the main trench bottom and side wall and the platform；
Formed a conductive-type impurity doping the first polysilicon layer in the tap drain canal until overflow；
Impose etch-back technics and overflowed with removing in the main ditch oxidation on the first polysilicon layer and the platform on the platform
Layer；
Form multiple depressed areas each with an interval, be formed in the n- epitaxial layers of the platform；
Thermal oxidation technology is imposed to form counter drain canal grid oxic horizon in the depressed area bottom, side wall platform and described more than first
On crystal silicon layer；
The second polysilicon layer is formed in the depressed area, until overflowing and higher than the counter drain canal grid on first polysilicon layer
Pole oxide layer；
Pattern second polysilicon layer and arranged with forming multiple MOS structures, the MOS structure row, which are included, imposes etch-back technics,
To remove the second polysilicon layer and counter drain canal grid oxic horizon on platform, to make the second described polysilicon layer only be formed at institute
State depressed area, the MOS structureRowComprising second polysilicon layer, the counter drain canal grid oxic horizon, the n- epitaxial layers,
It is that bottom upstream sequence is formed by the n- epitaxial layers；
First time ion implantation technique is imposed, injection is adjacent in MOS structure row to form p-type body zone with n-type impurity
Platform under n- epitaxial layers in；
Annealing process is imposed, to activate the impurity of implantation；
Remove all exposed oxide layers on platform；
Form a metal layer at top, be covered in first and second described polysilicon layer, p-type body zone semiconductor substrate front
To be used as anode；A bottom metal layers are formed as negative electrode in the back side of the n+ semiconductor substrates of the heavy doping.
7. the manufacture method of according to claim 6 pair of ditching type rectifier stack, it is characterised in that the manufacture method bag
It is contained on removal platform after all exposed oxide layers and is formed before a metal layer at top, forms two n+ ion implanted regions
In the p-type body zone and it is adjacent to the both sides of MOS structure row.
8. the manufacture method of according to claim 6 pair of ditching type rectifier stack, it is characterised in that the manufacture method is also
Before metal layer at top formation, first impose metal silicide self-registered technology to form metal silicide layer in described the
The upper surface of two polysilicon layers and p-type body zone.
9. the manufacture method of a kind of pair of ditching type rectifier stack, it is characterised in that the manufacture method is comprised the steps of:
Form multiple tap drain canals each with the spaced and parallel n- epitaxial layers being formed on the n+ semiconductor substrates of heavy doping of a platform；
Tap drain canal oxide layer is formed on the main trench bottom and side wall and the platform；
Formed a conductive-type impurity doping the first polysilicon layer in the tap drain canal until overflow；
Impose etch-back technics and overflowed with removing in the main ditch oxidation on the first polysilicon layer and the platform on the platform
Layer；
Form multiple depressed areas each with an interval, be formed in the n- epitaxial layers of the platform；
Thermal oxidation technology is imposed to form counter drain canal grid oxic horizon in the depressed area bottom, side wall platform and described more than first
On crystal silicon layer；
The second polysilicon layer is formed in the depressed area, until overflowing；
Pattern second polysilicon layer and arranged with forming the MOS structure moved towards perpendicular to tap drain canal, the MOS structure row are included
Second polysilicon layer, the counter drain canal grid oxic horizon, the n- epitaxial layers are bottom upstream sequence by the n- epitaxial layers
Formed and second polysilicon layer, the counter drain canal grid oxic horizon, first polysilicon layer, by first polysilicon
Layer is formed for bottom upstream sequence；
First time ion implantation technique is imposed, injection is adjacent in MOS structure row to form p-type body zone with n-type impurity
Platform under n- epitaxial layers in；
Annealing process is imposed, to activate the impurity of implantation；
Remove all exposed counter drain canal grid oxic horizons on platform；
A metal layer at top is formed to be covered in the semiconductor substrate including first and second described polysilicon layer, p-type body zone
Front is to be used as anode；
A bottom metal layers are formed as negative electrode in the back side of the n+ semiconductor substrates of the heavy doping.
10. the manufacture method of according to claim 9 pair of ditching type rectifier stack, it is characterised in that the manufacture method
Also it is contained on removal platform after all exposed counter drain canal grid oxic horizons and is formed before a metal layer at top, forms two
Individual n+ ion implanted regions are in the p-type body zone and are adjacent to the both sides that the MOS structure is arranged.
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| TW102122294A TWI514578B (en) | 2013-06-21 | 2013-06-21 | Structure of dual trench rectifier and method of forming the same |
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| TWI646604B (en) * | 2016-08-12 | 2019-01-01 | 聯華電子股份有限公司 | Semiconductor device and manufacturing method thereof |
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| CN101114670A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Schottky barrier semiconductor device |
| CN101180737A (en) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | Power semiconductor devices and methods of manufacture |
| TW200921792A (en) * | 2007-11-14 | 2009-05-16 | Chip Integration Tech Co Ltd | High switching speed two mask schottky diode with high field breakdown |
| CN102157568A (en) * | 2011-02-01 | 2011-08-17 | 英属维京群岛商节能元件股份有限公司 | P-N junction surface diode structure of metal oxide semiconductor and manufacturing method thereof |
| CN102246306A (en) * | 2008-12-08 | 2011-11-16 | 飞兆半导体公司 | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
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| US6580141B2 (en) * | 2001-06-01 | 2003-06-17 | General Semiconductor, Inc. | Trench schottky rectifier |
| WO2008039459A1 (en) * | 2006-09-27 | 2008-04-03 | Maxpower Semiconductor, Inc. | Power mosfet with recessed field plate |
| US8101995B2 (en) * | 2007-02-08 | 2012-01-24 | International Rectifier Corporation | Integrated MOSFET and Schottky device |
| TWI422043B (en) * | 2011-04-15 | 2014-01-01 | Pfc Device Corp | Rectifier with vertical mos structure and method manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101180737A (en) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | Power semiconductor devices and methods of manufacture |
| CN101114670A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Schottky barrier semiconductor device |
| TW200921792A (en) * | 2007-11-14 | 2009-05-16 | Chip Integration Tech Co Ltd | High switching speed two mask schottky diode with high field breakdown |
| CN102246306A (en) * | 2008-12-08 | 2011-11-16 | 飞兆半导体公司 | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
| CN102157568A (en) * | 2011-02-01 | 2011-08-17 | 英属维京群岛商节能元件股份有限公司 | P-N junction surface diode structure of metal oxide semiconductor and manufacturing method thereof |
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