CN104241214A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN104241214A
CN104241214A CN201310392415.3A CN201310392415A CN104241214A CN 104241214 A CN104241214 A CN 104241214A CN 201310392415 A CN201310392415 A CN 201310392415A CN 104241214 A CN104241214 A CN 104241214A
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China
Prior art keywords
substrate
line layer
semiconductor package
rerouting line
edge
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CN201310392415.3A
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Chinese (zh)
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CN104241214B (en
Inventor
郑斌宏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201710541530.0A priority Critical patent/CN107195602A/en
Publication of CN104241214A publication Critical patent/CN104241214A/en
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Publication of CN104241214B publication Critical patent/CN104241214B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a chip and an underfill. The substrate has streets vertically penetrating through the substrate and transversely extending from one edge side surface of the substrate to the other edge side surface of the substrate along the upper surface of the substrate, so that the substrate forms a plurality of sub-substrates separated from each other. The chip is arranged on the substrate. The bottom glue is formed between the chip and the substrate.

Description

Semiconductor package part and manufacture method thereof
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to a kind of semiconductor package part and the manufacture method thereof that reduce amount of warpage especially.
Background technology
Conventional semiconductors substrate is due to more and more thin, and the structure of semiconductor substrate bilateral is asymmetric, therefore easily produces warpage.When the amount of warpage of semiconductor substrate is larger, in the technique that follow-up chip is arranged thereon, easy generation is such as that chip engages the problems such as bad with substrate.
Summary of the invention
The invention relates to a kind of semiconductor package part and manufacture method thereof, the amount of warpage of semiconductor package part can be reduced.
According to one embodiment of the invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, a chip and a primer.Substrate has a segmentation road, and segmentation road vertically runs through substrate, and laterally extends to another side, edge of substrate from a side, edge of substrate along the upper surface of substrate, makes substrate form several submounts separated from one another.Chip is located on substrate.Primer is formed between chip and substrate.
According to one embodiment of the invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.One substrate is set on a support plate; Form a segmentation road and run through substrate, while laterally extend to another side, edge of substrate from a side, edge of substrate along the upper surface of substrate, make substrate form several submounts separated from one another; One chip is set on substrate; Form a primer between chip and substrate; And, remove support plate.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Figure 1A illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the vertical view of Figure 1A.
Fig. 2 A illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Fig. 2 B illustrates the vertical view of Fig. 2 A.
Fig. 3 A to 3F illustrates the process drawing of the semiconductor package part of Figure 1A.
Fig. 4 illustrates the another kind of process drawing of the semiconductor package part of Figure 1B.
Fig. 5 A to 5B illustrates the process drawing of the semiconductor package part of Fig. 2 A.
Symbol description:
100,200: semiconductor package part
10: support plate
11: adhesive layer
12: patterning photoresist layer
12a, 1143a: perforate
110: substrate
110r, 110r ', 110r ' ': segmentation road
110s: side, edge
110s1: the first side, edge
110s2: the second side, edge
111: submounts
110b, 112b: lower surface
110u, 112u: upper surface
110a, 1131a: perforate
112: base material
113,113 ', 113 ' ': conductive hole
1131: interior conductive mechanism
1132: outer dielectric layer
1133: conductting layer
114: first line layer
1141; 1151: the first dielectric layers
1142: the first rerouting line layers
1143,1153: the second dielectric layers
115: the second line layers
1152: the second rerouting line layers
116,121: electrical contact
120: chip
130: primer
D1: side direction
P: Cutting Road
W1: width
Embodiment
Please refer to Figure 1A, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises substrate 110, chip 120 and primer 130.
Substrate 110 is such as chip or interposer substrate.Substrate 110 comprises at least one submounts 111, base material 112, conductive hole 113, first line layer 114, second line layer 115, at least one electrical contact 116, segmentation road 110r, upper surface 110u and side, edge 110s (110s1,110s2).
Submounts 111 is formed by segmentation road 110r separating base plate 110, and segmentation road 110r extends to the lower surface 110b of substrate 110 from the upper surface 110u of substrate 110 and runs through substrate 110, and segmentation road 110r exposes from the lower surface 110b of substrate 110.
Base material 112 is such as glass, silicon (silicon), metal, metal alloy, polymer (polymer) or another appropriate configuration material form material.Base material 112 has relative upper surface 112u and lower surface 112b.
Conductive hole 113 runs through base material 112 from upper surface 112u, and is electrically connected the first rerouting line layer 1142 and the second rerouting line layer 1152.In one embodiment, conductive hole 113 can expose from the upper surface 112u of base material 112 and lower surface 112b.In another embodiment, conductive hole 113 also can protrude past upper surface 112u and/or the lower surface 112b of base material 112.
Substrate 110 more defines perforate 110a, and conductive hole 113 is located in perforate 110a at least in part.Conductive hole 113 can be silicon perforation (through silicon via, TSV).Conductive hole 113 comprises interior conductive mechanism 1131 and outer dielectric layer 1132, and interior conductive mechanism 1131 exposes from the upper surface 112u of base material 112 and lower surface 112b, and outer dielectric layer 1132 is around interior conductive mechanism 1131.Outer dielectric layer 1132 can adjacent openings 110a sidewall arrange.In this embodiment, in outer dielectric layer 1132, conductive mechanism 1131 can fill up in fact perforate 110a.
In another embodiment, the interior conductive mechanism 1131 of conductive hole 113 ' can protrude past upper surface 112u and the lower surface 112b of base material 112.In this embodiment, outer dielectric layer 1132 also can protrude past upper surface 112u and lower surface 112b.The ledge that one conductting layer (conductive layer) 1133 can be close to interior conductive mechanism 1131 and outer dielectric layer 1132 is arranged.Conductive hole 113 ' is electrically connected at the first rerouting line layer 1142 by conductting layer 1133.
In other embodiments, conductive hole 113 ' ' comprise interior conductive mechanism 1131 and outer dielectric layer 1132, interior conductive mechanism 1131 is ring-type electrodeposited coatings.Interior conductive mechanism 1131 definable perforate 1131a.In addition, interior conductive mechanism 1131 can be filled up by an inner-dielectric-ayer (not illustrating).
In other embodiments, conductive hole 113 comprises conductive mechanism 1131 in.Interior conductive mechanism 1131 directly adjacent base material 112 is arranged.In this embodiment, base material 112 is made up of non-conducting material, and non-conducting material is such as glass.Interior conductive mechanism 1131 definable is similar in appearance to a perforate (not illustrating) of perforate 1131a.
First line layer 114 is formed at the lower surface 112b of base material 112.First line layer 114 comprises the first dielectric layer 1141, first rerouting line layer 1142 and the second dielectric layer 1143.First dielectric layer 1141 is formed at the lower surface 112b of base material 112, and exposes the conductive hole 113 of substrate 110.First rerouting line layer 1142 is formed at the conductive hole 113 exposed, to be electrically connected conductive hole 113.Second dielectric layer 1143 to be formed on the first rerouting line layer 1142 and a part for the first rerouting line layer 1142 exposed.In the present embodiment, because segmentation road 110r walks around the first rerouting line layer 1142 of first line layer 114, therefore do not run through the first rerouting line layer 1142, make do not have direct electrical connection by the first rerouting line layer 1142 between arbitrary adjacent submounts 111.
In addition, the material of the first dielectric layer 1141 is such as organic protection layer, silicon nitride, silica or polymer.The material of the second dielectric layer 1143 can be same as or be different from the first dielectric layer 1141.The thickness of the first dielectric layer 1141 can be identical or be different from the second dielectric layer 1143.
Second line layer 115 is formed at the upper surface 112u of base material 112.Second line layer 115 comprises the first dielectric layer 1151, second rerouting line layer 1152 and the second dielectric layer 1153.First dielectric layer 1151 is formed at the upper surface 112u of base material 112, and exposes the conductive hole 113 of substrate 110.Second rerouting line layer 1152 is formed at the conductive hole 113 exposed, to be electrically connected conductive hole 113.Second dielectric layer 1153 to be formed on the second rerouting line layer 1152 and a part for the second rerouting line layer 1152 exposed, makes chip 120 be electrically connected at conductive hole 113 by the double wiring topology layer 1152 in ground exposed.In the present embodiment, because segmentation road 110r walks around the second rerouting line layer 1152 of the second line layer 115, therefore do not run through the second rerouting line layer 1152, make do not have direct electrical connection by the second rerouting line layer 1152 between arbitrary adjacent submounts 111.
In addition, the material of the first dielectric layer 1151 is such as organic protection layer, silicon nitride, silica or polymer.The material of the second dielectric layer 1153 can be same as or be different from the first dielectric layer 1151.The thickness of the first dielectric layer 1151 can be identical or be different from the second dielectric layer 1153.
Being positioned at the first dielectric layer of relative two of base material 112 and the material of the second dielectric layer and thickness can be identical or different.When the material of the first dielectric layer and the second dielectric layer that are positioned at relative two of base material 112 and/or thickness different time, the asymmetry of substrate 110 can be caused to increase, so even so, by the design of the segmentation road 110r of the embodiment of the present invention, the accumulation amount of warpage of semiconductor package part 100 still can be controlled in one among a small circle or one desired extent.
Electrical contact 116 is such as soldered ball, conductive pole or projection.Electrical contact 116 is formed on the first rerouting line layer 1142 of exposing, to be electrically connected at chip 120.
Chip 120 is located on the upper surface 110u of substrate 110 in orientation down with active surface.Chip 120 has at least one electrical contact 121 to be electrically connected at the conductive hole 113 of substrate 110.This kind of chip 120 is called and covers crystalline substance (flip chip).Electrical contact 121 is such as soldered ball, conductive pole or projection.In another example, chip 120 is located on the upper surface 110u of substrate 110 in orientation upward with active surface, and is electrically connected at substrate 110 with at least one bonding wire.
Primer 130 is formed between chip 120 and substrate 110.The coated electrical contact 121 of primer 130, with protect electrical contact 121 from or reduce the infringement of external environment.In addition, part primer 130 enters a part of segmentation road 110r, to cohere the submounts 111 of separation, and then promotes the bulk strength of substrate 110.In another example, part primer 130 can enter in whole segmentation road 110r, the associativity between so better two submounts 111 promoting separation.
Primer 130 can be formed by an encapsulating material (molding material).This encapsulating material can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.This encapsulating material also can comprise suitable filler (filler), such as, be the silicon dioxide of powdery.This encapsulating material can be pre impregnated material (pre-impregnated (prepreg) material), such as, be pre-preg dielectric material.
Please refer to Figure 1B, it illustrates the top view of Figure 1A.Segmentation road 110r (110r ', 110r ' ') laterally extends to another side, edge 110s (110s1,110s2) from the side, edge 110s (110s1,110s2) of substrate 110 along upper surface 110u.Such as, side, edge 110s comprises the first relative side, edge 110s1 and the second side, edge 110s2, and segmentation road 110r ' laterally extends to the second side, edge 110s2 from the first side, edge 110s1 along upper surface 110u.Again such as, side, edge 110s comprises the first adjacent side, edge 110s1 and the second side, edge 110s3, and segmentation road 110r ' ' laterally extends to the second side, edge 110s3 from the first side, edge 110s1 along upper surface 110u.And split 110r (110r ', 110r ' ') and run through substrate 110, make substrate 110 form several submounts 111 separated from one another.Because substrate 110 is separated into several submounts 111, the amount of warpage that semiconductor package part 100 produces because of high temperature in technique or use procedure therefore can be reduced.Specifically, if substrate 110 omits segmentation road 110r (110r ', 110r ' '), then the area that extends continuously of substrate 110 is comparatively large, makes the accumulation amount of warpage when substrate 110 is out of shape and internal stress increase.Review the present embodiment, because substrate 110 divided road 110r is separated into several little substrate 111, the divided road 110r of amount of warpage when substrate 110 is out of shape (110r ', 110r ' ') cuts off, and thus reduces overall amount of warpage.Therefore, under the design of the segmentation road 110r (110r ', 110r ' ') of the embodiment of the present invention, even if the sided configuration of semiconductor package part 100 is asymmetric and/or substrate 110 is more and more thinner, its accumulation amount of warpage still can be controlled in one among a small circle or one desired extent.
In one example, segmentation road 110r (110r ', 110r ' ') has a width W 1, such as, be that the quantity of submounts 111 is between 4 to 10 between 8 to 12 microns, and the area of single submounts 111 is less than 12x12 square millimeter, so this is not used to limit the embodiment of the present invention.The area of the width W of segmentation road 110r (110r ', 110r ' '), the quantity of submounts 111 and single submounts 111 can the size of optic placode 110 and/or chip 120 and/or thickness and determine.Segmentation road 110r (110r ', 110r ' ') can linearly, the direction of curve or its combination line segment extends, with the area of the quantity and submounts 111 that obtain the submounts 111 of expection.
In the present embodiment, segmentation road 110r (110r ', 110r ' ') laterally extends from a side, edge 110s (110s1,110s2) to another side, edge 110s (110s1,110s2) along the upper surface 110u of substrate 110, and walks around the first rerouting line layer 1142 (not illustrating) and/or the second rerouting line layer 1152 conductive hole 113 extends; That is, the extension path of segmentation road 110r (110r ', 110r ' '), be such as straight line, curve or its combination line segment, it can not through the first rerouting line layer 1142 (not illustrating) and/or the second rerouting line layer 1152.
Chip 120 with active surface down orientation be located at substrate 110 upper surface 110u on and be electrically connected at the conductive hole 113 of substrate 110.
Please refer to Fig. 2 A, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises substrate 110, chip 120 and primer 130.Fig. 2 A, roughly similar in appearance to Figure 1A, holds this and repeats no more.Its difference is in does not walk around the first rerouting line layer 1142 and the second rerouting line layer 1152 in segmentation road 110r, therefore makes there is direct electrical connection by the first rerouting line layer 1142 and the second rerouting line layer 1152 between arbitrary adjacent submounts 111.
Please refer to Fig. 2 B, it illustrates the vertical view of Fig. 2 A.Fig. 2 B, roughly similar in appearance to Figure 1B, holds this and repeats no more.Although its difference is in laterally split road 110r laterally through the first rerouting line layer 1142 (not illustrating) and the second rerouting line layer 1152 through the second rerouting line layer 1152 in segmentation road 110r, but segmentation road 110r only runs through substrate 110 does not split the first rerouting line layer 1142 (not illustrating) and the second rerouting line layer 1152, first rerouting line layer 1142 (not illustrating) of reservation and/or the second rerouting line layer 1152 can be exposed from the lower surface 110b of substrate 110, and make there is direct electrical connection by the first rerouting line layer 1142 and the second rerouting line layer 1152 between arbitrary adjacent submounts 111.
Please refer to Fig. 3 A to 3F, it illustrates the process drawing of the semiconductor package part 100 of Figure 1A.
As shown in Figure 3A, can adopt is such as that technology (SMT) is pasted on surface, arranges substrate 110 on support plate 10.Substrate 110 comprises at least one base material 112, at least one conductive hole 113, first line layer 114, second line layer 115 and at least one electrical contact 116.On the lower surface 112b that first line layer 114 and the second line layer 115 are formed at base material 112 respectively and upper surface 112u.Support plate 10 comprises adhesive layer 11, and the electrical contact 116 of substrate 110 embeds in adhesive layer 11, uses and is bonding on support plate 10 by substrate 110.
As shown in Figure 3 B, photolithography techniques (coating/exposure/etching/development) can be adopted, form the upper surface 110u of patterning photoresist layer 12 covered substrate 110.Patterning photoresist layer 12 has at least one perforate 12a, and it defines segmentation road 110r(Figure 1A and 1B of follow-up formation) distribution patterns.In this example, perforate 12a laterally walks around conductive hole 113, first rerouting line layer 1142, second rerouting line layer 1152 and the electrical contact 116 of substrate 110.
As shown in Figure 3 C, can adopt is such as chemical etching, as dry ecthing, forms at least one segmentation road 110r and laterally to extend along upper surface 110u and to run through substrate 110, and form several submounts 111 separated from one another by perforate 12a.Owing to being embedded in adhesive layer 11 in the electrical contact 116 of submounts 111, therefore the unlikely disengaging support plate 10 of submounts 111.
As shown in Figure 3 D, remove patterning photoresist layer 12(Fig. 3 C), to expose the second rerouting line layer 1152 and the second dielectric layer 1153.
As shown in FIGURE 3 E, can adopt is such as that technology is pasted on surface, arranges at least one chip 120 on substrate 110.Chip 120 is located on substrate 110 in orientation down with active surface, and be electrically connected at substrate 110 by least one electrical contact 121.
Then, primer 130 is formed between chip 120 and substrate 110, with the electrical contact 121 of coating chip 120.Because segmentation road 110r exposes from the upper surface 110u of substrate 110, primer 130 part flows in segmentation road 110r; But in another example, whole segmentation road 110r can be filled up by primer 130, namely primer 130 can touch adhesive layer 11 via segmentation road 110r.
As illustrated in Figure 3 F, can adopt is such as laser or cutter, and at least all cut P through the second line layer 115, base material 112 and first line layer 114, to be formed at least just like the semiconductor package part 100 shown in Figure 1A in formation.Cutting Road P is more through part adhesive layer 11, and to cut off substrate 110 completely, this kind of cutting mode is called entirely to wear to be cut (full cut).
Please refer to Fig. 4, it illustrates the another kind of process drawing of the semiconductor package part 100 of Figure 1B.The manufacture method of the present embodiment, roughly similar in appearance to the corresponding step of the manufacture method of the semiconductor package part 100 of Fig. 3 A to 3F, is held this and is repeated no more.Its difference is in before formation patterning photoresist layer 12, the second dielectric layer 1143 in substrate 110 forms at least one perforate 1143a, the distribution patterns of the corresponding opening 1143a of distribution patterns of its patterning photoresist layer 12 and the segmentation road 110r of follow-up formation, that is the distribution of this opening 1143a is the segmentation road 110r of corresponding follow-up formation.So, when etching solution removes the material of substrate 110 by the perforate 12a of patterning photoresist layer 12, as long as extend to perforate 1143a from perforate 12a can form segmentation road 110r, the material removal quantity of the second dielectric layer 1143 so can be reduced to save etching required time.
In another example, before formation patterning photoresist layer 12, the second dielectric layer 1153 can form the perforate similar in appearance to perforate 1143a, to reach similar effect.
Please refer to Fig. 5 A to 5B, it illustrates the process drawing of the semiconductor package part 200 of Fig. 2 A.
As shown in Figure 5A, can photolithography techniques be adopted, form the upper surface 110u of patterning photoresist layer 12 covered substrate 110.Patterning photoresist layer 12 has at least one perforate 12a, its definition segmentation road 110r(Fig. 2 A) distribution patterns.In this example, perforate 12a laterally walks around conductive hole 113 and the electrical contact 116 of substrate 110, but can be passed through the first rerouting line layer 1142 and the second rerouting line layer 1152 at least one.
As shown in Figure 5 B, can adopt is such as chemical etching, as dry ecthing, forms at least one segmentation road 110r and runs through substrate 110 and laterally extend to the side, edge of substrate and form several submounts 111 separated from one another.The present embodiment selects the specific etching gas that can not remove metallic circuit material, therefore can retain the first rerouting line layer 1142 and the second rerouting line layer 1152.The present embodiment, on etching parameter controls, is adopt the directivity but the iso mode of increase etching gas that reduce etching gas, etching solution so can be made to remove the material below rerouting line layer toward side direction D1, and form the segmentation road 110r running through substrate 110.That is, undercutting (undercut) amount of etching is increased, the material namely below the removable road floor that reroutes.
All the other steps forming semiconductor package part 200, similar in appearance to the corresponding step forming semiconductor package part 100, are held this and are repeated no more.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.

Claims (20)

1. a semiconductor package part, is characterized in that, comprising:
One substrate, has a segmentation road, and this segmentation road runs through this substrate, and laterally extends to a side, edge of this substrate, makes this substrate form several submounts separated from one another;
One chip, is located on this substrate; And
One primer, is formed between this chip and this substrate.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this substrate has several conductive hole, and this chip is electrically connected those conductive holes, and this segmentation road is laterally walked around those conductive holes and extends to this side, edge.
3. semiconductor package part as claimed in claim 1, it is characterized in that, this substrate comprises:
One rerouting line layer, is electrically connected at a conductive hole of this substrate;
Wherein, this segmentation road is laterally walked around this rerouting line layer and extends to this side, edge.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this substrate comprises:
One rerouting line layer, is electrically connected at a conductive hole of this substrate;
Wherein, this segmentation road laterally extends to this side, edge through this rerouting line layer, but does not split this rerouting line layer.
5. semiconductor package part as claimed in claim 4, it is characterized in that, this rerouting line layer connects those adjacent submounts.
6. semiconductor package part as claimed in claim 1, it is characterized in that, this substrate comprises:
One base material, has a upper surface and a lower surface;
One first dielectric layer, is formed at this lower surface of this base material, and exposes a conductive hole of this substrate;
One rerouting line layer, is formed at this conductive hole exposed; And
One second dielectric layer, to be formed on this rerouting line layer and a part for this rerouting line layer exposed.
7. semiconductor package part as claimed in claim 6, it is characterized in that, this substrate more comprises:
One first dielectric layer, is formed at this upper surface of this base material, and exposes this conductive hole of this substrate;
One rerouting line layer, is formed at this conductive hole exposed; And
One second dielectric layer, to be formed on this rerouting line layer and a part for this rerouting line layer exposed.
8. semiconductor package part as claimed in claim 1, is characterized in that, this primer part is formed at those segmentation roads.
9. semiconductor package part as claimed in claim 6, it is characterized in that, this base material can be glass, silicon, metal, metal alloy or polymer.
10. semiconductor package part as claimed in claim 1, it is characterized in that, this substrate has one first relative side, edge and one second side, edge, and this segmentation road laterally extends to this side, the second edge from this side, the first edge.
11. semiconductor package parts as claimed in claim 1, it is characterized in that, this substrate has one first adjacent side, edge and one second side, edge, this segmentation road laterally extends to this side, the second edge from this side, the first edge.
The manufacture method of 12. 1 kinds of semiconductor package parts, is characterized in that, comprising:
One substrate is set on a support plate;
Form a segmentation road and run through this substrate, and laterally extend to a side, edge of this substrate, make this substrate form several submounts separated from one another;
One chip is set on this substrate;
Form a primer between this chip and this substrate; And
Remove this support plate.
13. manufacture methods as claimed in claim 12, is characterized in that, this primer part is formed at those segmentation roads.
14. manufacture methods as claimed in claim 12, is characterized in that, in arranging this substrate in the step of this support plate, this substrate has several conductive hole; In the step forming this segmentation road, those conductive holes are laterally walked around in this segmentation road; In arranging this chip in the step of this substrate, this chip is electrically connected those conductive holes.
15. manufacture methods as claimed in claim 12, is characterized in that, one first dielectric layer is formed at a surface of this substrate, and exposes a conductive hole of this substrate;
One rerouting line layer is formed at this conductive hole exposed; And
One second dielectric layer to be formed on this rerouting line layer and a part for this rerouting line layer exposed.
16. manufacture methods as claimed in claim 15, is characterized in that, more comprise and are formed at a patterning photoresist layer on this second dielectric layer, and the distribution patterns of this patterning photoresist layer is this segmentation road of corresponding follow-up formation.
17. manufacture methods as claimed in claim 15, is characterized in that, in the step forming this segmentation road, this rerouting line layer is laterally walked around in this segmentation road.
18. manufacture methods as claimed in claim 15, is characterized in that, in the step forming this segmentation road, this segmentation road laterally passes through this rerouting line layer, but does not split this rerouting line layer.
19. manufacture methods as claimed in claim 18, is characterized in that, in the step forming this segmentation road, are use dry ecthing.
20. manufacture methods as claimed in claim 15, is characterized in that, more comprise formation one and are opened on this second dielectric layer, and the distribution of this opening is this segmentation road of corresponding follow-up formation.
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